JP2013089871A - Solid state imaging device wafer, manufacturing method of solid state imaging device, and solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a chip region to be diced in a solid state imaging device wafer, in which the plurality of chip regions, respectively including rear surface radiation type solid state imaging devices, are aligned, thereby downsizing the solid state imaging device.SOLUTION: A solid state image device wafer 100-1 includes: multiple chip regions 200; a division region 300 which is disposed enclosing the chip regions 200; photoelectric conversion parts 20 respectively provided at the chip regions 200; driving circuits, each of which is provided on the surface side opposite to a light receiving surface A relative to the photoelectric conversion part 20 in each chip region 200; device terminals 33, each of which connects with the driving circuit and is led out to the surface side in each chip region 200; and inspection terminals 400, each of which connects with the driving circuit and is exposed to the light receiving surface A side in the division region 300.

Description

  The present technology relates to a solid-state image sensor wafer, a method for manufacturing a solid-state image sensor, and a solid-state image sensor. In particular, a solid-state image sensor wafer in which a plurality of chip regions each having a back-illuminated solid-state image sensor are arranged, a method for manufacturing a solid-state image sensor manufactured using the solid-state image sensor wafer, and a solid obtained by the manufacturing method The present invention relates to an image sensor.

  In the solid-state image sensor, a so-called back-illuminated structure is proposed in which a drive circuit is formed on the front side of the semiconductor substrate and the back side is the light-receiving surface for the purpose of improving photoelectric conversion efficiency and sensitivity to incident light. Has been. Since this backside illumination type has a drive circuit on the surface opposite to the light receiving surface, the light receiving aperture ratio on the light receiving surface can be increased compared to the surface type. For this reason, it is possible to increase the sensitivity and reduce the size of the solid-state imaging device.

  In such a back-illuminated solid-state imaging device, the semiconductor substrate is made thin so that incident light efficiently reaches the photoelectric conversion unit. This requires a support substrate, which is an advantage that other devices can be used as the support substrate. Therefore, in addition to the sensor substrate including the semiconductor substrate on which the photoelectric conversion unit is formed, a circuit substrate on which a drive circuit is formed is prepared, and the circuit substrate is bonded to the surface side opposite to the light receiving surface of the sensor substrate. A dimensional structure has also been proposed.

  By the way, in the manufacturing process of the back-illuminated solid-state imaging device as described above, an inspection for confirming the operation of the solid-state imaging device is performed in a wafer state before the solid-state imaging device is chipped. In order to perform inspection in such a wafer state, a solid-state imaging device wafer and a solid-state imaging device having the following configurations are disclosed.

  A plurality of sensor chips each provided with a back-illuminated solid-state image sensor are arranged on the solid-state image sensor wafer, and a scribe region is provided around the sensor chip. The sensor chip is provided with a first bond pad group, and the scribe region is provided with a second bond pad group, and the first bond pad group and the second bond pad group are electrically connected through a metal extending portion. Has been. Further, an opening that penetrates from the light receiving surface side to the second bonding pad group is provided in the scribe region. Thereby, an inspection needle is inserted into the opening from the light receiving surface side, and an inspection using the second bonding pad group is performed. That is, by adopting a structure in which the inspection needle can be inserted from the light receiving surface side, it is possible to easily inspect the operation of the solid-state imaging device in the wafer state.

  Further, after the inspection in the wafer state as described above, the sensor chip is separated into pieces in a state including the second bonding pad group in the scribe region. As a result, a solid-state imaging device including the separated sensor chip and the second bonding pad group around it is manufactured. The connection between the solid-state imaging device and the outside is achieved using the second bonding pad group (see Patent Document 1).

JP 2007-150283 A (refer to FIGS. 5 and 7 in particular)

  However, the above-described solid-state imaging device has a configuration in which the second bonding pad group used for the inspection in the wafer state is left around the sensor chip as an external connection terminal. For this reason, the solid-state image sensor becomes larger by the amount of the second bond pad group.

  In view of this, the present technology reduces the size of a chip area to be separated into individual solid-state image sensors in a solid-state image sensor wafer in which a plurality of chip areas having back-illuminated solid-state image sensors are arranged, thereby reducing the size of the solid-state image sensor. The purpose is to plan. Furthermore, it aims at providing the manufacturing method of the solid-state image sensor using such a solid-state image sensor wafer, and the solid-state image sensor obtained by the manufacturing method.

  In order to achieve such an object, the solid-state imaging device wafer of the present technology includes a plurality of chip regions and divided regions arranged so as to surround the chip regions. Further, each chip region has a photoelectric conversion unit, a drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit, and a device terminal connected to the drive circuit and drawn to the surface side. Yes. The divided region has an inspection terminal connected to the drive circuit and exposed to the light receiving surface side.

  Moreover, this technique is also a manufacturing method of the solid-state image sensor produced using such a solid-state image sensor wafer, and the following procedure is performed. First, photoelectric conversion parts are formed in a plurality of chip regions provided on the solid-state imaging device wafer. In each chip region, a drive circuit is formed on the surface side opposite to the light receiving surface for the photoelectric conversion unit. Further, in each chip region, a device terminal connected to the drive circuit and drawn out to the surface side is formed. In the divided region arranged so as to surround the chip region, an inspection terminal connected to the drive circuit and exposed on the light receiving surface side is formed. After the above, the solid-state imaging device including the photoelectric conversion unit and the drive circuit connected thereto is inspected using the inspection terminal.

  The present technology is also a solid-state imaging device obtained by the manufacturing method described above, and has the following configuration. The solid-state imaging device includes a photoelectric conversion unit, a drive circuit provided on the surface side opposite to the light receiving surface with respect to the photoelectric conversion unit, a device terminal connected to the drive circuit and drawn to the surface side, And an insulating film covering the entire surface.

  Such a solid-state imaging device wafer includes a chip region including a solid-state imaging device including a device terminal pulled out on the surface side opposite to the light receiving surface, and a divided region including an inspection terminal different from the device terminal. It is the structure provided with. Further, by providing inspection terminals separately from the device terminals, when dividing the chip area provided with the solid-state image sensor, all the divided areas provided with the inspection terminals are removed from the solid-state image sensor wafer. be able to. That is, the chip size to be singulated can be reduced, and the solid-state imaging device can be reduced in size.

  According to the present technology as described above, the chip region including the solid-state image sensor is separated into pieces by removing all the divided regions in the solid-state image sensor wafer. That is, since the divided area including the inspection terminal is removed, the chip size to be separated can be reduced. As a result, it is possible to reduce the size of the solid-state imaging device.

It is a schematic block diagram which shows an example of the solid-state image sensor to which this technique is applied. 1 is a schematic plan view of a solid-state imaging device wafer to which the present technology is applied and an enlarged view of a main part thereof. It is principal part sectional drawing which shows the structure of the solid-state image sensor wafer of 1st Embodiment. It is sectional process drawing (1) which shows the manufacture procedure of the solid-state image sensor of 1st Embodiment. It is sectional process drawing (2) which shows the manufacture procedure of the solid-state image sensor of 1st Embodiment. It is sectional process drawing (3) which shows the manufacture procedure of the solid-state image sensor of 1st Embodiment. It is sectional process drawing (4) which shows the manufacture procedure of the solid-state image sensor of 1st Embodiment. It is principal part sectional drawing which shows the structure of the solid-state image sensor using the solid-state image sensor wafer of 1st Embodiment. It is principal part sectional drawing which shows the structure of the solid-state image sensor wafer of 2nd Embodiment. It is principal part sectional drawing which shows the structure of the solid-state image sensor of 2nd Embodiment. It is principal part sectional drawing which shows the structure of the solid-state image sensor wafer of 3rd Embodiment. It is sectional process drawing (1) which shows the manufacture procedure of the solid-state image sensor of 3rd Embodiment. It is sectional process drawing (2) which shows the manufacture procedure of the solid-state image sensor of 3rd Embodiment. It is sectional process drawing (3) which shows the manufacture procedure of the solid-state image sensor of 3rd Embodiment. It is sectional process drawing (4) which shows the manufacture procedure of the solid-state image sensor of 3rd Embodiment. It is principal part sectional drawing which shows the structure of the solid-state image sensor of 3rd Embodiment.

Hereinafter, embodiments of the present technology will be described in the following order based on the drawings.
1. 1. Schematic configuration example of solid-state image sensor according to embodiment Configuration of Solid-State Image Sensor Wafer of First Embodiment (Example in which inspection terminals are provided in divided areas and copper wiring is cut)
3. 3. Manufacturing method of solid-state imaging device according to first embodiment 4. Solid-state image sensor according to the first embodiment Configuration of Solid-State Imaging Device Wafer of Second Embodiment (Example in which inspection terminals are provided in divided areas and aluminum wiring is cut)
6). 6. Manufacturing method of solid-state imaging device according to second embodiment 7. Solid-state image sensor of the second embodiment Configuration of Solid-State Image Sensor Wafer of Third Embodiment (Example in which inspection terminals are provided on the sensor substrate side of the divided region)
9. 9. Manufacturing method of solid-state imaging device according to third embodiment Solid-State Imaging Device of Third Embodiment In addition, in each embodiment, common constituent elements are denoted by the same reference numerals, and redundant description is omitted.

<1. Schematic Configuration Example of Solid-State Image Sensor of Embodiment>
FIG. 1 shows a schematic configuration of a solid-state image sensor having a three-dimensional structure as an example of a back-illuminated solid-state image sensor to which the present technology is applied. The solid-state imaging device 1 shown in this figure includes a sensor substrate 2 on which photoelectric conversion units are arranged and a circuit substrate 9 that is bonded to the sensor substrate 2 in a stacked state.

  The sensor substrate 2 includes a pixel region 4 in which one surface is a light receiving surface A and a plurality of pixels 3 including a photoelectric conversion unit are two-dimensionally arranged with respect to the light receiving surface A. In the pixel region 4, a plurality of pixel drive lines 5 are wired in the row direction, and a plurality of vertical signal lines 6 are wired in the column direction. One pixel 3 has one pixel drive line 5 and one line. It is arranged in a state of being connected to the vertical signal line 6. Each of these pixels 3 is provided with a photoelectric conversion unit, a charge storage unit, and a pixel circuit composed of a plurality of transistors (so-called MOS transistors) and a capacitor element. A part of the pixel circuit is provided on the surface side opposite to the light receiving surface A. A part of the pixel circuit may be shared by a plurality of pixels.

  The sensor substrate 2 includes a peripheral region 7 outside the pixel region 4. Wiring (not shown) is provided in the peripheral region 7, and the pixel driving lines 5, the vertical signal lines 6, the pixel circuits, and the circuit board 9 are provided on the sensor substrate 2 as necessary. Is connected to a drive circuit provided in

  The circuit board 9 has a vertical drive circuit 10, a column signal processing circuit 11, a horizontal drive circuit 12, and a system control circuit for driving each pixel 3 provided on the sensor board 2 on one side facing the sensor board 2 side. 13 and the like are provided. These drive circuits are connected to the wiring on the sensor substrate 2 side and the pixel circuit. The pixel circuit provided on the surface side of the sensor substrate 2 is also a part of the drive circuit.

<2. Configuration of Solid-State Image Sensor Wafer of First Embodiment>
(Example where inspection terminals are provided in the divided area and the copper wiring is cut)
FIG. 2A is a schematic plan view of a solid-state imaging device wafer to which the present technology is applied as viewed from the light receiving surface side. When the solid-state imaging device wafer 100 is viewed in plan, a plurality of chip regions 200 each having a back-illuminated solid-state imaging device are arranged, and the periphery of the chip region 200 is a divided region 300.
FIG. 2B is an enlarged view of a portion B in FIG. 2A and is an enlarged view of a main part of the solid-state imaging device wafer 100 showing the vicinity of the boundary between the chip region 200 and the divided region 300. Hereinafter, the configuration of the chip area 200 and the divided area 300 will be described.

[Chip area 200]
Each chip region 200 is a region where the solid-state imaging device described with reference to FIG. 1 is formed. In such a chip region, as will be described in detail below, the entire surface of the light receiving surface with respect to the photoelectric conversion unit is covered with an insulating film, and on the surface side opposite to the light receiving surface, a drive circuit and its Device terminals connected to the drive circuit are provided. This device terminal is a terminal for connection between the solid-state imaging device and the outside.

[Division area 300]
The divided region 300 is a region where all is removed by dicing. By performing dicing to remove the divided region 300, the chip region 200 including the solid-state imaging device is separated into pieces. Such a divided region 300 has an inspection terminal 400 and its opening 400a described below.

  The inspection terminal 400 is a terminal used only for inspecting each solid-state imaging device in a wafer state. As shown in the drawing, the inspection terminal 400 has a structure in which a part of the wiring is a pad-shaped terminal in plan view and the wiring part extends toward the chip region 200. Further, the inspection terminal 400 is connected to a wiring that constitutes a driving circuit of the solid-state imaging device.

  The opening 400a is a pad opening that exposes the inspection terminal 400 on the light receiving surface side. With such a configuration, it is possible to inspect operation confirmation of each solid-state imaging device in a wafer state by inserting an inspection needle from the light receiving surface side.

  As described above, the chip region 200 is provided with device terminals for external connection, while the divided region 300 is provided with inspection terminals 400 for inspection in a wafer state. That is, it is characteristic that each region is provided with a terminal specialized for each, rather than providing a terminal that serves both for external connection and for inspection.

[Detailed configuration of solid-state image sensor wafer]
FIG. 3 is a cross-sectional view of the main part showing the configuration of the solid-state imaging device wafer 100-1 of the first embodiment, and is a cross-sectional view taken along line AA of FIG. 2B. Hereinafter, the configuration of the solid-state imaging device wafer 100-1 of the first embodiment will be described based on the cross-sectional view of the main part.

  As shown in FIG. 3, the solid-state image sensor wafer 100-1 of the first embodiment is a solid-state image sensor wafer having a three-dimensional structure in which the sensor substrate 2 and the circuit board 9 are bonded together. Further, when viewed in a plan view, the chip area 200 includes a chip area 200 and a divided area 300, and the chip area 200 including a solid-state imaging element includes a pixel area 4 and a peripheral area 7.

  A wiring layer 2a and a protective film 2b covering the wiring layer 2a are provided on the surface opposite to the light receiving surface A of the sensor substrate 2, that is, the surface facing the circuit board 9 side. On the other hand, a wiring layer 9a and a protective film 9b covering the wiring layer 9a are provided on the surface side of the circuit board 9, that is, the surface facing the sensor board 2 side. A protective film 9 c is provided on the back side of the circuit board 9. The sensor substrate 2 and the circuit board 9 are bonded together between the protective film 2b and the protective film 9b.

  Further, on the back side of the sensor substrate 2, that is, on the light receiving surface A, an antireflection film 41, an interface state suppressing film 42, an etching stop film 43, a wiring groove forming film 44, a wiring 45, a cap film 46, and a light shielding film 47 are formed. Is provided. Further, on the light shielding film 47, a transparent protective film 48, a color filter 49, and an on-chip lens 50 are laminated in this order.

  In the solid-state imaging device wafer 100-1 having the layer configuration as described above, the device terminal 33 is provided on the circuit board 9 in the chip region 200, and is connected to the drive circuit on the circuit board 9 side. On the other hand, the inspection terminal 400 is provided in the wiring layer 9 a of the divided region 300 and is connected to the embedded wiring 37 of the driving circuit extending from the wiring layer 9 a of the chip region 200. Furthermore, the opening 400a is a through hole provided in the divided region 300, having an opening on the light receiving surface A side, and exposing the inspection terminal 400.

  Hereinafter, the details of the above-described solid-state imaging device wafer 100-1 will be described in order of the configuration of each layer of the sensor substrate 2, the configuration of each layer of the circuit board 9, and the configuration of each layer on the light receiving surface A.

[Sensor board 2]
The sensor substrate 2 is obtained by thinning a semiconductor substrate made of, for example, single crystal silicon. A plurality of photoelectric conversion units 20 are arrayed along the light receiving surface A in the pixel region 4 in each chip region 200 of the sensor substrate 2. Each photoelectric conversion unit 20 has a stacked structure of, for example, an n-type diffusion layer and a p-type diffusion layer. The photoelectric conversion unit 20 is provided for each pixel, and a cross section for one pixel is shown in the drawing.

  Further, in the chip region 200 of the sensor substrate 2, on the surface side opposite to the light receiving surface A, the floating diffusion FD composed of an n + -type impurity layer, the source / drain 21 of the transistor Tr, and other elements not shown here are omitted. An impurity layer, element isolation 22 and the like are provided.

  Further, in the chip region 200 of the sensor substrate 2, a through via 23 penetrating the sensor substrate 2 is provided in the peripheral region 7 outside the pixel region 4. The through via 23 is made of a conductive material embedded in a connection hole formed through the sensor substrate 2 via an isolation insulating film 24.

[Wiring layer 2a (sensor substrate 2 side)]
The chip region 200 of the wiring layer 2a provided on the surface of the sensor substrate 2 is formed on the interface side with the sensor substrate 2 via the gate insulating film (not shown here) and the transfer gate TG and the gate electrode of the transistor Tr. 25, and other electrodes not shown here. The transfer gate TG and the gate electrode 25 are covered with an interlayer insulating film 26, and a buried wiring 27 using, for example, copper (Cu) is formed in a groove pattern provided in the interlayer insulating film 26. It is provided as a multilayer wiring. These embedded wirings 27 are connected to each other by vias, and a part thereof is connected to the source / drain 21, the transfer gate TG, and further to the gate electrode 25. Further, the through wiring 23 provided in the sensor substrate 2 is also connected to the embedded wiring 27, and a pixel circuit is configured by the transistor Tr and the embedded wiring 27.

  An insulating protective film 2b is provided on the interlayer insulating film 26 on which the embedded wiring 27 as described above is formed, and the sensor substrate 2 is bonded to the circuit board 9 on the surface of the protective film 2b.

[Circuit board 9]
The circuit board 9 is obtained by thinning a semiconductor substrate made of, for example, single crystal silicon. In the chip region 200 of the circuit board 9, the source / drain 31 of the transistor Tr, the impurity layer not shown here, the element isolation 32, and the like are provided on the surface layer toward the sensor substrate 2 side. Yes.

  Further, the chip region 200 of the circuit board 9 is provided with a device terminal 33 penetrating therethrough. The device terminal 33 is made of a conductive material embedded through a separation insulating film 34 in a connection hole formed through the circuit board 9.

[Wiring layer 9a (circuit board 9 side)]
The chip region 200 of the wiring layer 9a provided on the surface of the circuit board 9 has a gate electrode 35 provided on the interface side with the circuit board 9 via a gate insulating film not shown here, and further It has other electrodes which are not shown here. These gate electrodes 35 and other electrodes are covered with an interlayer insulating film 36, and a buried wiring 37 using, for example, copper (Cu) is formed in a multilayer pattern in a groove pattern provided in the interlayer insulating film 36. It is provided as. These embedded wirings 37 are connected to each other by vias and partly connected to the source / drain 31 and the gate electrode 35. Further, a device terminal 33 provided on the circuit board 9 is also connected to the embedded wiring 37, and a drive circuit is configured by the transistor Tr, the embedded wiring 37, and the like.

  Further, an aluminum wiring 38 is provided on the sensor substrate 2 side of the multilayer wiring. A part of this wiring is provided in the divided region 300 as an inspection terminal 400 described in detail later. Such an aluminum wiring 38 is connected to the buried wiring 37 by a via and is covered with an interlayer insulating film 36. The surface of the interlayer insulating film 36 has a concavo-convex shape corresponding to the aluminum wiring 38, and a flattening film 39 is provided to cover the concavo-convex surface, and the surface of the flattening film 39 is a flat surface.

  The insulating protective film 9b is provided on the planarizing film 39 as described above, and the circuit board 9 is bonded to the sensor substrate 2 on the surface of the protective film 9b. In the circuit board 9, a protective film 9 c that covers the circuit board 9 is provided on the back surface side opposite to the front surface side on which the wiring layer 9 a is provided.

[Antireflection film 41, interface state suppression film 42, etching stop film 43, wiring groove formation film 44, cap film 46 (on light receiving surface A)]
In the peripheral region 7 of the chip region 200, an antireflection film 41, an interface state suppressing film 42, an etching stop film 43, and a wiring groove forming film 44 are formed on the light receiving surface A of the sensor substrate 2 in this order from the light receiving surface A side. Is provided. Further, a wiring 45 is provided in the wiring groove forming film 44, and a cap film 46 is provided to cover the wiring 45.
In the pixel region 4 of the chip region 200, an antireflection film 41, an interface state suppression film 42, and a light shielding film 47 are provided on the light receiving surface A of the sensor substrate 2.
In the divided region 300, an antireflection film 41 and an interface state suppression film 42 are provided on the light receiving surface A of the sensor substrate 2.

  Each layer having the above structure is made of the following materials. The antireflection film 41 is configured using an insulating material having a higher refractive index than silicon oxide, such as hafnium oxide (HfO 2), tantalum oxide (Ta 2 O 5), or silicon nitride. The interface state suppression film 42 is configured using, for example, silicon oxide (SiO 2). The etching stop film 43 is made of a material whose etching selectivity is kept low with respect to the material constituting the upper wiring groove forming film 44, and is made of, for example, silicon nitride (SiN). The wiring trench formation film 44 is configured using, for example, silicon oxide (SiO 2). The cap film 46 is configured using, for example, silicon nitride (SiN).

[Wiring 45 (on light receiving surface A)]
The wiring 45 is provided as an embedded wiring embedded in the wiring groove forming film 44 on the light receiving surface A in the peripheral region 7 of the chip region 200. The wiring 45 is formed integrally with the through via 23 and connects the through vias 23. The upper part of the wiring 45 is covered with a cap film 46.

[Through-through via 23]
In the peripheral region 7 of the chip region 200, the through via 23 penetrates the etching stop film 43, the interface state suppressing film 42, and the antireflection film 41 from the wiring 45 on the light receiving surface A, and further penetrates the sensor substrate 2. The wiring layer 2a is provided. There are a plurality of through vias 23 connected to the embedded wiring 27 of the sensor substrate 2 and the aluminum wiring 38 or the embedded wiring 37 of the circuit board 9.

  The wiring 45 and the through via 23 are connected to the wiring groove and the connection hole through the isolation insulating film 24 that continuously covers the wiring groove formed in the wiring groove formation film 44 and the inner wall of the connection hole at the bottom thereof. Embedded with copper (Cu). Here, the portion of the wiring groove corresponds to the wiring 45, and the portion of the connection hole corresponds to the through via 23. The isolation insulating film 24 is configured using a material having a copper (Cu) diffusion preventing function such as silicon nitride (SiN). In this way, by connecting the through vias 23 with the wiring 45, the embedded wiring 27 of the sensor substrate 2 to which the through vias 23 are respectively connected, and the aluminum wiring 38 or the embedded wiring 37 of the circuit board 9. Electrical connection between them. That is, the drive circuit of the sensor board 2 and the drive circuit of the circuit board 9 are connected.

[Light shielding film 47 (on light receiving surface A)]
The light shielding film 47 is provided above the interface state suppression film 42 on the light receiving surface A in the pixel region 4 of the chip region 200, and includes a plurality of light receiving openings 47 a corresponding to the photoelectric conversion units 20. Such a light shielding film 47 is made of a conductive material having excellent light shielding properties such as aluminum (Al) or tungsten (W), and is provided in a state of being grounded to the sensor substrate 2 at the opening 47b. ing.

[Transparent protective film 48 (on light receiving surface A)]
The transparent protective film 48 is provided in the chip region 200 and the divided region 300 so as to cover the cap film 46 and the light shielding film 47 on the light receiving surface A. The transparent protective film 48 is made of an insulating material and is configured using, for example, an acrylic resin.

[Color filter 49, on-chip lens 50 (on light receiving surface A)]
In the pixel region 4 of the chip region 200, a color filter 49 and an on-chip lens 50 corresponding to each photoelectric conversion unit 20 are further provided on the transparent protective film 48. The color filter 49 is configured with each color corresponding to each photoelectric conversion unit 20. The arrangement of the color filters 49 for each color is not limited. The on-chip lens 50 is configured such that incident light is condensed on each photoelectric conversion unit 20.
On the other hand, in the peripheral region 7 and the divided region 300 of the chip region 200, an on-chip lens film 50 a that is integral with the on-chip lens 50 is provided on the transparent protective film 48.

[Inspection terminal 400, opening 400a]
The inspection terminal 400 is provided on the wiring layer 9 a in the divided region 300 and is a part of the aluminum wiring 38 provided on the wiring layer 9 a in the chip region 200. A part of the embedded wiring 37 constituting the drive circuit of the chip region 200 extends to the divided region 300 and is connected to the inspection terminal 400 by a via.
The opening 400a is a pad opening that is provided in the divided region 300 and exposes the inspection terminal 400 on the light receiving surface A side. That is, the opening 400a is formed by the on-chip lens film 50a, the transparent protective film 48, the interface state suppressing film 42, the antireflection film 41, the sensor substrate 2, the interlayer insulating film 26, the protective film 2b, the protective film 9b, and the planarizing film 39. And the pad opening in which the inspection terminal 400 is exposed at the bottom of the interlayer insulating film 36. In the divided region 300 of the wiring layer 2a that passes through the opening 400a, the embedded wiring 27 constituting the solid-state imaging device is not provided.

<3. Manufacturing Method of Solid-State Image Sensor of First Embodiment>
Next, a manufacturing method of the solid-state imaging device wafer 100-1 having the above-described configuration and a manufacturing method of the solid-state imaging device 1-1 using the same will be described with reference to cross-sectional process diagrams of FIGS.

  As shown in FIG. 4, a plurality of photoelectric conversion units 20 are arranged in the pixel region 4 of each chip region 200 set on the sensor substrate 2, and the source / drain 21, the floating diffusion FD, and other impurities are formed on the sensor substrate 2. Layers and element isolations 22 are formed. Next, the transfer gate TG and the gate electrode 25 are formed on the surface of the sensor substrate 2, and the embedded wiring 27 is formed together with the interlayer insulating film 26 to provide the wiring layer 2a. The upper part of the wiring layer 2a is covered with a protective film. Cover with 2b.

  On the other hand, an impurity layer other than the source / drain 31 and an element isolation 32 are formed in each chip region 200 set on the circuit board 9. Next, the gate electrode 35 is formed on the surface of the circuit board 9, and the embedded wiring 37 is formed together with the interlayer insulating film 36. At this time, the device terminals 33 are embedded and formed from the wiring layer 9 a of the chip region 200 to the circuit board 9. Subsequently, an aluminum wiring 38 connected to the embedded wiring 37 by a via is formed, and this is covered with an interlayer insulating film 36. At this time, a part of the aluminum wiring 38 is provided as the inspection terminal 400 in the divided region 300. The inspection terminal 400 is provided in a state where the embedded wiring 37 extending to the divided region 300 is connected. Thereafter, the interlayer insulating film 36 on the uneven surface is covered with a planarizing film 39, the surface is further planarized to provide a wiring layer 9a, and the upper part of the wiring layer 9a is covered with a protective film 9b.

  After the above, the sensor substrate 2 and the circuit substrate 9 are bonded to each other between the protective film 2b and the protective film 9b so as to correspond to the respective chip regions 200. After the bonding is completed, the light receiving surface A side of the sensor substrate 2 is thinned as necessary. The procedure described above is not particularly limited in procedure, and can be performed by applying a normal bonding technique.

  As shown in FIG. 5, an antireflection film 41, an interface state suppression film 42, an etching stop film 43, and a wiring groove formation film 44 are stacked in this order on the light receiving surface A of the sensor substrate 2. Subsequently, in the peripheral region 7 of the chip region 200, a wiring groove is formed in the wiring groove forming film 44, and a connection hole of each depth penetrating the sensor substrate 2 is formed at the bottom thereof. Next, the isolation insulating film 24 is formed so as to cover the inner walls of the wiring grooves and connection holes, and the embedded wiring 27 or the aluminum wiring 38 is exposed at the bottom of each connection hole, and then a conductive material made of, for example, copper Thus, the wiring groove and the connection hole are embedded integrally. Thus, the plurality of through vias 23 connected to the embedded wiring 27 or the aluminum wiring 38 and the wiring 45 connecting the through vias 23 are formed. Thereafter, a cap film 46 having a diffusion preventing effect on copper (Cu) constituting the wiring 45 is formed in a state of covering the wiring 45 and the wiring groove forming film 44.

  Next, in the pixel region 4 and the divided region 300 of the chip region 200, the cap film 46, the wiring groove forming film 44, and the etching stop film 43 are removed, and the antireflection film 41 and the interface state suppression film 42 are formed on the light receiving surface A. Leave two layers.

  Thereafter, in the pixel region 4 of the chip region 200, an opening 47b is formed in the two layers of the antireflection film 41 and the interface state suppression film 42 at a position on the light receiving surface A that is above the photoelectric conversion unit 20, and the sensor The substrate 2 is exposed. Next, a light shielding film 47 that is grounded to the sensor substrate 2 through the opening 47b is patterned on the light receiving surface A in the pixel region 4 of the chip region 200. At this time, the light-shielding film 47 is formed using a light-shielding conductive material film such as aluminum (Al) or tungsten (W), and is patterned so as to have a light-receiving opening 47 a corresponding to the photoelectric conversion unit 20. It is formed.

  After the above, a transparent protective film 48 made of a light-transmitting material is formed on the entire surface of the chip region 200 and the divided region 300, that is, on the light receiving surface A so as to cover the light shielding film 47 and the cap film 46. At this time, the transparent protective film 48 is formed by a coating method such as a spin coating method. Subsequently, a color filter 49 of each color corresponding to the photoelectric conversion unit 20 is formed on the transparent protective film 48 in the pixel region 4 of the chip region 200, and an on-chip lens 50 corresponding to the photoelectric conversion unit 20 is further formed thereon. Form. When the on-chip lens 50 is formed, at the same time, an on-chip lens film 50 a integrated with the on-chip lens 50 is formed on the peripheral region 7 of the chip region 200 and the transparent protective film 48 in the divided region 300.

Further, the circuit board 9 is thinned by polishing the exposed surface of the circuit board 9, and the device terminals 33 are exposed in the chip region 200. As described above, the solid-state imaging device 1-1 including the device terminal 33 for external extraction is formed in the chip region 200.
Thereafter, a protective film 9 c is formed on the circuit board 9 so as to cover the device terminal 33.

  As shown in FIG. 6, an opening 400 a that exposes the inspection terminal 400 on the light receiving surface A side is formed in the divided region 300. At this time, with the resist pattern not shown here as a mask, the on-chip lens film 50a, the transparent protective film 48, the interface state suppressing film 42, the antireflection film 41, the sensor substrate 2, the interlayer insulating film 26, and the protection The film 2b, the protective film 9b, and the planarizing film 39 are removed by etching in order. Subsequently, the interlayer insulating film 36 is etched to expose the inspection terminal 400, and the etching is finished to complete the opening 400a.

  Next, an inspection needle is inserted into the opening 400 a from the light receiving surface A side, and a probe inspection is performed using the inspection terminal 400. Thus, the probe inspection is performed in the wafer state, and the operation of the solid-state image sensor 1-1 formed in each of the plurality of chip regions in the solid-state image sensor wafer 100-1 is confirmed.

As shown in FIG. 7, after the above-described probe inspection, the divided region 300 is removed by dicing, and the chip region 200 including the solid-state imaging device 1-1 is separated into pieces and left. As described above, the solid-state imaging device 1-1 is completed by the manufacturing method using the solid-state imaging device wafer 100-1.
Also, by this dicing process, the embedded wiring 37 extending to the inspection terminal 400 and connected to the driving circuit of the solid-state imaging device 1-1 is cut, and the section of the embedded wiring 37 is the solid-state imaging device 1-1. Exposed to the side.

  Thereafter, only the solid-state imaging device 1-1 that has been separated into pieces that have passed the probe test described above is finally used, and the process proceeds to the next assembly step. Although illustration is omitted here before the assembly process, an opening is formed in the protective film 9c, and a bump connected to the device terminal 33 through the opening is formed on the protective film 9c. The timing for forming the bumps is not limited to this, and may be before dicing or before probe inspection.

<4. Solid-state imaging device of first embodiment>
FIG. 8 is a principal cross-sectional view showing the configuration of the solid-state imaging device 1-1 of the first embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. Hereinafter, the configuration of the solid-state imaging device 1-1 of the first embodiment will be described based on the cross-sectional view of the main part.

The solid-state image sensor 1-1 corresponds to the chip region 200 of the solid-state image sensor wafer 100-1 described with reference to FIG. That is, as shown in FIG. 8, the sensor substrate 2 and the circuit board 9 are bonded to each other, and in a plan view, the pixel region 4 having the photoelectric conversion unit 20 and the peripheral region having the wiring 45 are provided. 7.
Since it overlaps with the description of the solid-state image sensor wafer 100-1, detailed description thereof will be omitted, and the feature of the solid-state image sensor 1-1 of the first embodiment will be described next.

  As shown in FIG. 8, a wiring layer 2a having a driving circuit and a wiring layer 9a are provided on the surface side opposite to the light receiving surface A of the sensor substrate 2 having the photoelectric conversion unit 20, and the wiring layer 9a is further provided. A circuit board 9 is provided on the side opposite to the sensor board 2. The circuit board 9 is provided with a device terminal 33 connected to the drive circuit of the solid-state imaging device 1-1.

  On the side surface of the solid-state imaging device 1-1, that is, the side surface with respect to the light receiving surface A and the opposite surface, a cross section of the embedded wiring 37 cut by dicing in the manufacturing process is exposed. The embedded wiring 37 is a wiring connected to the drive circuit.

  In the peripheral region 7, a plurality of through vias 23 penetrating the sensor substrate 2 from the light receiving surface A side are provided. The through vias 23 are respectively embedded wiring 27 on the sensor substrate 2 side and aluminum wiring 38 on the circuit board 9 side or embedded. The lead-in wiring 37 is reached. Further, a wiring 45 is provided on the light receiving surface A of the peripheral region 7, and the through vias 23 are connected by this wiring 45. The drive circuit on the sensor substrate 2 side and the drive circuit on the circuit board 9 side are connected by the through via 23 and the wiring 45.

  On the light receiving surface A, the entire surface of the pixel region 4 and the peripheral region 7 is covered with a transparent protective film 48 and an on-chip lens film 50a configured as an insulating film. That is, the wiring 45 provided on the light receiving surface A is similarly covered with the insulating film.

  Further, the bumps 30 connected to the device terminals 33 are provided on the surface opposite to the light receiving surface A. The solid-state imaging device 1-1 and the outside are connected via the bumps 30, and signal extraction of the solid-state imaging device 1-1 is performed.

<Effects of First Embodiment>
The solid-state imaging device wafer 100-1 according to the first embodiment described above includes a plurality of chip regions 200 including the solid-state imaging device 1-1, and divided regions 300 arranged so as to surround the chip region 200. It is a configuration. In the chip region 200, device terminals 33 are provided on the surface side opposite to the light receiving surface A. Further, in the divided region 300, an inspection terminal 400 is provided separately from the device terminal 33, and an opening 400a for exposing the inspection terminal 400 is provided on the light receiving surface A side.

  Thereby, in the manufacturing method of the solid-state image sensor 1-1 produced using such a solid-state image sensor wafer 100-1, an inspection needle is inserted into the opening 400a from the light receiving surface A side, and the inspection terminal 400 is used. A solid-state image sensor can be inspected. That is, it becomes possible to easily inspect the solid-state imaging device in the wafer state.

  Further, in this manufacturing method, the divided region 300 including the inspection terminal 400 is removed by dicing, so that the chip region 200 including the solid-state imaging device 1-1 is singulated. By removing all the divided regions 300 in this way, the chip size obtained as a single piece can be reduced, and the solid-state imaging device 1-1 can be downsized.

  Moreover, the solid-state imaging device 1-1 manufactured as described above has a configuration in which the device terminal 33 is provided on the surface side opposite to the light receiving surface A. That is, no space for providing the device terminal 33 is required on the light receiving surface A side. Thereby, the light-receiving aperture ratio on the light-receiving surface A side is improved, and high sensitivity and miniaturization of the solid-state imaging device 1-1 are achieved.

<5. Configuration of Solid-State Image Sensor Wafer of Second Embodiment>
(Example in which inspection terminals are provided in divided areas and aluminum wiring is cut)
FIG. 9 is a cross-sectional view of the main part showing the configuration of the solid-state imaging device wafer 100-2 of the second embodiment, and is a cross-sectional view taken along line AA of FIG. 2B. Hereinafter, the configuration of the solid-state imaging device wafer 100-2 of the second embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device wafer 100-2 of the second embodiment shown in FIG. 9 is different from the solid-state imaging device wafer 100-1 of the first embodiment described with reference to FIG. The arrangement relationship between the inspection terminal 400 and the embedded wiring 37 in the vicinity of the boundary is the same as in the first embodiment.

  That is, in the second embodiment, the inspection terminal 400 provided in the divided region 300 extends to the chip region 200. The extended inspection terminal 400 and the embedded wiring 37 constituting the drive circuit are connected in the chip region 200.

<6. Manufacturing Method of Solid-State Image Sensor of Second Embodiment>
The manufacturing method of the solid-state imaging device 1-2 manufactured using the solid-state imaging device wafer 100-2 having the above-described configuration is characterized by the following points. A feature is that the inspection terminal 400 extended to the chip region 200 is cut by the dicing process, and a cross section of the inspection terminal 400 is exposed to the side surface of the solid-state imaging device 1-2. Other parts are the same as those of the first embodiment described with reference to FIGS.

<7. Solid-state imaging device of second embodiment>
FIG. 10 is a cross-sectional view of the main part showing the configuration of the solid-state imaging device 1-2 of the second embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. Hereinafter, the configuration of the solid-state imaging device 1-2 of the second embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device 1-2 of the second embodiment shown in FIG. 10 is characterized in that the cross section of the inspection terminal 400 cut by dicing in the manufacturing process is exposed on the side surface of the solid-state imaging device 1-2. . About another structure, it is the same as that of the solid-state image sensor 1-1 of 1st Embodiment demonstrated using FIG.

<Effects of Second Embodiment>
Also in the second embodiment described above, the same effects as in the first embodiment can be obtained.

  In the second embodiment, the cross section of the inspection terminal 400 made of aluminum is exposed on the side surface of the solid-state imaging device 1-2. Since aluminum has better corrosion resistance than copper, the solid-state imaging device 1-2 of the second embodiment described above is more stable.

<8. Configuration of Solid-State Image Sensor Wafer of Third Embodiment>
FIG. 11 is a cross-sectional view of the main part showing the configuration of the solid-state imaging device wafer 100-3 of the third embodiment, and is a cross-sectional view taken along line AA of FIG. 2B. Hereinafter, the configuration of the solid-state imaging device wafer 100-3 of the third embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device wafer 100-3 of the third embodiment shown in FIG. 11 is characterized in that the inspection terminal 400 of the divided region 300 is provided on the sensor substrate 2 side, and details thereof will be described below. . Other configurations are the same as those of the solid-state imaging device wafer 100-1 of the first embodiment described with reference to FIG.

  In the wiring layer 2a on the sensor substrate 2 side of the chip region 200, the embedded wiring 27 is provided as a multilayer wiring. Further, although not shown here, aluminum wiring connected to the embedded wiring 27 by a via is provided on the circuit board 9 side of the multilayer wiring. A part of the aluminum wiring is provided as the inspection terminal 400 in the divided region 300. The inspection terminal 400 extends to the chip region 200 and is connected to the through via 23. Note that the inspection terminal 400 extending to the chip region 200 may be connected to the embedded wiring 27 constituting the driving circuit on the sensor substrate 2 side, although illustration is omitted here.

  Such aluminum wiring and the inspection terminal 400 are covered with the interlayer insulating film 26, and the surface of the interlayer insulating film 26 has an uneven shape. A flattening film 28 is provided to cover the uneven surface, and the surface of the flattening film 28 is flattened. Further, a protective film 2b is provided on the planarizing film 28, and the sensor substrate 2 is bonded to the circuit board 9 on the surface of the protective film 2b.

<9. Manufacturing Method of Solid-State Image Sensor of Third Embodiment>
Next, a manufacturing method of the solid-state image pickup device 1-3 manufactured using the solid-state image pickup device wafer 100-3 having the above-described configuration will be described with reference to cross-sectional process diagrams of FIGS.

  As shown in FIG. 12, a plurality of photoelectric conversion portions 20 are arranged in the pixel region 4 of the chip region 200 in the sensor substrate 2, and the source / drain 21 and the floating diffusion FD on the sensor substrate 2 and other impurity layers and elements are arranged. Isolation 22 is formed. Next, the transfer gate TG and the gate electrode 25 are formed on the surface of the sensor substrate 2, and the embedded wiring 27 is formed together with the interlayer insulating film 26. Next, an aluminum wiring connected to the embedded wiring 27 is formed by a via, and this is further covered with an interlayer insulating film 26. At this time, a part of the aluminum wiring is provided as the inspection terminal 400 in the divided region 300. Further, the inspection terminal 400 extends to the chip region 200 and is provided in a state of being connected to the embedded wiring 27 although not shown here. Thereafter, the interlayer insulating film 26 on the uneven surface is covered with a flattening film 28, the surface is further flattened to provide a wiring layer 2a, and the upper part of the wiring layer 2a is covered with a protective film 2b.

  On the other hand, an impurity layer other than the source / drain 31 and an element isolation 32 are formed in the chip region 200 of the circuit board 9. Next, the gate electrode 35 is formed on the surface of the circuit board 9, and the embedded wiring 37 is formed together with the interlayer insulating film 36. At this time, the device terminals 33 are embedded and formed from the wiring layer 9 a of the chip region 200 to the circuit board 9. Subsequently, an aluminum wiring 38 connected to the embedded wiring 37 by a via is formed, and this is covered with an interlayer insulating film 36. Thereafter, the interlayer insulating film 36 on the uneven surface is covered with a planarizing film 39, the surface is further planarized to provide a wiring layer 9a, and the upper part of the wiring layer 9a is covered with a protective film 9b.

  After the above, the sensor substrate 2 and the circuit board 9 are bonded together between the protective film 2b and the protective film 9b. After the bonding is completed, the light receiving surface A side of the sensor substrate 2 is thinned as necessary. The procedure described above is not particularly limited in procedure, and can be performed by applying a normal bonding technique.

  As shown in FIG. 13, on the light receiving surface A of the sensor substrate 2, an antireflection film 41, an interface state suppression film 42, an etching stop film 43, and a wiring groove forming film 44 are stacked in this order. Subsequently, in the peripheral region 7 of the chip region 200, a wiring groove is formed in the wiring groove forming film 44, and a connection hole of each depth penetrating the sensor substrate 2 is formed at the bottom thereof. Next, the isolation insulating film 24 is formed so as to cover the inner walls of the wiring grooves and the connection holes, and the wiring grooves and the connection holes are integrally embedded with a conductive material made of, for example, copper. As described above, the wiring 45 and the through via 23 connected thereto are provided on the light receiving surface A in the peripheral region 7 of the chip region 200. Thereafter, a cap film 46 having a diffusion preventing effect on copper (Cu) constituting the wiring 45 is formed in a state of covering the wiring 45 and the wiring groove forming film 44.

  Next, in the pixel region 4 and the divided region 300 of the chip region 200, the cap film 46, the wiring groove forming film 44, and the etching stop film 43 are removed, and the antireflection film 41 and the interface state suppression film 42 are formed on the light receiving surface A. Leave two layers.

  Thereafter, in the pixel region 4 of the chip region 200, an opening 47b is formed in the two layers of the antireflection film 41 and the interface state suppression film 42 at a position on the light receiving surface A that is above the photoelectric conversion unit 20, and the sensor The substrate 2 is exposed. Next, a light shielding film 47 that is grounded to the sensor substrate 2 through the opening 47b is patterned on the light receiving surface A in the pixel region 4 of the chip region 200. At this time, the light-shielding film 47 is formed using a light-shielding conductive material film such as aluminum (Al) or tungsten (W), and is patterned so as to have a light-receiving opening 47 a corresponding to the photoelectric conversion unit 20. It is formed.

  After the above, a transparent protective film 48 made of a light-transmitting material is formed on the entire surface of the chip region 200 and the divided region 300, that is, on the light receiving surface A so as to cover the light shielding film 47 and the cap film 46. At this time, the transparent protective film 48 is formed by a coating method such as a spin coating method. Subsequently, a color filter 49 of each color corresponding to the photoelectric conversion unit 20 is formed on the transparent protective film 48 in the pixel region 4 of the chip region 200, and an on-chip lens 50 corresponding to the photoelectric conversion unit 20 is further formed thereon. Form. When the on-chip lens 50 is formed, at the same time, an on-chip lens film 50 a integrated with the on-chip lens 50 is formed on the peripheral region 7 of the chip region 200 and the transparent protective film 48 in the divided region 300.

Further, the circuit board 9 is thinned by polishing the exposed surface of the circuit board 9, and the device terminal 33 is exposed in the chip region 200 to form the device terminal 33. As described above, the solid-state imaging device 1-3 including the device terminal 33 for external extraction is formed in the chip region 200.
Thereafter, a protective film 9 c is formed on the circuit board 9 so as to cover the device terminal 33.

  As shown in FIG. 14, an opening 400 a that exposes the inspection terminal 400 on the light receiving surface A side is formed in the divided region 300. At this time, using the resist pattern not shown here as a mask, the on-chip lens film 50a, the transparent protective film 48, the interface state suppressing film 42, the antireflection film 41, and the sensor substrate 2 are removed by etching in order. Subsequently, the interlayer insulating film 26 is etched, the inspection terminal 400 is exposed, the etching is finished, and the opening 400a is completed.

  Next, an inspection needle is inserted into the opening 400 a from the light receiving surface A side, and a probe inspection is performed using the inspection terminal 400. Thus, the probe inspection is performed in the wafer state, and the operation of the solid-state imaging device 1-3 formed in each of the plurality of chip regions in the solid-state imaging device wafer 100-3 is confirmed.

As shown in FIG. 15, after the probe inspection described above, the divided region 300 is removed by dicing, and the chip region 200 including the solid-state imaging device 1-3 is separated into pieces and left. As described above, the solid-state imaging device 1-3 is completed by the manufacturing method using the solid-state imaging device wafer 100-3.
Further, the cross section of the inspection terminal 400 cut by the dicing process is exposed on the side surface of the solid-state imaging device 1-3.

  After that, only the solid-state imaging device 1-3 that has been separated into pieces that have passed the probe test described above is finally used, and the process proceeds to the next assembly step. Although not shown here before the assembly process, an opening is formed in the protective film 9c, and a bump connected to the device terminal 33 through this opening is formed on the protective film 9c. The timing for forming the bumps is not limited to this, and may be before dicing or before probe inspection.

<10. Solid-State Image Sensor of Third Embodiment>
FIG. 16 is a cross-sectional view of the main part showing the configuration of the solid-state imaging device 1-3 of the third embodiment, and is a cross-sectional view near the boundary between the pixel region 4 and the peripheral region 7 in FIG. The solid-state imaging device 1-3 corresponds to the chip region 200 of the solid-state imaging device wafer 100-3 described with reference to FIG. Hereinafter, the configuration of the solid-state imaging device 1-3 according to the third embodiment will be described based on the cross-sectional view of the main part.

  The solid-state imaging device 1-3 according to the third embodiment shown in FIG. 16 is characterized in that a cross section of the inspection terminal 400 cut by dicing in the manufacturing process is exposed on the side surface. About another structure, it is the same as that of the solid-state image sensor 1-1 of 1st Embodiment demonstrated using FIG.

<Effects of Third Embodiment>
Also in the third embodiment described above, the same effect as in the first embodiment can be obtained.

  In the third embodiment, the inspection terminal 400 is provided on the sensor substrate 2 side. Accordingly, the opening 400a is shallower than the configuration in which the inspection terminal 400 is provided on the circuit board 9 side, the opening is easily formed, and the inspection needle 400 can be easily accessed. Become.

  In the above-described third embodiment, the configuration in which the inspection terminal 400 is cut by dicing has been described as an example of the configuration in which the inspection terminal 400 is provided on the sensor substrate 2 side. However, the present invention is not limited thereto, and may be combined with a configuration in which the embedded wiring made of copper is cut by dicing as in the first embodiment.

In addition, this technique can also take the following structures.
(1)
Multiple chip areas;
A divided region arranged to surround the chip region;
A photoelectric conversion unit provided in each of the chip regions;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit in each chip region;
Device terminals connected to the drive circuit and drawn out to the surface side in each chip region;
A solid-state imaging device wafer, comprising: an inspection terminal connected to the drive circuit and exposed to the light receiving surface side in the divided region.

(2)
The solid-state imaging device wafer according to (1), wherein an opening for exposing the inspection terminal is provided on the light receiving surface side.

(3)
The solid-state imaging device wafer according to (1) or (2), wherein an entire surface of the light receiving surface is covered with an insulating film in the chip region.

(4)
A sensor substrate having the photoelectric conversion unit and the drive circuit;
The solid-state imaging device according to any one of (1) to (3), further comprising: a circuit board that includes the drive circuit, the device terminal, and the inspection terminal, and is attached to the sensor substrate. Wafer.

(5)
Forming photoelectric conversion portions in a plurality of chip regions provided on the solid-state imaging device wafer;
Forming a drive circuit on the surface side opposite to the light receiving surface for the photoelectric conversion unit in each chip region;
In each chip region, forming a device terminal connected to the drive circuit and drawn out to the surface side;
Forming a test terminal connected to the drive circuit and exposed to the light-receiving surface side in a divided region arranged to surround the chip region;
Inspecting a solid-state image sensor provided with the photoelectric conversion unit and the drive circuit connected to the photoelectric conversion unit using the inspection terminal.

(6)
After the inspection, dicing is performed to remove the divided regions including the inspection terminals and to separate the chip regions including the solid-state imaging device. (5) Method.

(7)
When forming the inspection terminal,
After forming the inspection terminal connected to the drive circuit in the divided region,
An opening for exposing the inspection terminal to the light receiving surface side is formed. (5) or (6).

(8)
A bump connected to the device terminal is formed on a surface opposite to the light receiving surface in the chip region. The method for manufacturing a solid-state imaging element according to any one of (5) to (7).

(9)
A photoelectric conversion unit;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit;
Device terminals connected to the drive circuit and drawn out to the surface side;
A solid-state imaging device comprising: an insulating film covering the entire surface of the light receiving surface.

(10)
The solid-state imaging device according to (9), wherein a cross section of the wiring connected to the drive circuit is exposed on the light receiving surface and a side surface with respect to the surface.

(11)
A sensor substrate having the photoelectric conversion unit and the drive circuit;
The solid-state imaging device according to (9) or (10), further comprising: a circuit board that includes the drive circuit and the device terminal and is attached to the sensor substrate.

(12)
A plurality of through vias that penetrate the sensor substrate from the light receiving surface side and are connected to the driving circuit of the sensor substrate or the driving circuit of the circuit substrate in a peripheral region located outside the pixel region having the photoelectric conversion unit When,
The solid-state imaging device according to any one of (9) to (11), further comprising: a wiring provided on the light receiving surface in the peripheral region and connecting the through vias.

(13)
The solid-state imaging device according to (12), wherein the wiring is covered with the insulating film.

(14)
Bumps connected to the device terminals are provided on the surface. The solid-state imaging device according to any one of (9) to (13).

  DESCRIPTION OF SYMBOLS 1,1-1, 1-2, 1-3 ... Solid-state image sensor, 2 ... Sensor substrate, 4 ... Pixel area | region, 7 ... Peripheral area | region, 9 ... Circuit board, 20 ... Photoelectric conversion part, 23 ... Through-via, 30 ... Bump, 33 ... Device terminal, 45 ... Wiring, 100, 100-1, 100-2, 100-3 ... Solid-state imaging device wafer, 200 ... Chip area, 300 ... Division area, 400 ... Inspection terminal, 400a ... Opening

Claims (14)

Multiple chip areas;
A divided region arranged to surround the chip region;
A photoelectric conversion unit provided in each of the chip regions;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit in each chip region;
Device terminals connected to the drive circuit and drawn out to the surface side in each chip region;
A solid-state imaging device wafer, comprising: an inspection terminal connected to the drive circuit and exposed to the light receiving surface side in the divided region. The solid-state imaging device wafer according to claim 1, wherein an opening for exposing the inspection terminal is provided on the light receiving surface side. The solid-state imaging device wafer according to claim 1, wherein an entire surface of the light receiving surface is covered with an insulating film in the chip region. A sensor substrate having the photoelectric conversion unit and the drive circuit;
The solid-state imaging device wafer according to claim 1, further comprising: a circuit board that includes the drive circuit, the device terminal, and the inspection terminal and is attached to the sensor substrate. Forming photoelectric conversion portions in a plurality of chip regions provided on the solid-state imaging device wafer;
Forming a drive circuit on the surface side opposite to the light receiving surface for the photoelectric conversion unit in each chip region;
Forming device terminals connected to the drive circuit and led out to the surface side in each chip region;
Forming a test terminal exposed to the light-receiving surface side in a divided region that is connected to the drive circuit and is arranged to surround the chip region;
Inspecting a solid-state image sensor provided with the photoelectric conversion unit and the drive circuit connected to the photoelectric conversion unit using the inspection terminal. The solid-state imaging device manufacturing method according to claim 5, wherein after the inspection, dicing is performed to remove the divided regions including the inspection terminals and to separate each chip region including the solid-state imaging device. Method. When forming the inspection terminal,
After forming the inspection terminal connected to the drive circuit in the divided region,
The method for manufacturing a solid-state imaging device according to claim 5, wherein an opening is formed to expose the inspection terminal to the light receiving surface side. The method for manufacturing a solid-state imaging element according to claim 5, wherein a bump connected to the device terminal is formed on a surface opposite to the light receiving surface in the chip region. A photoelectric conversion unit;
A drive circuit provided on the surface side opposite to the light receiving surface for the photoelectric conversion unit;
Device terminals connected to the drive circuit and drawn out to the surface side;
A solid-state imaging device comprising: an insulating film covering the entire surface of the light receiving surface. The solid-state imaging device according to claim 9, wherein a cross section of the wiring connected to the drive circuit is exposed on the light receiving surface and a side surface with respect to the surface. A sensor substrate having the photoelectric conversion unit and the drive circuit;
The solid-state imaging device according to claim 9, further comprising: a circuit board that includes the drive circuit and the device terminal and is attached to the sensor substrate. A plurality of through vias that penetrate the sensor substrate from the light receiving surface side and are connected to the driving circuit of the sensor substrate or the driving circuit of the circuit substrate in a peripheral region located outside the pixel region having the photoelectric conversion unit When,
The solid-state imaging device according to claim 9, further comprising: a wiring provided on the light receiving surface in the peripheral region and connecting the through vias. The solid-state imaging device according to claim 12, wherein the wiring is covered with the insulating film. The solid-state imaging device according to claim 9, wherein a bump connected to the device terminal is provided on a surface opposite to the light receiving surface.