WO2006127696A3 - Process for fabricating an integrated circuit package - Google Patents

Process for fabricating an integrated circuit package Download PDF

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Publication number
WO2006127696A3
WO2006127696A3 PCT/US2006/019897 US2006019897W WO2006127696A3 WO 2006127696 A3 WO2006127696 A3 WO 2006127696A3 US 2006019897 W US2006019897 W US 2006019897W WO 2006127696 A3 WO2006127696 A3 WO 2006127696A3
Authority
WO
WIPO (PCT)
Prior art keywords
leadframe strip
integrated circuit
circuit package
strip
fabricating
Prior art date
Application number
PCT/US2006/019897
Other languages
French (fr)
Other versions
WO2006127696A2 (en
Inventor
Chun Ho Fan
Neil Mclellan
Wing Him Lau
Emily Shui Ming Tse
Original Assignee
Asat Ltd
Chun Ho Fan
Neil Mclellan
Wing Him Lau
Emily Shui Ming Tse
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/137,973 external-priority patent/US7247526B1/en
Application filed by Asat Ltd, Chun Ho Fan, Neil Mclellan, Wing Him Lau, Emily Shui Ming Tse filed Critical Asat Ltd
Publication of WO2006127696A2 publication Critical patent/WO2006127696A2/en
Publication of WO2006127696A3 publication Critical patent/WO2006127696A3/en

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract

A process for fabricating an integrated circuit package. At least a first side of a leadframe strip (22) is selectively etched to define portions of a die attach pad (24) and at least one row of contacts (26) adjacent the die attach pad (24). A carrier strip (28) is laminated to the first side of the leadframe strip (22) and a second side of the leadframe strip (22) is selectively etched to thereby define a remainder of the die attach pad (24) and the at least one row of contacts ( 26). A semiconductor die (30) is mounted to the die attach pad, on the second side of the leadframe strip (22) and the semiconductor die (30) is wire bonded to ones of the contacts. The second side of the leadframe strip (22) is encapsulating, including the semiconductor die (30) and wire bonds (32), in a molding material ( 34). The carrier strip ( 28) is removed from the leadframe strip (22) and the integrated circuit package ( 20) is singulated from a remainder of the leadframe strip ( 22).
PCT/US2006/019897 2005-05-25 2006-05-24 Process for fabricating an integrated circuit package WO2006127696A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/137,973 2005-05-25
US11/137,973 US7247526B1 (en) 1998-06-10 2005-05-25 Process for fabricating an integrated circuit package

Publications (2)

Publication Number Publication Date
WO2006127696A2 WO2006127696A2 (en) 2006-11-30
WO2006127696A3 true WO2006127696A3 (en) 2009-04-16

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PCT/US2006/019897 WO2006127696A2 (en) 2005-05-25 2006-05-24 Process for fabricating an integrated circuit package

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
US6777265B2 (en) * 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6956942B2 (en) * 2002-09-18 2005-10-18 Sbc Properties, L.P. Multi-modal address book

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
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