WO2006127696A2 - Process for fabricating an integrated circuit package - Google Patents

Process for fabricating an integrated circuit package Download PDF

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Publication number
WO2006127696A2
WO2006127696A2 PCT/US2006/019897 US2006019897W WO2006127696A2 WO 2006127696 A2 WO2006127696 A2 WO 2006127696A2 US 2006019897 W US2006019897 W US 2006019897W WO 2006127696 A2 WO2006127696 A2 WO 2006127696A2
Authority
WO
WIPO (PCT)
Prior art keywords
strip
integrated circuit
leadframe strip
circuit package
fabricating
Prior art date
Application number
PCT/US2006/019897
Other languages
French (fr)
Other versions
WO2006127696A3 (en
Inventor
Chun Ho Fan
Neil Mclellan
Wing Him Lau
Emily Shui Ming Tse
Original Assignee
Asat Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/137,973 external-priority patent/US7247526B1/en
Application filed by Asat Ltd. filed Critical Asat Ltd.
Publication of WO2006127696A2 publication Critical patent/WO2006127696A2/en
Publication of WO2006127696A3 publication Critical patent/WO2006127696A3/en

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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Definitions

  • the present invention relates in general to integrated circuit packaging and more particularly to an improved process for fabricating an integrated circuit package, that includes unique features that allow gang testing of integrated circuit packages and etching to provide mold interlock.
  • LPCC Leadless Plastic Chip Carrier
  • a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die attach pad (paddle) and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die attach pad is eliminated, thereby increasing the moisture sensitivity performance.
  • thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard.
  • the exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required).
  • a localized etch process is provided for the improved manufacture of the LPCC IC package.
  • the leadframe strip is subjected to a partial etch on one or both of the top and bottom surfaces in order to create a pattern of contact leads (pads) and a die attach pad (paddle).
  • This method of manufacture provides many advantages including contact pads that stand off from the remainder of the package.
  • a process for fabricating an integrated circuit package At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad.
  • a carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts.
  • a semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts.
  • the second side of the leadframe strip is encapsulated, including the semiconductor die and wire bonds, in a molding material.
  • the carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.
  • the unique etch-back process results in mold interlocking features for better board mount reliability. Also, the mold interlocking features are provided by an etch- back process that results in decreased cost of manufacture as compared to plate-up processes.
  • the package is manufactured using a carrier strip that is laminated to the leadframe strip.
  • the carrier strip provides increased rigidity and support for the leadframe strip during manufacture.
  • the contacts of the leadframe strip are electrically isolated by etching prior to mounting the semiconductor die to the die attach pad. This permits gang testing of the individual units of the strip prior to singulation.
  • package handling and testing time is reduced.
  • Figures 1 to 11 show processing steps for fabricating an integrated circuit package in accordance with an embodiment of the present invention.
  • Figures 12A and 12B show an additional process step for fabricating an integrated circuit package in accordance with another embodiment of the present invention.
  • FIG. 1 to 11 Reference is first made to Figures 1 to 11 to describe a process for fabricating an integrated circuit package, indicated generally in Figure 11 by the numeral 20.
  • the process includes selectively etching at least a first side of a leadframe strip 22 to define portions of a die attach pad 24 and at least one row of contacts 26 adjacent the die attach pad 24.
  • a carrier strip 28 is laminated to the first side of the leadframe strip 22 and a second side of the leadframe strip 22 is selectively etched to thereby define a remainder of the die attach pad 24 and the at least one row of contacts 26.
  • a semiconductor die 30 is mounted to the die attach pad 24, on the second side of the leadframe strip 22 and the semiconductor die 30 is wire bonded to ones of the contacts 26.
  • the second side of the leadframe strip 22 is encapsulated, including the semiconductor die 30 and wire bonds 32, in a molding material 34.
  • the carrier strip 28 is removed from the leadframe strip 22 and the integrated circuit package 20 is singulated from a remainder of the leadframe strip 22.
  • FIG. 1 A and 1 B there is shown a top view and a partial sectional side view, respectively, of a copper (Cu) panel substrate which forms the raw material of the leadframe strip 22.
  • the leadframe strip 100 is divided into a plurality of sections, each of which incorporates a plurality of leadframe units in an array (e.g.
  • FIG. 2A and 2B a top view and a sectional side view of the leadframe strip 22 are shown in which, the first side of the leadframe strip 22 is selectively etched to partially define the die attach pad 24 and the contacts 26.
  • the selective etch is carried out by coating the first and second sides of the leadframe strip 22 with a layer of photo- imageable etch resist such as photo-imageable epoxy.
  • the etch resist is spin coated on the leadframe strip 22, selectively exposed with an ultraviolet light using a photo-tool, and the exposed portions are removed.
  • the etch resist is thereby patterned to provide pits on the leadframe strip 22, in which selected portions of the leadframe strip 22 are exposed.
  • the leadframe strip 22 is then immersion or pressurized spray etched to partially define the die attach pad 24 and the contacts 26 and the etch resist is stripped away using conventional means.
  • the etch resist is also exposed at selected positions prior to etching, to provide tooling holes in the leadframe strip 22 after etching.
  • the resulting leadframe strip 22 is shown in Figures 2A and 2B. In the present embodiment, two rows of contacts 26 that circumscribe the die attach pad 24, are formed.
  • curved undercut regions are created during etching to form the etched-down portions of the leadframe strip 22. These undercut regions act as mold interlocking features for mold compound adherence. Portions of the leadframe strip 22, on the etched-down portions, connect the partially defined die attach pad 24 and the contact pads 26 to the remainder of the leadframe strip 22 and thereby act as temporary tie bars 36 for holding the leadframe strip 22 together.
  • the second side of the leadframe strip 22 is then selectively plated with a metal 38 that permits wire bonding thereto and acts as an etch resistant layer, using known selective plating techniques ( Figures 3A and 3B).
  • Suitable plating metals include, for example, Silver (Ag), Nickel and Palladium (Ni/Pd) and Nickel and Gold (Ni/Au).
  • the selectively plated metal 38 is plated on the second side of the leadframe strip 22 to cover the die attach pad 24, the contacts 26, and peripheral portions of the package, around the tooling holes.
  • the carrier strip 28 is prepared for laminating to the first side of the leadframe strip 22.
  • the carrier strip 28 is made of any suitable metal, such as copper, and is plated with metal on both sides thereof, prior to lamination, as shown in the sectional side view of Figure 4.
  • the metal plating on the carrier strip 28 facilitates lamination of the carrier strip to the first side of the leadframe strip 22 and acts as an etch resist.
  • Suitable plating materials include, for example, tin (Sn), solder, palladium (Pd), silver (Ag) and nickel then gold (Ni/Au).
  • the carrier strip 28 includes tooling holes for aligning with the tooling holes of the leadframe strip 22.
  • the tooling holes of the carrier strip 28 are aligned with and are larger than the tooling holes of the leadframe strip 22, as shown.
  • the semiconductor die 30 is conventionally mounted by, for example, epoxy or other suitable means, to the die attach pad 24, on the second side of the leadframe strip 22. Wire bonds 32 are then bonded between the semiconductor die 30 and the contacts 26.
  • the leadframe strip 22 is then molded in the molding material 34 using a modified mold with a bottom cavity being a flat plate, and subsequently cured ( Figures 7A and 7B).
  • Figures 7A and 7B the second side of the leadframe strip 22, the semiconductor die 30 arid the wire bonds 32 are encapsulated in the molding material 34, as shown.
  • the carrier strip 28 is removed from the first side of the leadframe strip 22 by heating and pulling the carrier strip 28 from the leadframe strip 22 ( Figures 8A and 8B). As shown in Figure 8B, upon removal of the carrier strip 28, metal plating from the carrier strip is left on the metal contacts 26 and die attach pad 24. Because the temporary tie bars 36 have been etched away ( Figures 6A and 6B) and the carrier strip 28 is removed, the die attach pad 24 and the contacts 26 are electrically isolated.
  • the contacts 26 and die attach pad 24 are electrically isolated prior to singulating, thereby permitting gang testing of the individual units. Testing is then carried out on the unit prior to singulation ( Figure 9).
  • Singulation of the individual unit from the full leadframe strip 22 is then performed either by saw singulation or by die punching ( Figures 1 OA and 10B).
  • the individual unit is singulated by saw singulation, the cutting path of the cutting wheel saw being indicated in ghost outline in Figures 10A and 10B.
  • Clearly a portion of the selectively etched leadframe that does not become part of the integrated circuit package 20 is saw singulated away, resulting in the integrated circuit package shown in the sectional side view of Figure 11.
  • FIGS 12A and 12B show one alternative embodiment in which an additional step is carried out to mount a plurality of contact balls 40 on the first side of the leadframe strip 22, on the contacts 26 and the die attach pad 24.
  • the contact balls 40 are mounted to the contacts 26 and the die attach pad 24 after the carrier strip 28 is removed from the first side of the leadframe strip 22 and prior to singulation of the individual unit from the full leadframe strip 22.
  • the contact balls 40 In mount the contact balls 40 to the contacts 26, the contact balls 40, in the form of solder balls, are placed on the contacts 26 and the die attach pad 24 using known pick and place technique and reflowed using known reflow technique.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A process for fabricating an integrated circuit package. At least a first side of a leadframe strip (22) is selectively etched to define portions of a die attach pad (24) and at least one row of contacts (26) adjacent the die attach pad (24). A carrier strip (28) is laminated to the first side of the leadframe strip (22) and a second side of the leadframe strip (22) is selectively etched to thereby define a remainder of the die attach pad (24) and the at least one row of contacts ( 26). A semiconductor die (30) is mounted to the die attach pad, on the second side of the leadframe strip (22) and the semiconductor die (30) is wire bonded to ones of the contacts. The second side of the leadframe strip (22) is encapsulating, including the semiconductor die (30) and wire bonds (32), in a molding material ( 34). The carrier strip ( 28) is removed from the leadframe strip (22) and the integrated circuit package ( 20) is singulated from a remainder of the leadframe strip ( 22).

Description

PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT PACKAGE •
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation-in-part of United States Patent Application Serial No. 10/765,192, filed January 28, 2004, entitled Leadless Plastic Chip Carrier with Standoff Contacts and Die Attach Pad and a continuation-in-part of United States Patent Application Serial No. 09/802,678, filed March 9, 2001 , which is a continuation-in-part of United States Patent Application Serial No. 09/288,352, now United States Patent 6,498,099, issued December 24, 2002, which is a continuation-in-part of United States Patent Application Serial No. 09/095,803, now United States Patent No. 6,299,200, issued May 8, 2001.
FIELD OF THE INVENTION
[0002] The present invention relates in general to integrated circuit packaging and more particularly to an improved process for fabricating an integrated circuit package, that includes unique features that allow gang testing of integrated circuit packages and etching to provide mold interlock.
BACKGROUND OF THE INVENTION
[0003] According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die pads (attach paddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a motherboard, thereby limiting the packaging density of such prior art devices.
[0004] In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants' LPCC methodology, a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die attach pad (paddle) and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die attach pad is eliminated, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features of outer leads is eliminated and no outer leads are necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior art methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants1 own prior art LPCC process are discussed in Applicants' United States Patent No. 6,229,200, issued May 8, 2001 , the contents of which are incorporated herein by reference.
[0005] According to Applicants' United States Patent No. 6,498,099, the contents of which are incorporated herein by reference, a localized etch process is provided for the improved manufacture of the LPCC IC package. The leadframe strip is subjected to a partial etch on one or both of the top and bottom surfaces in order to create a pattern of contact leads (pads) and a die attach pad (paddle). This method of manufacture provides many advantages including contact pads that stand off from the remainder of the package.
[0006] In Applicants' own United States Patent Application No. 09/802,678, the contents of which are incorporated herein by reference, a plate-up process is used to form contact pads and a die attach pad. The unique plate-up process results in columnar shaped contact pads with a "mushroom cap" or rivet-shaped top for mold interlocking to provide superior board mount reliability.
[0007] Further improvements in integrated circuit packaging are still desirable and are driven by industry demands for increased thermal and electrical performance and decreased size and cost of manufacture. SUMMARY OF THE INVENTION
[0008] According to one aspect of the present invention, there is provided a process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts. A semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts. The second side of the leadframe strip is encapsulated, including the semiconductor die and wire bonds, in a molding material. The carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.
[0009] Advantageously, the unique etch-back process results in mold interlocking features for better board mount reliability. Also, the mold interlocking features are provided by an etch- back process that results in decreased cost of manufacture as compared to plate-up processes.
[0010] In one aspect, the package is manufactured using a carrier strip that is laminated to the leadframe strip. Advantageously, the carrier strip provides increased rigidity and support for the leadframe strip during manufacture. In another aspect, the contacts of the leadframe strip are electrically isolated by etching prior to mounting the semiconductor die to the die attach pad. This permits gang testing of the individual units of the strip prior to singulation. Advantageously, package handling and testing time is reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The present invention will be better understood with reference to the drawings and to the following description, in which:
[0012] Figures 1 to 11 show processing steps for fabricating an integrated circuit package in accordance with an embodiment of the present invention; and
[0013] Figures 12A and 12B show an additional process step for fabricating an integrated circuit package in accordance with another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0014] Reference is first made to Figures 1 to 11 to describe a process for fabricating an integrated circuit package, indicated generally in Figure 11 by the numeral 20. The process includes selectively etching at least a first side of a leadframe strip 22 to define portions of a die attach pad 24 and at least one row of contacts 26 adjacent the die attach pad 24. A carrier strip 28 is laminated to the first side of the leadframe strip 22 and a second side of the leadframe strip 22 is selectively etched to thereby define a remainder of the die attach pad 24 and the at least one row of contacts 26. A semiconductor die 30 is mounted to the die attach pad 24, on the second side of the leadframe strip 22 and the semiconductor die 30 is wire bonded to ones of the contacts 26. The second side of the leadframe strip 22 is encapsulated, including the semiconductor die 30 and wire bonds 32, in a molding material 34. The carrier strip 28 is removed from the leadframe strip 22 and the integrated circuit package 20 is singulated from a remainder of the leadframe strip 22.
[0015] The process for fabricating the integrated circuit package 20 will now be further described with reference to the Figures. Referring first to Figures 1 A and 1 B, there is shown a top view and a partial sectional side view, respectively, of a copper (Cu) panel substrate which forms the raw material of the leadframe strip 22. As discussed in detail in Applicant's United States patent no. 6,229,200, the contents of which are incorporated herein by reference, the leadframe strip 100 is divided into a plurality of sections, each of which incorporates a plurality of leadframe units in an array (e.g. 3 x 3 array, 5 x 5 array, etc.) Only one portion of one such unit is depicted in the Figures, the remainder of the one unit and portions of adjacent units being indicated by stippled lines. It will be appreciated that the adjacent units of the leadframe strip are similar to the unit depicted. Reference is made to a single unit throughout the following description for the purpose of simplicity. It will be understood, however, that the process described is carried out in the fabrication of several units in the array.
[0016] Referring to Figures 2A and 2B, a top view and a sectional side view of the leadframe strip 22 are shown in which, the first side of the leadframe strip 22 is selectively etched to partially define the die attach pad 24 and the contacts 26. The selective etch is carried out by coating the first and second sides of the leadframe strip 22 with a layer of photo- imageable etch resist such as photo-imageable epoxy. The etch resist is spin coated on the leadframe strip 22, selectively exposed with an ultraviolet light using a photo-tool, and the exposed portions are removed. The etch resist is thereby patterned to provide pits on the leadframe strip 22, in which selected portions of the leadframe strip 22 are exposed. The leadframe strip 22 is then immersion or pressurized spray etched to partially define the die attach pad 24 and the contacts 26 and the etch resist is stripped away using conventional means. In the present embodiment, the etch resist is also exposed at selected positions prior to etching, to provide tooling holes in the leadframe strip 22 after etching. The resulting leadframe strip 22 is shown in Figures 2A and 2B. In the present embodiment, two rows of contacts 26 that circumscribe the die attach pad 24, are formed.
[0017] As shown in Figure 2B, curved undercut regions are created during etching to form the etched-down portions of the leadframe strip 22. These undercut regions act as mold interlocking features for mold compound adherence. Portions of the leadframe strip 22, on the etched-down portions, connect the partially defined die attach pad 24 and the contact pads 26 to the remainder of the leadframe strip 22 and thereby act as temporary tie bars 36 for holding the leadframe strip 22 together.
[0018] The second side of the leadframe strip 22 is then selectively plated with a metal 38 that permits wire bonding thereto and acts as an etch resistant layer, using known selective plating techniques (Figures 3A and 3B). Suitable plating metals include, for example, Silver (Ag), Nickel and Palladium (Ni/Pd) and Nickel and Gold (Ni/Au). As shown in Figures 3A and 3B, the selectively plated metal 38 is plated on the second side of the leadframe strip 22 to cover the die attach pad 24, the contacts 26, and peripheral portions of the package, around the tooling holes.
[0019] Next, the carrier strip 28 is prepared for laminating to the first side of the leadframe strip 22. The carrier strip 28 is made of any suitable metal, such as copper, and is plated with metal on both sides thereof, prior to lamination, as shown in the sectional side view of Figure 4. The metal plating on the carrier strip 28 facilitates lamination of the carrier strip to the first side of the leadframe strip 22 and acts as an etch resist. Suitable plating materials include, for example, tin (Sn), solder, palladium (Pd), silver (Ag) and nickel then gold (Ni/Au). As shown in Figure 4, the carrier strip 28 includes tooling holes for aligning with the tooling holes of the leadframe strip 22. The tooling holes of the carrier strip 28 are aligned with and are larger than the tooling holes of the leadframe strip 22, as shown.
[0020] Referring to Figures 5A and 5B which show a top view and a sectional side view, respectively, of the leadframe strip 22, lamination of the carrier strip 28 to the first side of the leadframe strip 22 is carried out using suitable means such as using elevated temperature and pressure. Alternatively, lamination is carried out using an appropriate flux and solder reflow technique. [0021] After lamination of the carrier strip 28 to the first side of the leadframe strip 22, the second side of the leadframe strip is selectively etched as shown in Figures 6A and 6B. Thus, exposed portions of the leadframe strip 22 that are not covered by the selectively plated metal 38 are subjected to a suitable etchant to define the remainder of the die attach pad 24 and the contacts 26. It will be apparent that the temporary tie bars 26 are etched away.
[0022] The semiconductor die 30 is conventionally mounted by, for example, epoxy or other suitable means, to the die attach pad 24, on the second side of the leadframe strip 22. Wire bonds 32 are then bonded between the semiconductor die 30 and the contacts 26. The leadframe strip 22 is then molded in the molding material 34 using a modified mold with a bottom cavity being a flat plate, and subsequently cured (Figures 7A and 7B). Thus, the second side of the leadframe strip 22, the semiconductor die 30 arid the wire bonds 32 are encapsulated in the molding material 34, as shown.
[0023] Next, the carrier strip 28 is removed from the first side of the leadframe strip 22 by heating and pulling the carrier strip 28 from the leadframe strip 22 (Figures 8A and 8B). As shown in Figure 8B, upon removal of the carrier strip 28, metal plating from the carrier strip is left on the metal contacts 26 and die attach pad 24. Because the temporary tie bars 36 have been etched away (Figures 6A and 6B) and the carrier strip 28 is removed, the die attach pad 24 and the contacts 26 are electrically isolated.
[0024] As stated above, the contacts 26 and die attach pad 24 are electrically isolated prior to singulating, thereby permitting gang testing of the individual units. Testing is then carried out on the unit prior to singulation (Figure 9).
[0025] Singulation of the individual unit from the full leadframe strip 22 is then performed either by saw singulation or by die punching (Figures 1 OA and 10B). In the present embodiment, the individual unit is singulated by saw singulation, the cutting path of the cutting wheel saw being indicated in ghost outline in Figures 10A and 10B. Clearly a portion of the selectively etched leadframe that does not become part of the integrated circuit package 20 is saw singulated away, resulting in the integrated circuit package shown in the sectional side view of Figure 11.
[0026] Alternatives and variations to the above-described process are possible. Reference is made to Figures 12A and 12B which show one alternative embodiment in which an additional step is carried out to mount a plurality of contact balls 40 on the first side of the leadframe strip 22, on the contacts 26 and the die attach pad 24. The contact balls 40 are mounted to the contacts 26 and the die attach pad 24 after the carrier strip 28 is removed from the first side of the leadframe strip 22 and prior to singulation of the individual unit from the full leadframe strip 22. To mount the contact balls 40 to the contacts 26, the contact balls 40, in the form of solder balls, are placed on the contacts 26 and the die attach pad 24 using known pick and place technique and reflowed using known reflow technique.
[0027] The present invention has been described by way of examples. Modifications and variations to the embodiments described herein may occur to those skilled in the art. For example, rather than using a pick and place technique, solder paste printing followed by known reflow technique is also possible. Other modifications and variations are also possible, all of which are within the sphere and scope of the present invention.

Claims

CLAIMSWhat is claimed is:
1. A process for fabricating an integrated circuit package, comprising: selectively etching at least a first side of a leadframe strip to define portions of a die attach pad and at least one row of contacts adjacent said die attach pad; laminating a carrier strip to said first side of said leadframe strip; selectively etching a second side of said leadframe strip to thereby define a remainder of said die attach pad and said at least one row of contacts; mounting a semiconductor die to said die attach pad, on the second side of the leadframe strip; wire bonding said semiconductor die to ones of said contacts; encapsulating said second side of said leadframe strip, including said semiconductor die and wire bonds, in a molding material; removing said carrier strip from said leadframe strip; and singulating said integrated circuit package from a remainder of said leadframe strip.
2. The process for fabricating the integrated circuit package according to claim 1 , further comprising: plating said carrier strip for facilitating lamination, prior to laminating said carrier strip to said first side of said leadframe strip.
3. The process for fabricating the integrated circuit package according to claim 2, wherein said plating comprises plating metal on both sides of said carrier strip for facilitating lamination.
4. The process for fabricating the integrated circuit package according to claim 2, wherein said plating comprises plating one of Tin (Sn), Solder, Palladium (Pd), Silver (Ag) and layers of Nickel and Gold (Ni/Au) on said leadframe strip.
5. The process for fabricating the integrated circuit package according to claim 3, wherein said metal that is plated on both sides of said carrier strip, acts as an etch resistant layer.
6. The process for fabricating the integrated circuit package according to claim 1 , wherein said selectively etching said second side of said leadframe strip comprises: selectively plating an etch-resistant metal on said second side of said leadframe strip; and etching said leadframe strip to thereby define said remainder of said die attach pad and said at least one row of contacts.
7. The process for fabricating the integrated circuit package according to claim 1 , wherein said selectively etching said first side of said leadframe strip comprises: depositing a photo-imageable etch-resistant mask on said first side of said leadframe strip; imaging and developing said mask to expose portions of said first side of said leadframe strip; and etching said first side of said leadframe strip to thereby etch said exposed portions of said first side of said leadframe strip.
8. The process for fabricating the integrated circuit package according to claim 1 , wherein said laminating said carrier strip to said first side of said leadframe strip comprises laminating at elevated temperature and pressure.
9. The process for fabricating the integrated circuit package according to claim 1 , wherein said laminating said carrier strip to said first side of said leadframe strip comprises laminating using solder reflow technique.
10. The process for fabricating the integrated circuit package according to claim 1, wherein said removing said carrier strip comprises: heating the laminated strip and pulling said carrier strip from said leadframe strip.
11. The process for fabricating the integrated circuit package according to claim 1 , further comprising: mounting a plurality of contact balls on said first side of said leadframe strip, in the form of a ball grid array, ones of said contact balls being electrically connected to ones of said contacts, after removing said carrier strip and prior to singulating.
12. The process for fabricating the integrated circuit package according to claim 1 , further comprising solder reflowing after removing the carrier strip.
13. The process for fabricating the integrated circuit package according to claim 1 , wherein the carrier strip is a metal strip.
14. The process for fabricating the integrated circuit package according to claim 1 , further comprising gang testing individual units of the leadframe strip prior to singulating said integrated circuit package.
PCT/US2006/019897 2005-05-25 2006-05-24 Process for fabricating an integrated circuit package WO2006127696A2 (en)

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US11/137,973 US7247526B1 (en) 1998-06-10 2005-05-25 Process for fabricating an integrated circuit package

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
US6777265B2 (en) * 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6956942B2 (en) * 2002-09-18 2005-10-18 Sbc Properties, L.P. Multi-modal address book

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
US6777265B2 (en) * 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6956942B2 (en) * 2002-09-18 2005-10-18 Sbc Properties, L.P. Multi-modal address book

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