WO2006126166A2

WO2006126166A2 - Demodulator for multi-mode receiver

Info

Publication number: WO2006126166A2
Application number: PCT/IB2006/051636
Authority: WO
Inventors: Brian Minnis; Anthony D. Sayers
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-05-27
Filing date: 2006-05-22
Publication date: 2006-11-30
Also published as: WO2006126166A3

Abstract

A demodulator (70) suitable for a multi-mode receiver (101 ), demodulates (50, 520, 540, 550) samples having a sample rate not an integer multiple of the specified data rate of a current mode, and decimates (60, 160, 545) demodulated samples to reduce an average sample rate by a fractional factor to the specified data rate. By demodulating at a sample rate unrelated to the specified data rate, and using such fractional reduction after the demodulation, the fractional resampling before demodulation, can be saved and demodulation now uses higher quality samples free of timing jitter, introduced by the fractional resampling. It can be implemented in software and dispenses with analogue circuitry for fractional-N clock generation and filtering.

Description

DESCRIPTION

DEMODULATOR FOR MULTI-MODE RECEIVER

This invention relates to demodulators for multi-mode receivers, to receivers, to apparatus having such receivers, and to mobile devices having such demodulators, and to methods of demodulating.

Multi-band mobile devices (for example mobile phones that are capable of operating within the same system but in different bands) are already commonplace today. For example, quad-band GSM phones are being widely sold and operated throughout most of Europe, America and Asia. Multi-band receivers need RF band filters and local oscillators to suit each band. The local oscillators can be implemented by a known fractional-N synthesiser integrated on a single integrated circuit with one external crystal. For all bands, the same baseband signals are produced and demodulated, in other words, there is one mode.

It is known for a phone to operate in different radio bands, but also to operate under more than one different radio system, for example GSM (Global System for Mobile Communication) and UMTS (Universal Mobile Telecommunication System), with different base band demodulation (called multi-mode). One problem that arises in this case is the need for multiple clock rates corresponding to the different bit rates of the different modes, which increases complexity and tends to demand the use of multiple crystals. For example, the GSM standard requires clocks to operate at 270.833 kHz or at multiples thereof, whereas the Wideband Coded Divisional Multiplexed Access standard (WCDMA) uses 3.84 MHz or multiples thereof. Because there is no easy harmonic relationship between the various clock frequencies, there is no direct way of deriving one frequency from another, so multi-mode devices, operating using different standards, need to have separate crystal oscillators capable of generating different clock reference frequencies. As the crystals cannot be integrated easily, this conflicts with the need for greater integration to reduce size and manufacturing costs of portable devices, such as mobile telephones.

An article entitled "Sample Rate Conversion for Software Radio" and was published in IEEE Communications Magazine in August 2000, by T. Hentschel and G. Fettweis, describes a fractional Sample Rate Converter (SRC) for a software definable radio, with examples supporting GSM, IS-95 and UMTS. This fractional SRC allows analogue to digital conversion to be done at a fixed clock rate for different communication standards, because a conversion to the sample rate, dedicated to each communication standard, is carried out following analogue to digital conversion, and before demodulation. Subsequent demodulation of the samples having the desired sample rate related to the specified data rate, can be carried out by software.

European patent application 1304808 indicates that such fractional sample rate conversion requires using both interpolation and decimation functions. To reduce computational load, this document proposes a multi-rate analogue to digital converter coupled to a single crystal oscillator as a reference clock and having at least two separate channels arranged to sample and convert input data at two differing clock rates, each channel deriving a clock signal from said reference clock. Associated with each of the channels is a sigma-delta converter. Each sigma-delta converter is configured to operate at a different frequency channel. Each frequency can support a particular standard. A first converter can handle a WCDMA signal and a second converter can handle a GSM signal. Each sigma-delta converter comprises a clock divider, a sigma-delta modulator, a low pass filter, and a resampling switch, clocked by an output of a clock synthesizer. Resampling the signal in each channel avoids the need for introducing a new high frequency reference clock and associated problems of harmonic interference between several high frequency reference clocks. It is an object of the invention to provide improved apparatus or methods. According to a first aspect of the invention, there is provided a demodulator suitable for a multi-mode receiver, the modes each having a specified data rate and using a specified modulation, the demodulator being arranged to receive samples of a signal modulated with data, the samples having a sample rate not an integer multiple of the specified data rate of a current mode, and being arranged to demodulate the samples according to their mode and output samples of a demodulated signal having an average output sample rate which is a fractional factor of the input sample rate and is an integer multiple or integer factor of the specified data rate. By carrying out the demodulation on samples at a rate unrelated to the specified data rate, and using such fractional reduction after the demodulation, the considerable computational effort of fractional resampling before demodulation, necessarily involving interpolation and filtering, can be saved. The demodulation is now done on higher quality samples free of the noise and distortion, notably timing jitter, introduced by the fractional resampling. Thus consequential degradation in signal to noise ratio and thus receiver sensitivity can be reduced. Interpolation and filtering can be reduced or avoided. Deferring the fractional reduction also makes it easier to implement more of a receiver in software for more flexibility. All this can outweigh any greater computational load in the demodulator caused by using a higher sample rate. Also it retains the capability of the known arrangement discussed above, of handling many modes with differing specified rates without needing extra hardware for generating unrelated clocks, such as external crystal oscillators or analogue circuitry for fractional-N clock generation and filtering. This helps save space and power consumption.

Demodulation is intended to encompass any processing which recovers information from a modulated carrier, at baseband or IF, and can encompass spread spectrum demodulation, frequency or amplitude demodulation, any type of decoding including decryption, error correction, equalisation and so on. The samples can be multi level or binary digital samples or time discrete analogue samples for example. An additional feature of some embodiments is the demodulator being arranged to receive baseband signals. This is currently a commercially valuable part of the signal processing, though in principle digital demodulation at other stages such as IF or RF demodulation may be appropriate and similar advantages could apply.

Another such additional feature is the demodulator being arranged to use a plurality of input samples to generate each demodulated sample before reduction of the sample rate.

Another such additional feature is a decimator for selecting from the demodulated samples, and a means arranged to control the decimator by alternating between two or more decimation factors such that a time averaged decimation factor corresponds to the reduction by a fractional factor.

Another such additional feature is the demodulator being implemented by software. This implies the samples no longer need to be processed in real time, they can be stored and processed later, but still they have an implied sample rate which can be changed by decimation. Such implementation can make it easier to use the same processing resources for different modes.

Another such additional feature is the demodulation comprising despreading using a despreading code which is resampled to match the sample rate before reduction.

Another such additional feature is the data being in the form of symbols, the demodulator being arranged to demodulate the signal at a sample rate oversampled compared to a specified symbol rate, and to decimate the oversampled signal to output symbols at the specified symbol rate. The symbols can be decoded subsequently to derive data bits. Other subsequent operations can include for example other coding schemes, error correction, and so on.

A receiver can be provided having the demodulator. Another additional feature is an analogue to digital converter for providing the samples to the demodulator. Another alternative is a sampler for providing time discrete analogue samples. Another such additional feature is the analogue to digital converter comprising a sigma-delta converter. As this involves oversampling, it is suitable to be combined with the other features, and helps reduce power consumption. Another such additional feature is a channel filter before the demodulator. This can encompass a digital channel filter or a time discrete analogue filter for use with analogue samples

Another such additional feature is one or more stages of integer decimation before the demodulator. Another such additional feature is there being no fractional decimation before the demodulator.

Another such additional feature is the receiver having clock signals for different modes generated by integer divisions without any fractional clock generator. An additional feature of some embodiments is RF circuitry for deriving the input signal as a complex IF signal from an RF input. In principle, the above features could also be applied to an RF demodulator or a baseband demodulator for example.

Another aspect provides apparatus having the multi-mode receiver, a transmitter circuit, and an antenna.

Another aspect provides a mobile battery powered device having the apparatus. Notably the simpler processing requirements can enable smaller size and reduced power consumption, which are particularly useful in such apparatus. In principle, the demodulator or receiver can be incorporated in base stations.

Another aspect provides a method of demodulating samples corresponding to one of several modes, the modes each having a specified data rate and using a specified modulation, the method having the steps of determining a current mode, demodulating samples according to their mode, the samples having a sample rate not an integer multiple of the specified data rate of the current mode, and outputting samples of a demodulated signal having an average sample rate which is a fractional factor of the input sample rate and is an integer multiple or integer factor of the specified data rate.

Any of the additional features can be combined together or with any of the aspects of the invention, as would be apparent to those skilled in the art. Other advantages may be apparent to those skilled in the art, especially over other prior art not known to the inventors.

Embodiments of the invention will now be described by way of example only, and with reference to the accompanying drawings, in which: Figure 1 shows an embodiment of a demodulator;

Figure 2 shows another embodiment;

Figure 3 shows another embodiment;

Figure 4 shows resampling a spreading code for use with some embodiments; Figure 5 shows an embodiment of a receiver;

Figure 6 shows another embodiment of a receiver; and

Figure 7 shows an embodiment of a mobile device having a receiver.

Figure 1 shows a first embodiment. Input samples having a sample rate F_s not integer related to a specified data rate F_data of the current mode, are fed to the demodulator 70. A demodulation process 50 is carried out and the demodulated samples are fed to a fractional reduction stage 60. Here the sample rate is reduced by a fractional factor to an output sample rate F_sout which is so that it is integer related to the specified data rate for the mode (Fs₀Ut= nFdata, 1/nF_data_> where n is an integer). The demodulation and fractional reduction can be adapted by means of a mode control input 55 or 65 respectively to suit the different modulation types or different data rates of different modes. These basic features can be implemented in many ways, in software or hardware, in real time or batch processing, for any type of demodulation, and any rate, to suit a wide variety of applications. Such demodulation can be useful for streams of samples from any source, for any purpose, and can be incorporated before or after other layers of processing such as filtering or other layers of demodulation including decoding. The sample rate F_s (≠ nF_data ) of the samples being demodulated can be an arbitrary sample rate which makes clock generation for a multi-mode or multi- rate device much easier. Different modes can encompass modes using the same type of modulation, and differing only in data rate for example.

Figure 2 shows another embodiment of a demodulator 70, in this case as part of a baseband processing arrangement of a receiver. The input samples are complex values (I and Q) at baseband, representing a baseband interface (BBI). A despread and demodulation part 440 feeds complex value symbols to a symbol filter 450. The output of this is fed to a symbol recovery part 460 for implementing the fractional reduction in sample rate. The despread and demodulation part 440 is fed by a clock derived from a common system clock 485 by a divider 480 which divides by an integer factor m. The symbol recovery part 460 outputs symbols sampled at the symbol rate in this case and thus having a sample rate, F_Sym- This output can be generated either by generating a fractional clock, or more simply by sampling alternately at two or more rates integer related to the system clock by factors n and n+1 as shown by part 470. The resulting average sample rate F sym can be arranged to be fractionally related to the input sample rate and be integer related to the specified data rate, by controlling the alternating to bias it appropriately. This can be achieved by a derived symbol clock as will be explained below. This average rate is sufficient in many cases, because the demodulation is done ahead of the fractional rate reduction, so the sensitivity of the demodulation to such timing jitter is not a problem. If the demodulator is implemented in software, the clocks are not derived as signals, but represented in the form of sample timing information.

Figure 3 shows another embodiment, using the example of UMTS demodulation. In this case the demodulation operation is exemplified by a multiplication 540 followed by an integration 550. A resampled chip sequence 520 is fed to the multiplier 540 at a sample rate matching the input sample rate

F_s, 4 MHz in this case. The results of the multiplication are integrated in part 550 with the preceding 133 results. The output is decimated by part 545 by a factor of 133 or 134 so as to achieve a fractional decimation down to the specified symbol rate for UMTS of 30 ksymbol/s. While it is possible to calculate each integration separately and output one and ignore the 132 or 133 that are not used, in practice it is more efficient to calculate the integrations using a known incremental algorithm that uses the last integration result to calculate the next integration with a minimum of calculation. Scrambling can be added to this but is not shown for the sake of clarity. The decimator 545 is controlled by an output from the symbol clock recovery part 523. This output can provide an indication of the boundaries of a symbol. This means there may be considerable jitter on this signal, compared to an equivalent generated by a fractional resampler or other means. All are intended to be encompassed by the term "means arranged to control the decimator". In cases where the timing jitter cannot be tolerated, then filtering can be carried out.

Figure 4 shows in schematic form a process for producing the resampled chip sequence for use with the embodiment of Figure 3 or other embodiments. For a UMTS chip sequence, the example shows a resampling from the specified 3.68MHz up to 4 MHz. At step 600 scrambling codes are spread, at step 610 they are concatenated, and at step 620 they are resampled by a fractional factor of F_s/F_chj_P where F_chj_P is the specified rate of the chip sequence before resampling. This brings the codes to the same sample rate as the input samples, ready for the demodulation. This process usually need not be carried on continuously, if the chip sequence repeats regularly, the resampled sequence can be stored and read out repeatedly.

Figure 5 shows an embodiment of a receiver, in this case a radio receiver for receiving RF. The antenna signal is fed from antenna 135 via a conventional RF multiplexer 125 for band selection to an RF (radio) chip. The radio front end is also conventional using typically a single down-conversion to a zero or near-zero intermediate frequency (IF). This can be implemented following conventional practice using mixers 115 fed by a local oscillator (not shown). Next the I and Q channels are processed separately by an analogue to digital converter (ADC) 105 and decimation arrangement 110 with channel filtering. This can be similar to that used in previous receiver architectures, with the exception that the ADC is clocked at significantly higher rate and preferably at the same rate for all modes. The over-sampling ratio at the ADC is likely to be greater than 100 and will not in general be an exact integer multiple of any chip, bit or symbol rate. There is an option to reduce the clock rate at the ADC by a small integer ratio should this be beneficial but in any case, the reduced clock rate would be derived from the same system clock 140 with a simple divider 40. The I and Q channel samples are fed to the demodulator 50 and subsequent fractional decimator 160 which can be implemented as discussed above. The fractional decimator 160 needs no post filtering generally. It uses a clock or selection signal generated at a rate related to the specified rate by a clock recovery circuit 420. This corresponds to the above mentioned symbol clock recovery 523, but is not limited to recovering symbols; it can be any multiple or factor of the data rate, depending on the mode. If generated by software using samples at the input sample rate, then the clock or selection can be an indication of which of a numbered series of samples to select, and this will have some timing jitter resulting from the fractional nature. This can be filtered out if necessary or ignored if the fractional reduction is considerable.

Figure 6 shows another embodiment showing an example of a receiver path in more detail. In this case, the ADC is a sigma-delta type 605. After the

ADC, integer decimation is performed in a succession of filters, including a decimation filter 610, and an N-mode digital channel filter 615. These filters give the receiver the majority of its selectivity. This decimation is followed by various other digital functions such as frequency de-rotation 620 for GSM, DC offset correction and automatic gain control (AGC) 625. They are clocked at the sub-divided system clock frequency, as is the baseband signal that is fed across the baseband interface (BBI) to the software modem for baseband processing. To provide the clocks, a crystal 685 typically feeds a local oscillator LO, and a DLL (delay lock loop) 680. A VCO 690 runs at 416MHz in this example, and is optionally divided down by integer factors by dividers 695 and 696 as desired to clock the ADC and successive integer decimators in the receiver chain as described. Usually the BBI provides a convenient boundary between hardware circuitry (such as ASICs or programmable hardware), and functions more effectively carried out in software, (for example running on conventional DSP or general purpose microprocessor circuitry).

Beyond the BBI, the rest of the demodulation process 670 is performed at a non-integer multiple of the chip, bit or symbol rate. This can include such processes as the rake receiver, the equaliser and the symbol filtering, as desired to suit the specifications of the modes. At no time does the receiver need to generate a new clock at precisely the symbol rate pertaining to the mode in question. All that is required is that symbols are extracted at the correct average rate, and this can be viewed as either a process of fractional symbol recovery or fractional clock recovery. As discussed above, fractional reduction produces symbols at the sample rate related to the specified data rate, optionally using a clock recovery part 420, or other decimation controller. Symbols can be collected in a memory buffer at the end of the receiver chain and held ready for export to higher layers 675 or whatever the relevant peripheral device might be (e.g. a vocoder, a graphics processor, some data application software, etc). The current mode can be detected by the higher layers or set by user input for example.

Notably only one clock is needed for all modes throughout system, and no symbol rate clock need be generated from the system clock if a symbol clock is recovered, represented by samples having a rate unrelated to the specified data rate and yet having an average rate corresponding to the specified symbol rate.

An absence of a symbol rate clock implies no need for strictly fractional decimation, since an average by alternating between two or more adjacent integer decimations can suffice. This exploits the principle that symbols don't need an exact time assignment, and can tolerate some timing jitter. The radio runs basically on a single, high, system clock frequency whatever radio system it is attempting to implement. This can be in the region of 400 MHz for a radio receiver capable of all 2G, 3G, WLAN and digital video standards. Possible modes and their frequencies include:

1. Digital Video Broadcasting - Handheld, DVB-H (590 MHz),

2. Advanced Mobile Phone System, AMPS (850 MHz). 3. Global System for Mobile Communication, GSM (900 MHz and others).

4. Digital Cellular System, DCS1800 (1800 MHz).

5. Personal Communication System, PCS (1850 MHz).

6. Universal Mobile Telecommunications System, UMTS (WCDMA) (2050 MHz and others).

7. Global Positioning System, GPS (1575 MHz).

8. Bluetooth™ (2.4 GHz).

9. Wireless Local Area Network, WLAN (IEEE 802.11 ) (2.4-5.5 GHz).

10. Ultra Wide Band, UWB (3.1-4.8 GHz). 11. WiMAX (IEEE 802.16) (many frequencies).

This new clock regime should not for most modes alter in principle the software baseband modem handling the demodulation. Notably the rake receiver in the UMTS mode should run at a clock speed which is higher than the chip rate. The chip sequence should also be resampled at the higher rate. In a conventional receiver, a UMTS demodulator has an input clock frequency which is an integer multiple of the chip rate (i.e. 15.36 MHz = 4 x 3.84 MHz). The rake correlation is done at precisely the chip rate and then integration takes place over exactly 128 chips to recover the symbols at 30 ksymbol/s. The decimated sample stream can be derived by integer division of a 400 MHz system clock. The system clock would have been locked to a lower-frequency reference oscillator making use of a single crystal. In this particular case, the chip multiplication rate in the rake correlator is 4 MHz, which is nearly but not quite equal to the 3.84 MHz of a conventional system.

If the input sampling rate to a channel filter such as a root-raised-cosine (RRC) filter is 16 MHz, subsequent decimation by 4 takes the sampling rate down to 4 MHz for the correlator and then there is a pseudo random selection of 133 or 134 samples over which integration takes place for the symbol extraction at 30 ksymbol/s. Note that the symbols appear at the output at an average rate of 30 ksymbol/s. An alternative is to omit the decimation by 4 before the rake correlator. Hence, the multiplication in the correlator runs at 16 MHz and the integration of the chips in the symbol filter takes place over a mixture of 533 and 534 samples. It should be noted that in both systems, the chip sequence must be resampled at 4 MHz and 16 MHz respectively. This does not alter the timing of the boundaries of the chip sequence. It only changes the number of samples used to represent the chip sequence. It should also be noted that the increased sampling rate in the correlator should not cause a significant increase in power consumption compared to the rest of the receiver since by virtue of the chip sequence being a series of 1s and -1s, the multiplication involves only sign changes.

For the embodiment with a clock speed of 4 MHz at the rake correlator, a degradation in sensitivity of about 0.5 dB has been observed, which reduces to a degradation of only <0.1 dB for the embodiment with a 16 MHz clock. These degradations are associated with the effective jitter that appears on the clock due to the resampling of the chip sequence and due to the fractional nature of the symbol filtering. Notably they are small and would probably be of the same order as or smaller than those resulting from clock jitter and a finite timing resolution in the rake for a conventional system.

Figure 7 shows an application of the receiver in a mobile multimedia device 101. A multi-mode receiver 102 is combined with a transmit path by a transmitter and RF combiner 100. It is shown in radio communication with a GSM base station 104 having a transceiver 108. Another mode is provided by a radio path from a transceiver 110 of a WLAN network base station 105, coupled to a WLAN 109. Clearly many other applications are possible in radio and non radio applications.

Above-described embodiments of a multi-mode radio receiver for use in mobile terminals such as multi-band mobile phones can operate with more than one radio standard. They can achieve a wider roaming capability by switching mode as opposed to merely switching frequency band. The need for multiple clock rates corresponding to the different bit rates of the different modes, can be achieved without needing multiple crystals. To implement a multi-mode radio with a single crystal and therefore a single system clock, the clock frequencies for the digital processing parts for the different modes are generated so that the single system clock can have a frequency completely unrelated to the chip, bit and symbol rates of any given radio standard.

Also described is a receiver system in which a single high-frequency clock can be used to implement the analogue to digital conversion and digital demodulation processes, for a multiplicity of modes. The system incorporates an ADC (typically a sigma-delta type) which is clocked at a high frequency and whose output is decimated in a decimation filter by an integer division ratio. The rest of the demodulation process is also implemented at a convenient integer ratio of the system, high-frequency clock. At no instance in the signal processing chain is it necessary to generate a clock which is an integer multiple of the chip, bit or symbol rates applying to any given radio standard. Hence, new modes can be added without any need to modify the clock generation scheme. Only a single crystal is needed to create the system clock.

These embodiments can avoid generating a large number of clock frequencies for different radio systems using different oscillators and/or reference crystals. It thus can save a large number of components and result in a simpler, lower-cost device. It also gives the radio system a better multi- mode capability, allowing it accommodate the introduction of new modes without necessitating the re-design of the clock generation system. This can enable a much more adaptable, open, more future-proof radio pipe, a simpler clock generator for all modes, a simplified ADC design with no significant impact on power consumption. Adaptability is improved by effectively shifting functions into digital or software domains. A simplified pre demodulation decimation and channel filter regime is not constrained by particular chip/bit/symbol rates. A reduced range of sampling rates is present on the baseband interface to the software modem.

In the present specification and claims the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Further, the word "comprising" does not exclude the presence of other elements or steps than those listed.

The inclusion of reference signs in parentheses in the claims is intended to aid understanding and is not intended to be limiting. From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the art of receiver design and the art of digital signal processing and which may be used instead of or in addition to features already described herein.

Claims

1. A demodulator (70) suitable for a multi-mode receiver, the modes each having a specified data rate and using a specified modulation, the demodulator being arranged to receive samples of a signal modulated with data, the samples having a sample rate not an integer multiple of the specified data rate of a current mode, and being arranged to demodulate (50) the samples according to their mode and output (60) demodulated samples having an average output sample rate which is a fractional factor of the input sample rate and is an integer multiple or integer factor of the specified data rate.

2. The demodulator (70) of claim 1 , arranged (550) to use a plurality of input samples to generate each demodulated sample before reduction of the sample rate.

3. The demodulator (70) of any preceding claim and having a decimator (545) for selecting from the demodulated samples, and a means (523) arranged to control the decimator by alternating between two or more decimation factors such that a time averaged decimation factor corresponds to the reduction by a fractional factor.

4. The demodulator (70) of any preceding claim and arranged to carry out despreading (540, 550) using a despreading code (520) having a sample rate to match the sample rate before reduction.

5. The demodulator (70) of any preceding claim and the data being in the form of symbols, the demodulator being arranged to demodulate the signal at a sample rate oversampled compared to a specified symbol rate, and to decimate the oversampled signal to output symbols at the specified symbol rate.

6. A receiver having the demodulator (70) of any preceding claim.

7. The receiver of claim 6 and having one or more stages of integer decimation (610) before the demodulator.

8. The receiver of claim 6 or 7 and having no fractional decimation before the demodulator.

9. The receiver of any of claims 6 to 8 and having integer divisor means (40, 695, 696) for generating clock signals for different modes without any fractional clock generator.

10. Apparatus (101 ) having the multi-mode receiver of any of claims 6 to 9, and a transmitter circuit (100), and an antenna (135).

11. A method of demodulating samples corresponding to one of several modes, the modes each having a specified data rate and using a specified modulation, the method having the steps of determining a current mode, demodulating samples according to their mode, the samples having a sample rate not an integer multiple of the specified data rate of the current mode, and outputting samples of demodulated data having an average sample rate which is a fractional factor of the input sample rate and is an integer multiple or integer factor of the specified data rate.