WO2006102929A1 - Circuit de demarrage souple de convertisseur cc-cc faisant appel a une limitation de cycle de service - Google Patents

Circuit de demarrage souple de convertisseur cc-cc faisant appel a une limitation de cycle de service Download PDF

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Publication number
WO2006102929A1
WO2006102929A1 PCT/EP2005/004653 EP2005004653W WO2006102929A1 WO 2006102929 A1 WO2006102929 A1 WO 2006102929A1 EP 2005004653 W EP2005004653 W EP 2005004653W WO 2006102929 A1 WO2006102929 A1 WO 2006102929A1
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WIPO (PCT)
Prior art keywords
duty cycle
output
converter
flip
voltage
Prior art date
Application number
PCT/EP2005/004653
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English (en)
Inventor
David M. Schlueter
Matthew Bacchi
Original Assignee
Freescale Semiconductor, Inc.
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Publication date
Application filed by Freescale Semiconductor, Inc. filed Critical Freescale Semiconductor, Inc.
Priority to PCT/EP2005/004653 priority Critical patent/WO2006102929A1/fr
Publication of WO2006102929A1 publication Critical patent/WO2006102929A1/fr

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the present application relates to a DC-DC converter. More specifically, the present application relates to a DC -DC converter in which the current is limited during start-up by limiting the duty cycle.
  • a boost converter is a circuit that increases the voltage supplied to the circuit to a higher voltage, which is used by other circuitry in the device. For example, typically a battery supplies about 3 V and the boost converter outputs about 5 V.
  • a buck converter reduces the voltage supplied to a lesser voltage for use by other circuitry.
  • the boost converter contains a capacitor that is connected to a battery through an inductor and a diode, and a transistor that controls the amount of current through the inductor.
  • the output of the boost converter is taken from the output of the capacitor.
  • the capacitor When the boost converter is initially turned on, the capacitor is already charged to the battery voltage. The transistor is conductive for a period of time, increasing the current drawn through the inductor and then made non-conductive. The energy in the inductor is transferred to the capacitor when the transistor is made non-conductive. This continues until the output voltage of the capacitor reaches a desired voltage. When the desired voltage is reached, the capacitor is connected to a load and power is drawn from the capacitor. The capacitor continues to be recharged, resulting in a steady state condition. In steady state (or normal operation), the transistor is conductive over a particular duty cycle of the system clock. The duty cycle is designed such that under maximum load conditions, the capacitor can provide the necessary power to drive the load.
  • in-rush current when the boost converter is initially turned on, a large amount of current (in-rush current) is drawn from the battery if the duty cycle is the same as that under steady state conditions. This can drain the battery temporarily, causing the battery to be unable to supply sufficient power to other circuits in the device. In addition, if the in-rush current is large enough, it can damage the inductor or the transistor as it flows through both.
  • a soft start circuit is used to limit the in-rush current from the battery.
  • the soft start circuit is a circuit that controls switching of the transistor by setting the duty cycle to be lower than the steady state duty cycle upon initial activation of the boost converter switcher. This limits the amount of time the transistor is active, and thus limits the in-rush current from the battery.
  • the soft start circuit uses a timer to control selection of the two duty cycles.
  • the smaller duty cycle is selected from when the boost converter switcher is activated for a predetermined period and, after that period elapses, the larger duty cycle is selected and the load connected to the capacitor.
  • the timer is preset after the soft start circuit is manufactured and is not altered once it is set. Because the charging time of the capacitor is a function of multiple components within the boost converter, the values of each of which vary within a set tolerance, the predetermined period is set to a time that is substantially longer than the maximum time needed to charge the capacitor under the worst case scenario with the tolerances of the components.
  • the soft start circuit is formed using both analog circuitry and digital circuitry.
  • the analog circuitry occupies a relatively large amount of space and consumes substantially more power than the digital circuitry.
  • the circuitry in the soft start circuit remains active during steady state operation.
  • Other circuits that limit the battery current monitor the average or peak current flowing thru the transistor during startup. The current limit in these circuits is fairly constant across battery voltage and inductor value.
  • such circuits require an accurate current sensing circuit and a high speed comparator, both of which draws a substantial amount of current and consume a large amount of space.
  • the present invention provides a DC-DC converter and a method of controlling an output voltage in a DC-DC converter as described in the accompanying claims.
  • FIG. 1 illustrates one embodiment of a DC-DC converter.
  • Fig. 2 is a timing diagram showing the relationship between the phase lock loop signal and the various clock signals.
  • a direct current (DC)-DC converter and method which dynamically and autonomously adjusts the current limit of the DC-DC converter from an initial soft start condition during start-up to a final value used during normal steady-state operation. Accordingly, idle time of the difference between a charging time and a predetermined period may be avoided.
  • the autonomous adjustment is capable of working with a timed adjustment to increase the maximum duty cycle to that obtained under normal operation.
  • the DC-DC converter is dynamic, fluctuating with capacitive and DC loading. In the DC-DC converter, an initial DC voltage is supplied and increased or decreased to produce a DC output voltage. The potential amount of time the output voltage is permitted to change is set and then changed dependent on the output voltage.
  • a clock and a plurality of delays of the clock are supplied, the potential amount of time is set by selecting a delay between the clock and one of the delays as the potential amount of time and then a different delay is selected once the output voltage has reached a predetermined voltage.
  • the delay selected can additionally be changed if the output voltage has not reached the predetermined voltage in a predetermined amount of time.
  • One or more of the delays can be used to trigger logic rather than being selectable as the potential amount of time.
  • a flag can be used to indicate when the predetermined output voltage has been first achieved and/or the in-rush current controlled such that the in-rush current increases with increasing initial voltages.
  • the DC-DC converter includes a low power boost converter 100, as shown in Fig. 1.
  • a DC voltage source such as a battery 102 is connected to an output unit such as a capacitor 108 through an inductor 104.
  • the battery 102 provides an initial DC voltage to the capacitor 108.
  • the boost converter 100 also contains a switch such as a power NMOS (Metal-Oxide- n-type doped Semiconductor) transistor 110 and a diode 106.
  • the anode of the diode 106 is connected to the inductor 104 and the cathode of the diode 106 is connected to the capacitor 108. Additional, different, or fewer components may be provided.
  • the boost converter 100 also contains a switcher 150 (also called a pulse width modulator) that includes a feedback loop 160 (also called soft start circuit).
  • the switcher 150 also contains a buffer 112 and a D flip-flop 114 (the first flip-flip 114).
  • the buffer 112 is connected to the gate of the transistor 110 and provides an output signal sufficient to drive the transistor 110.
  • the drain of the transistor 110 is connected at the connection between the inductor 104 and diode 106.
  • the source of the transistor 110 and the other side of the capacitor 108 are connected to ground.
  • the connection point between the capacitor 108 and the diode 106 is taken as the output of the boost converter 100 and supplied to a load 140.
  • the transistor 110 When conductive, the transistor 110 thus provides a current path for current in the inductor 104 and draws sufficient current through the inductor 104 such that when the transistor 110 is subsequently turned off, the capacitor 108 charges.
  • the transistor 110 is "on” when a voltage applied to the gate of the transistor 110 is sufficient to form a channel between the source and drain.
  • the switcher 150 switches the transistor 110 "on” and “off as per a duty cycle and permits the capacitor 108 to charge or discharge, thereby providing a controllable output voltage.
  • the switcher 150 controls a maximum duty cycle of the switch based on a voltage of the capacitor 108. More specifically, the switcher 150 increases a maximum duty cycle of the transistor 110 once the capacitor 108 has reached a predetermined voltage.
  • the battery 102 supplies power to the buffer 112.
  • the output of the buffer 112 is connected to the gate of the transistor 110.
  • the buffer 112 sources enough current to supply the transistor 110.
  • the input of the buffer 112 is connected to the data output Q of the first flip-flop 114.
  • a power supply voltage VDD is supplied to the data input D of the first flip-flop 114.
  • the first flip-flop 114 is triggered using a system clock signal CLK.
  • the power supply voltage VDD and system clock CLK are supplied by other circuits (not shown) in the device.
  • the power supply voltage VDD is a logic high voltage (hereinafter referred to as high).
  • the first flip-flop 114 has a reset rb input.
  • the soft start circuit 160 is connected to the reset rb input of the first flip-flop 114.
  • the soft start circuit 160 contains a second D flip-flop 116.
  • the data output Q of the first flip-flop 114 (Ndrive) is supplied to the data input D of the second flip-flop 116.
  • the second flip-flop 116 is triggered using a delayed CLK signal DutyCycle_ref.
  • the inverted output Qb of the second flip- flop 116 triggers a third D flip-flop 118.
  • the data input D of the third flip-flop 118 is supplied with a logic high voltage VDD.
  • the reset rb inputs of the second flip-flop 116 and the third flip-flop 118 is connected to the output Q of a fourth D flip-flop 120 (SS_enable).
  • the voltage VDD is supplied to the data input D of the fourth D flip-flop 120.
  • the fourth D flip-flop 120 is triggered using the clock CLK signal.
  • the reset rb input of the fourth D flip-flop 120 is supplied with a boost converter enable signal described below.
  • the output Q of the third flip-flop 118 is supplied to an OR gate 124.
  • the inverted output Qb of the third flip-flop 118 is supplied to external circuitry (not shown) and can be used as a trigger to indicate that the capacitor 108 has reached the predetermined voltage.
  • the inverted output of a flip-flop has the opposite state as the output of the flip-flop.
  • the SS_enable signal is also used to trigger a digital timer 122, whose output is also connected to the OR gate 124.
  • the output of the OR gate 124 (DCL indicator) is connected to the select SeI input of a multiplexer (MUX) 126.
  • the DCL_indicator is used to select between two clock CLK signals with different delays: DutyCycle ss and DutyCycle max.
  • the DutyCycle ss signal is delayed for a smaller amount of time than the DutyCycle max signal, and is used initially in soft start.
  • the DutyCycle_max signal is used after the capacitor 108 has charged up to the desired voltage or after a predetermined period of time. Both DutyCycle ss and DutyCycle max are delayed for a longer amount of time than DutyCycle_ref.
  • DutyCycle_ref, DutyCycle_ss, and DutyCycle_max are all CLK signals in which the delay of the rising edge of the signal as measured from the rising edge of the clock CLK signal supplied to the first flip-flop 114 increases such that DutyCycle_max delay > DutyCycle_ss delay > DutyCycle_ref delay.
  • the width of the delayed clock signals DutyCycle ref, DutyCycle ss, and DutyCycle max is the same as the clock CLK signal.
  • the delay time between the rising edge of the clock CLK and DutyCycle max is determined based on the maximum duty cycle used by the overall system under steady state conditions, which may depend on many other aspects of the boost converter.
  • the width of the delayed clock signals DutyCycle ref, DutyCycle_ss, and DutyCycle_max may be different from that of the clock signal CLK. No matter the width of the delayed clock signals DutyCycle_ref, DutyCycle_ss, and DutyCycle_max, these signals transition from high to low before the rising edge of the clock signal CLK after the clock signal CLK immediately preceding the delayed clock signals DutyCycle ref, DutyCycle ss, and DutyCycle_max.
  • the output X of the MUX 126 is connected to the input of a NOR gate 128.
  • a regulator feedback pulse is supplied to another input of the NOR gate 128.
  • the regulator feedback pulse is low as the capacitor 108 charges and becomes high when the output of the capacitor 108 has reached a predetermined value.
  • the regulator feedback pulse is dependent on the output voltage of the boost converter (i.e. the capacitor 108 voltage) that is fed back into a closed loop system (not shown).
  • a fraction of the output voltage is provided, such as by applying a voltage divider to the output voltage.
  • the fraction of the output voltage is supplied to an input of an operational amplifier (op-amp). Another input of the op-amp is supplied with the predetermined voltage.
  • the op-amp If the fraction of the output voltage is less than the predetermined voltage, the op-amp provides a low signal and if the fraction of the output voltage is greater than the predetermined voltage, the op-amp provides a high signal.
  • the signals are supplied to a voltage limiter, which limits the voltage from the op-amp and supplies one input of a comparator.
  • Another input of the comparator is provided with a ramp voltage that increases from 0 to a set voltage and then suddenly decreases to 0.
  • the comparator compares the voltage from the voltage limiter with the ramp voltage. When the voltage from the voltage limiter is smaller than the ramp voltage, the comparator provides a low signal and when the voltage from the voltage limiter is greater than the ramp voltage, the comparator provides a high signal.
  • the comparator provides the regulator feedback pulse.
  • the regulator feedback pulse in combination with DutyCycle max controls the transistor 110.
  • the output of the NOR gate 128 is supplied to an input of an AND gate 130.
  • the boost converter enable signal is supplied to another input of the AND gate 130.
  • the output of the AND gate 130 is taken as the output of the soft start circuit 160 and thus supplied to the reset rb of the first flip-flop 114.
  • the boost converter 100 operates in the following manner.
  • the reset rb of the first flip-flop 114 When the reset rb of the first flip-flop 114 is supplied with a low signal, the output Q of the first flip-flop 114 is low and thus the transistor 110 is off.
  • the reset rb of the first flip-flop 114 When the reset rb of the first flip-flop 114 is supplied with a high signal, the output Q of the first flip-flop 114 follows the input D of the D first-flop 114 when triggered by the rising edge of the clock CLK signal supplied thereto.
  • the input D of the first-flop 114 is VDD, the transistor 110 turns on.
  • the transistor 110 is controlled by signals supplied to the reset rb input of the first-flop 114. Accordingly, the output voltage of the capacitor 108 is controlled by the difference between the rising edge of the clock CLK signal and the falling edge of the signal supplied to the reset rb input of the first-flop 114 occurring before the rising edge of the next clock CLK signal.
  • the boost converter enable signal is low.
  • the output of the AND gate 130 and the input to the reset rb of the first flip-flop 114 are low.
  • the boost converter enable signal is low, SS Enable and thus the inputs to the reset rb of the second and third flip-flops 116, 118 and the digital timer are low. This sets the inverted output Qb of the second flip-flop 116 high. Because the third flip-flop 118 is in a reset state, however, the output Q of the third flip-flop 118 is low.
  • the timer 122 has not started and thus also provides a low output.
  • the boost converter 100 When the boost converter enable signal switches to high, the boost converter 100 is activated. Thus, the output of the AND gate 130 and the input to the reset rb of the first flip-flop 114 become high within one CLK cycle. On the next rising edge of the clock CLK signal, the output of the first flip-flop 114 (Ndrive) is set to VDD, turning on the transistor 110. At the same time, since the boost converter enable signal is high, the fourth D flip-flop 120 is no longer in a reset state. Thus, simultaneously with Ndrive being set high, SS_Enable is set high. With SS Enable high, the second and third flip-flops 116, 1 18 are also no longer in a reset state. In addition, when SS_Enable is set high, the digital timer 122 is started.
  • the inverted output Qb of the second flip-flop 116 is set low when triggered by DutyCycle ref. This does not yet affect the third flip-flop 118 as data is transferred from the input to the output of the flip-flops only on the rising edge of the clock signal used to trigger the flip-flops. Accordingly, the output Q of the third flip-flop 118 remains low.
  • the MUX 126 continues to select DutyCycle_ss as the output, which is supplied to the NOR gate 128.
  • the regulator feedback pulse is wider than DutyCycle max.
  • both inputs to the NOR gate 128 are low. Consequently, the output of the NOR gate 128 and the output of the AND gate 130 (and thus input to the reset rb the first flip-flop 114) remain high until the DutyCycle ss clock pulse occurs.
  • the first flip-flop 114 When the DutyCycle ss pulse occurs, the first flip-flop 114 is reset. The output Q of the first flip-flop 114 switches to low, turning off the transistor 110 and causing the inductor 104 to provide the current to charge the capacitor 108. At the end of the DutyCycle_ss pulse, both inputs to the NOR gate 128 are again low. This switches the first flip-flop 114 out of the reset state. However, the output Q of the first flip-flop 114 remains low and the transistor 110 turned off until the next clock CLK pulse, when VDD is once again latched through to the output Q of the first flip-flop 114. This cycle repeats until either the capacitor 108 has charged up to the predetermined value or the digital timer 122 triggers.
  • the pulse width of the regulator feedback pulse decreases.
  • the regulator feedback pulse becomes smaller than the delay between the clock CLK signal and DutyCycle_ss, thus driving the output of the NOR gate 128 and AND gate 130 low before the rising edge of DutyCycle ss, resetting the first flip-flop 114, and turning off the transistor 110.
  • the first flip-flop 114 remains in the reset state.
  • Ndrive remains low and on the next DutyCyclejref pulse, the inverted output Qb of the second flip-flop 116 switches from low to high.
  • the switching of the inverted output Qb of the second flip-flop 116 from low to high latches VDD from the input D of the third flip-flop 118 to the output Q of the third flip-flop 118. This causes the output of the OR gate 124 to go high, thereby forcing the MUX 126 to select the DutyCycle max pulse.
  • the SS_Indicator also switches from high to low.
  • the SS_Indicator signal is thus an indication that the capacitor 108 has reached the predetermined voltage and can be used to trigger external circuits, for example to enable the load 140 to be applied to the capacitor 108.
  • the pulse width controller 150 contains a feedback loop 160 in which an output of the pulse width controller 150 is controlled by a combination of the output voltage of the capacitor 108 and the output of the pulse width controller 150.
  • the actual duty cycle is generally set by the regulator feedback pulse.
  • the regulator feedback pulse width increases as the voltage on the capacitor 108 diverges from the predetermined value. This once again causes the first flip-flop 114 to transition out of the reset state.
  • the transistor 110 once again turns on. Ndrive becomes high, so that when DutyCycle_ref occurs, the inverted output Qb of the second flip-flop 116 transitions from high to low.
  • the DutyCycle max pulse is delayed more than the DutyCycle ss pulse, if the regulator feedback pulse remains low, the output of the NOR gate 128 and the AND gate 130 remain high longer. This consequently permits the first flip-flop 114 to remain out of the reset state for a longer time and the transistor 110 to stay on longer than if the DutyCycle ss pulse were selected.
  • the maximum duty cycle increases from the soft start duty cycle set by the delay between the clock pulse CLK and the delayed clock pulse _ n _
  • DutyCycle_ss to the steady state maximum duty cycle between the clock pulse CLK and the delayed clock pulse DutyCycle max.
  • the capacitor 108 is taking a relatively long amount of time to charge to the predetermined value, for example if a large load is attached to the capacitor 108, the maximum duty cycle is increased.
  • it is the timer 122 rather than the output of the fourth flip-flop 120 that causes the MUX 126 to select the longer delay DutyCycle_max.
  • the timer 122 triggers, sending a high signal through the OR gate 124. As above, this increases the amount of time between when VDD is latched through the first flip-flop 114 and when the first flip-flop 114 is reset, thereby increasing the amount of time the transistor 110 is on and consequently increasing the charging rate of the capacitor 108.
  • the SS_Indicator is triggered only when the capacitor 108 has reached the predetermined value and thus can still be used to trigger external circuits.
  • a phase-lock loop may be used to provide the timing for the clock CLK signal and the DutyCycle ref, DutyCycle ss and DutyCycle_max delays.
  • the PLL signal operates at a particular frequency while the clock CLK signal and the DutyCycle_ref, DutyCycle ss and DutyCycle max delays operate at a slower frequency.
  • the PLL signal can be divided and the DutyCycle ref, DutyCycle ss and DutyCycle max accordingly delayed for multiples of the ratio of the frequencies.
  • the PLL signal is sixteen times the frequency of the clock CLK and DutyCycle ref, DutyCycle_ss and DutyCycle_max delays.
  • the DutyCycle_ref, DutyCycle_ss and DutyCycle_max are delayed for multiples of 6.25% (1/16) of the clock CLK signal, specifically, 6.25%, 25%, and 75% as shown.
  • the PLL signal operates at 16MHz while the clock CLK signal and the DutyCycle ref, DutyCycle_ss and DutyCycle max delays operate at IMHz, with the DutyCycle ref, DutyCycle ss and DutyCycle_max delays being delayed 62.5 ns, 250ns, and 750 ns from the clock CLK signal.
  • the amount of in-rush current is susceptible to the battery voltage and the inductor value and tolerances, these percentages are exemplary only.
  • a number of systems have a low power mode of operation in which the clock CLK frequency is decreased dramatically (for example, from IMHz to 32kHz).
  • the system is disabled from entering the low power mode during soft start to permit the capacitor in the DC-DC converter to reach the predetermined value.
  • a signal such as the SS Indicator may then re- enable low power operation requests once the DC-DC converter reaches steady state.
  • the pulse width modulator on the DC-DC converter is disabled until the PLL is able to supply CLK signals at the system frequency.
  • any logic circuits that fulfill the overall function of one or more of the gates illustrated may be used.
  • D flip-flops have been shown, any latch may be used.
  • the addition of the timer 122 and OR gate 124 is optional.
  • the output Q of the fourth flip-flop 120 is supplied directly to the selector of the MUX 126.
  • a MUX that selects three or more delays may be used.
  • corresponding logic can be used to select the delays based on the output of the boost converterer and/or one or more timers. For example, an initial maximum duty cycle is selected and incrementally increased depending on set fractions of the predetermined output voltage achieved.
  • NMOS transistor is described, other transistors, such as a PMOS or bipolar transistor, may be used.
  • boost converter is shown, similar circuitry can be used for a buck converter topology, in which the voltage of the capacitor is decreased rather than increased, thereby providing a smaller DC voltage in steady state than the initial voltage provided by the battery.
  • Other power supply topologies including other switching power supply topologies may make use of this circuitry.
  • a low power DC-DC converter and method of operation of the DC-DC converter are provided in which the maximum duty cycle of the converter is dynamically and autonomously adjusted from an initial turn-on value (soft start) to a final value during steady state conditions.
  • the output unit is supplied with an initial DC voltage and controlled by a switch that controls the output voltage.
  • the maximum duty cycle is adjusted dependent on whether the output voltage has reached a predetermined, steady state value or after a preset time for cases in which an external load connected to the output causes the time for the output to reach the predetermined value to be excessively large.
  • the maximum duty cycle of the switch is increased by a pulse width controller once the output voltage has reached a predetermined voltage. A flag to be sent to other applications indicates when steady state is achieved and thus the capacitor is ready for loading.
  • the controller circuit easy to simulate and verify.
  • the use of digital logic permits the current limit circuitry to be physically smaller and draw comparatively less current than if using analog circuitry.
  • the controller circuit allows in-rush currents to be a function of battery voltage: at lower battery voltages, the in-rush current decreases while at higher battery voltages, the in-rush current increases, but not above specified limits. The decrease in the in-rush current when the battery voltage is low decreases the possibility of turning off external devices, such as radios, using the battery.
  • a smaller maximum duty cycle limit (25%) is used than in steady state (75%).
  • a pulse width modulator monitors the on-time of the transistor and compares it to a much smaller duty cycle limit (6.25%). As the output capacitor voltage of the boost converter nears the final value, the transistor on-time, which controls charging of the capacitor, reduces. When the 6.25% threshold is reached, the maximum duty cycle is switched from 25% to 75%.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un convertisseur CC-CC (104, 110, 106, 108) dans lequel un modulateur d'impulsions en largeur (150) connecté à un transistor (110) allume et éteint le transistor de façon à permettre à un condensateur (108) de se charger ou se décharger. Un cycle de service maximal du transistor est augmenté par le modulateur d'impulsions en largeur lorsque le condensateur a atteint une tension prédéterminée. Le cycle de service maximal est fixé par un retard d'horloge système. Le modulateur d'impulsions en largeur comprend des verrous (114, 116, 118, 120) dont les entrées, les sorties et les éléments de remise à zéro sont connectés ensemble en vue de la sélection du cycle de service maximal souhaité par l'intermédiaire d'un multiplexeur, une logique qui combine le cycle de service sélectionné avec une impulsion de rétroaction de régulateur de manière à déterminer un cycle de service en cours, une minuterie (122) qui sélectionne le cycle de service maximal si le condensateur n'a pas atteint une tension prédéterminée dans un intervalle de temps (130) prédéterminé, et une logique qui permet le fonctionnement du modulateur d'impulsions en largeur au moyen d'un signal de validation fourni extérieurement.
PCT/EP2005/004653 2005-04-01 2005-04-01 Circuit de demarrage souple de convertisseur cc-cc faisant appel a une limitation de cycle de service WO2006102929A1 (fr)

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US10797600B2 (en) 2017-12-25 2020-10-06 Asahi Kasei Microdevices Corporation Power supply apparatus, microbial fuel cell voltage boosting circuit and microbial fuel cell voltage boosting system
CN113258760A (zh) * 2021-05-14 2021-08-13 珠海格力电器股份有限公司 一种电路控制方法、装置、电子设备及存储介质
CN114172356A (zh) * 2020-09-10 2022-03-11 比亚迪股份有限公司 双向dc/dc变换器的过载处理方法、装置、存储介质及终端
CN117040498A (zh) * 2023-10-08 2023-11-10 成都明夷电子科技有限公司 一种可变占空比的时钟产生电路及电子设备

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CN102751859A (zh) * 2012-07-11 2012-10-24 圣邦微电子（北京）股份有限公司 软启动电路及其启动控制方法
US10797600B2 (en) 2017-12-25 2020-10-06 Asahi Kasei Microdevices Corporation Power supply apparatus, microbial fuel cell voltage boosting circuit and microbial fuel cell voltage boosting system
CN114172356A (zh) * 2020-09-10 2022-03-11 比亚迪股份有限公司 双向dc/dc变换器的过载处理方法、装置、存储介质及终端
CN113258760A (zh) * 2021-05-14 2021-08-13 珠海格力电器股份有限公司 一种电路控制方法、装置、电子设备及存储介质
CN117040498A (zh) * 2023-10-08 2023-11-10 成都明夷电子科技有限公司 一种可变占空比的时钟产生电路及电子设备
CN117040498B (zh) * 2023-10-08 2024-01-26 成都明夷电子科技有限公司 一种可变占空比的时钟产生电路及电子设备

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