WO2006095313A1 - Procede permettant de commander a distance un appareil d'affichage base sur ledit procede et dispositif portable comprenant ledit appareil - Google Patents

Procede permettant de commander a distance un appareil d'affichage base sur ledit procede et dispositif portable comprenant ledit appareil Download PDF

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Publication number
WO2006095313A1
WO2006095313A1 PCT/IB2006/050714 IB2006050714W WO2006095313A1 WO 2006095313 A1 WO2006095313 A1 WO 2006095313A1 IB 2006050714 W IB2006050714 W IB 2006050714W WO 2006095313 A1 WO2006095313 A1 WO 2006095313A1
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WIPO (PCT)
Prior art keywords
serial
data stream
word
synchronization
bits
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Application number
PCT/IB2006/050714
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English (en)
Inventor
Ewa Hekstra-Nowacka
Bart P. V. Peters
Wilhelmus J. M. Smits
Van Den Peter Hamer
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Koninklijke Philips Electronics N.V.
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Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2006095313A1 publication Critical patent/WO2006095313A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/045—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial

Definitions

  • the invention relates to a display system and the serial communication between a controller and the display system.
  • the invention relates in particular to a highspeed serial link for use in portable devices.
  • FIG. 1 An example of such a parallel link is illustrated in Fig. 1.
  • the parallel link 9 in this Figure connects two interface circuits 7 and 8.
  • the link itself has in the given example four bus lines 9.1 for control purposes (PCLK, VS, HS, DE) and eighteen bus lines for the 18 bit wide data stream for the pixel RGB data.
  • PCLK, VS, HS, DE control purposes
  • eighteen bus lines for the 18 bit wide data stream for the pixel RGB data.
  • This bridge 13 is for example situated inside the upper chassis of a clamshell phone.
  • the bridge 13 transforms the serial data into parallel data before sending them via another parallel bus 16 and a respective display driver or interface onto a display.
  • the invention presented herein is concerned specifically with the display parallel interface (DPI) as promoted by the Mobile Industry Processor Interface group.
  • the standard parallel display interface 14, as shown in Fig. 2 requires the following control signals: pixel clock (PCLK), data enable (DE), horizontal sync (HS), vertical sync (VS). It also requires between 12 and 24 bits (e.g., 18 bits RGB data with 6 bits R, 6 bits G, 6 bits B if an equal partitioning of the bits between these three colors is used). With each clock cycle a new data word is injected into the bridge 12. Such a word is defined to comprise of a header with DE, HS, VS bits, and the payload of 12 to 24 bits of RGB data for a pixel.
  • serial data stream consists then of consecutive serialized words with a specified structure, i.e. DE, HS, and VS bits first, followed by the RGB bits, or in the reverse order with the RGB bits first followed by the DE, HS, and VS bits.
  • the control signals DE, HS, and VS are hereinafter referred to as timing parameters or control signals, whereas the pixel data are referred to as payload.
  • HFP Horizontal Front Porch
  • HBT Horizontal Back Porch
  • VFP Vertical Front Porch
  • VBP Vertical Back Porch
  • the pixel clock signal is provided in order to synchronize pixel data to the LCD display panel.
  • VS is the vertical synchronization signal which in passive mode is the frame clock employed to signal the start of a new frame of pixels to the LCD display panel. In active mode, VS is the vertical synchronization signal.
  • HS is the horizontal synchronization signal which in passive mode is the line clock that signals the end of a line of pixels to the LCD display panel. In active mode, HS is the horizontal synchronization signal.
  • the clock synchronous serial interface is considered with two options, namely either clock and data, or strobe and data.
  • the respective link can also be characterized as source synchronous link, since the display uses the same clock frequency to display data as the source uses. That is, one can have as few as two wires or connections (data and clock) for the serial link 15. This is symbolically indicated in Fig. 2 by two wires present in the serial interface 15. In case of a differential signaling scheme in said serial link one would need two wire pairs. This is symbolically indicated in Fig. 9 by two twisted wire pairs present in the serial interface 25. On the serial link 15 an error can occur, which means that bit values may get inverted in case of clock and data, as illustrated in Fig. 4A.
  • Bits can be removed from the serial data stream in case of strobe and data, as illustrated in Fig. 4B.
  • the black boxes in these two Figures indicate the bit errors, the bit values in these are the erroneous values.
  • the word alignment is preserved even when data signal is "dirty".
  • this is not the case for the strobe and data, as illustrated in Fig. 4B, where the recovered clock can be severely affected.
  • word synchronization it is another problem, that while serializing data, the word/line boundaries are lost. If one starts to receive data at the display side, one sees just the bit stream and one does not know where the words are in this stream. That is, the word/line boundaries are lost on the serial link. So in the first instance one needs to find out where the word boundaries are in order to be able to retrieve these words (hereinafter referred to as word synchronization). The alignment between word and line boundaries becomes relevant when errors on the serial link occur. Such errors on the serial link can affect how the words align to each other within the bit stream.
  • the pixels can be represented by three colors R, G and B, for instance. Each of these colors can in turn be represented by different numbers of bits. This means that the RGB pixel representation can have different lengths. There can also be a different partitioning of the numbers of bits between these colors. There is thus also a need for a method that allows dealing with a dynamically changing format of the pixel representation at a line or frame level.
  • the synchronization method proposed herein allows to quickly and reliably provide for a word synchronization at the receiving side of a high-speed serial link.
  • an inventive synchronization method is proposed which allows a re-synchronization on a regular basis.
  • horizontal synchronization patterns are constructed, which occur in the serial data stream at regular intervals, and on which one can perform a synchronization at the receiving end of a high-speed serial link.
  • a method is proposed, which allows reasonably quickly to re-gain the line alignment within the video frame by incorporating the line numbers in the video stream.
  • This method for line alignment is typically carried out after the word synchronization was performed.
  • a characteristic word is constructed, which is located in the porch part of each line together with the active video data, and which contains an appropriate line number.
  • the advantages of the proposed method are many- fold. With the inventive method, no changes are needed for other words in the serial data stream than in the porch.
  • the characteristic word may instead of the line number also be a tag that defines the bit-budgeting for the different colors of a pixel.
  • the inventive method works for variable lengths of the RGB pixel representations and also for differently partitioned numbers of bits between the colors. There is no extra overhead required since one uses the bits already present in the serial data stream to send the line numbers and/or tags and/or the horizontal synchronization information in the serial data stream.
  • reliable word synchronization is also provided for the active video part.
  • the method according to the present invention is characterized in that, if the predetermined sequence occurs in the active video part or its direct neighborhood, these data are replaced by alternative unique data. Hereby false synchronizations are prevented.
  • inventive methods also work for video formats other than RGB, such as YUV, for instance.
  • inventive methods also work for other polarities of the control signals than those depicted in Fig. 3 A and 3B.
  • inventive methods can also be used for other devices dealing with serialized video, graphic streams, or still pictures, such as e.g. cameras, for example.
  • Fig. 1 is a schematic representation of a conventional parallel interface
  • Fig. 2 is a schematic representation of a serial high-speed interface, as for example used in a portable device according to the present invention
  • Fig. 3 A is a schematic diagram illustrating specific dependencies of signals occurring in the parallel display interface (these dependencies are preserved during serialization);
  • Fig. 3B is a schematic diagram illustrating specific dependencies of signals occurring in the parallel interface
  • Fig. 4A is a schematic diagram illustrating bit errors on the source synchronous serial link in case of a clock and data implementation
  • Fig. 4B is a schematic diagram illustrating bit errors on the source synchronous serial link in case of a strobe and data implementation
  • Fig. 5 is a schematic diagram illustrating the losing of the word synchronization and thus also the line alignment in case of errors on the serial link;
  • Fig. 6 is a schematic diagram illustrating the words retrieved from the serial data stream being displayed in the line-by-line manner (from left to right);
  • Fig. 7 is a schematic diagram giving a pictorial view of the programmable timing parameters on a serial link
  • Fig. 8 is a schematic block diagram of an embodiment of the present invention.
  • Fig. 9 is a schematic block diagram of another embodiment of the present invention.
  • the invention presented herein deals with this synchronization/re-alignment problem and a synchronization method is described and claimed, which allows a word realignment at the receiving side of the serial link at regular intervals.
  • horizontal synchronization patterns are constructed, which occur in the serial data stream at regular intervals, and on which one can perform a synchronization at the receiving end of a high-speed serial link. These horizontal synchronization patterns are generated at the transmitter side and replace certain bits in the data stream.
  • the proposed solution to the word synchronization problem satisfies the following additional requirements: - no additional synchronization signals are used beyond the actual signals already present in the display interface; the word alignment is restored as soon as possible at the beginning of a new line following errors; implementations at the transmitter and the receiver side are of a low complexity (both in hardware and software).
  • a serial data stream is transmitted via the serial link.
  • words are retrieved from the serial data stream. These words are displayed on a display in a line-by-line manner, as shown in Fig. 6.
  • Four lines are depicted in this Figure. Assuming that the original DE, HS, and VS signals are present in serialized words of the serial data stream, it is possible to distinguish at the receiving end a number of regions in the serial data stream. These regions are characterized by a specific combination of DE, HS, and VS bits/signals. The respective regions are depicted in Fig. 7.
  • FIG. 7 gives a pictorial overview of the programmable timing parameters.
  • Each region in this diagram can be described by a three bit word, where the first digit represents DE, the second digit represents HS, and the third digit VS. With these three digits one can describe all regions inside the diagram.
  • the gray area in the middle is the active video region.
  • the region in the left hand corner at the top (1 st row, 1 st column) is represented by the digits 000, for example.
  • the active video region (3 rd row, 3 rd column) is represented by the digits 111, just to give two examples.
  • Words outside the active video region have one of the following four headers: [000]; [001]; [010]; or [011].
  • the words inside the active video region have a [111] header followed by the original payload (e.g. an RGB payload).
  • horizontal synchronization patterns are constructed at the transmitter side and replace the not-active video payload data. The replacement is done in specific regions in Fig. 7 on which one can synchronize in order to (re-)gain the word synchronization.
  • the horizontal synchronization patterns replace bits in the regions at the beginning of each line (1 st column in Fig. 7).
  • Such a horizontal synchronization pattern preserves the characteristic [DE HS VS] header and does not have any impact on the clock speed. To achieve this, each of these regions in the 1 st column requires a different horizontal synchronization pattern.
  • the choice of payload of the horizontal synchronization patterns has to fulfill the following conditions: the horizontal synchronization pattern is characteristic in the sense that it has to differ from other words; - the horizontal synchronization pattern does not contain (or form with surrounding words) a sequence of three or more consecutive ones, since a sequence of three or more consecutive ones [111] represents the active video header (cf. Fig. 7); it is also essential that words coming from other regions of the serial data stream and their RGB payload are constructed in such a way that they too cannot be misinterpreted as a horizontal synchronization pattern.
  • the proposed horizontal synchronization patterns are examples only: in the combined horizontal/vertical synchronization region (1 st row, 1 st column), i.e. the region designated by [000], the proposed horizontal synchronization pattern has the following structure: the [000] header (herein referred to as synchronization header), followed by a payload (herein referred to as synchronization payload) comprising a concatenation of Os and 1 s, and two Os at the end
  • the proposed horizontal synchronization pattern has the following structure: the [001] header (herein referred to as synchronization header), followed by synchronization payload (herein referred to as synchronization payload) comprising a concatenation of Os and Is
  • the word synchronization is performed in any of the other regions except the active video part, e.g. in the second column depicted in Fig.7.
  • similar constraints as those imposed on column 1 must apply to the synchronization words in the addressed regions of column 2.
  • the number of reference points in the bitstream for finding subsequent words increases, therefore decreasing the chance of word misalignment in case of errors as the region without horizontal synchronization is restricted only to the active video.
  • other horizontal synchronization patterns could be proposed.
  • the synchronization method of the present invention works for other numbers (typically varying between 12 and 24) of bits needed for the RGB representation. These colors can be represented by different numbers of bits and the RGB pixel representation can have different length. Furthermore, there can be different partitioning of the numbers of bits between the colors.
  • the structure of the horizontal synchronization pattern remains then unchanged, i.e. the synchronization header is the same as well as the synchronization payload comprises alternating Os and Is. Only the length of the synchronization payload would have to be adapted.
  • This synchronization header may have 2, 3 or more bits.
  • This synchronization header enables an identification of words belonging to different regions of the serial data stream. However, in the case of the display or camera these 3 bits are inherent (already present) in the original parallel display interface anyhow.
  • the hardware implementation of the inventive synchronization method requires, for 18 bits RGB representation, 21 comparators for the total length of the serial word. Further details of possible implementations are discussed in connection with Fig. 8.
  • the solution to the line alignment problem has the following advantages: no additional signals are used beyond the actual signals already present in the display interface; the line alignment can be restored as soon as possible at the beginning of a new line following errors, the implementation are of a low complexity (both in hardware and software); the horizontal synchronization method with the proposed horizontal synchronization pattern remains unaffected, that is, one can combine the method for line realignment and the method for word synchronization.
  • the words 30 retrieved from the serial data stream are displayed in a line-byline manner, as shown in Fig. 6.
  • the original DE, HS, and VS signals (herein referred to as control signals) are present in the serialized words 30 received at the receiving side, it is possible to distinguish a number of regions in the serial data stream. Each such region is characterized by a unique combination of DE, HS, and VS bits/signals. These regions are depicted in Fig. 7. As addressed above, the diagram in Fig. 7 gives a pictorial overview of the programmable timing parameters.
  • a new characteristic word is constructed, which is placed as the first word in the porch region (it could be also placed in other parts of the porch or simply repeated in the porch of each line that contains the active video).
  • the porch region is the region in Fig. 7 being represented by the three digits [011]. In other words, the porch region is the "frame" around the active video region [111].
  • the new characteristic word incorporates an appropriate line number, according to the present invention.
  • the new payload (herein referred to as characteristic payload) consists of burst of Os followed by the binary representation of the respective line number. This can be symbolically represented as:
  • the line number of the respective line can be extracted whenever a word in the porch is detected at the receiving side. This enables the bridge device 13 at the receiving side of the serial link to do a line re-alignment for each line or whenever less often.
  • the format of the pixel representation can change dynamically.
  • appropriate format information is sent in the band. This enables a format detection at the receiving side.
  • the format detection is done in two steps:
  • bit-budget for different colors for a pixel is detected.
  • the synchronization words can be constructed. If the requirement of at least two consecutive synchronization words is fulfilled, then for each position in the bitstream a search for two consecutive synchronization words is done, for each possible length of pixel representation, in order to determine the total length of the new pixel format for two consecutive synchronization words prevents possible misdetection of the new pixel format, for example in case when a valid short synchronization word occurs in the video payload of longer pixel format. In such a case the three ones header [111] of the following pixel of an active video will make the test for synchronization word to fail since the expected second synchronization word does not contain three consecutive ones.
  • bit-budgeting for pixel colors is solved in a similar way as the line number problem discussed and described above.
  • the possible bit-budgets are for example enumerated and a unique number/tag is assigned to each possible bit-budget.
  • a tag is communicated across the serial link instead of the line number.
  • 10 bits can be reserved for line numbers. These 10 bits gives also ample of freedom to define the different bit-budgeting for pixel colors.
  • the method proposed for the format detection allows a nearly instantaneous detection of the new pixel format with its length and bit-budget per color on the line basis. It is also possible to implement the format detection on the frame basis only. In such a case the format could be changed only on a frame basis, and preferably at the beginning of a frame. In case of errors on the serial display interface in the worst case this would lead to a loss of one frame.
  • the format detection method does not change the synchronization mechanisms as herein addressed.
  • RGB formats e.g. YUV
  • the length detection would remain the same, but the bit- budgeting options must be extended by extra combinations specific for e.g. YUV.
  • the active video part one cannot synchronize using the method described so far.
  • the active video data is characterized by a 111 header followed by payload data.
  • For the active video area one identifies a synchronization event as a matching of the active video header 111 -sequence.
  • next one replaces all active video data words having at least a l l 1 -sequence in the concatenation of active video data word header 111 and active video data payload, not starting at the word boundary, by unique valid synchronization words from the space of unique synchronization words that satisfy the synchronization requirements, as outlined above, and that are not synchronization words already used for word synchronization in other regions.
  • the replacement unique synchronization words are available at the receiving end of the bridge and one can do the synchronization at the receiving end on the 111 header of the active video data word or on the replacing unique valid synchronization word or on the synchronization words for the not active video regions.
  • the receiver then has to replace the unique synchronization words used in the active video area with the original data using an inverse mapping available to the receiver.
  • an advanced single-lane (single channel) synchronization was described. The method described in these sections can also be expanded so that it can be used for multilane synchronization.
  • the polarity of the HS 5 VS and DE signals can be different. If the polarity is different (e.g., DE is active low), one can do a mapping to the polarity that was assumed so far (e.g. DE active high). One then has to signal in the encoding of the synchronization words (by using different synchronization words) that a different polarity is used such that in the receiver the inverse mapping can take place.
  • serial link is employed for transmitting a serial data stream from a controller to the display.
  • the serial data stream carries payload, e.g. RGB formatted image signals, and control signals (HS, VS, DE) for the horizontal and vertical synchronization.
  • control signals HS, VS, DE
  • HS, VS, DE enable a number of regions in the serial data stream to be distinguished, as depicted in Fig. 7, where each of these regions is characterized by a unique combination of the control signals (HS, VS, DE).
  • the serial bit clock is not part of the serial data stream.
  • the time reference is used at the receiver side to sample the data.
  • a characteristic sequence of bits is constructed at the serializer/transmitter side
  • the characteristic sequence of bits comprises a header and a payload portion.
  • the serial data stream is prepared for transmission across the serial link 25.
  • the serial data stream comprises the control signals (CLK, HS, VS, DE), the payload (RGB), and the characteristic sequence of bits.
  • the serial data stream is then transmitted across the serial link 25 and at the receiving end 23.2 the words are retrieved from the serial data stream.
  • a bridge 23.2 processes the serial data stream to detect the characteristic sequence of bits that indicate the word boundaries.
  • the bridge can be a receiver or any other kind of device. It is also possible to include the functionality of the bridge into some other device, such as a display driver for instance.
  • the characteristic sequence of bits that indicate the word boundaries enables the bridge 23.2 to provide for a word synchronization.
  • the words are displayed on the display 23.1 in a line-by-line manner.
  • the present invention can be implemented in a display port bridge integrated circuit pair where one bridge 12 serves as transmitter-serializer and one bridge 13 as receiver- deserializer, as for example illustrated in Fig. 8.
  • the bridges 12 implement building blocks
  • the bridge 12 has a parallel input 14 and a serial output 15. Preferably, the inputs and outputs are CMOS based.
  • the bridge 12 receives via the parallel bus 14 RGB (e.g., RGB888) and control signals (e.g., HS, VS, DE).
  • RGB e.g., RGB888
  • control signals e.g., HS, VS, DE
  • the data lines are designated as Dat[0] through Dat[17]
  • the control lines 9.1 are designated as PCLK, DE, VS, and HS.
  • the bridge 12 comprises the following building blocks: a parallel to serial converter 12.1, a PLL circuit 12.2, and an encoding unit 12.3 that implements the generation of the characteristic word and/or the horizontal synchronization patterns.
  • the bridge 12 is implemented so that the data are replaced by the horizontal synchronization words before the parallel- serial conversion is carried out by the parallel to serial converter 12.1. Furthermore, there are output buffers 12.4 for driving the signals across the serial link 15. In the present embodiment differential signaling is used on the serial link 14, as indicated by the CLK- / CLK+ and DO- / DO+ signal pairs.
  • the bridge 13 has a serial input 15 and a parallel output 16.
  • the bridge 13 receives via the serial link 15 a serial data stream.
  • This serial data stream comprises control signals, payload with image data, and characteristic words and/or horizontal synchronization patterns, in accordance with the present invention.
  • the bridge 13 comprises the following building blocks: a serial to parallel converter 13.1that implements the extraction of the characteristic word and/or the horizontal synchronization patterns.
  • the serial to parallel converter 13.1 performs the word synchronization according to the present invention.
  • the serial to parallel converter 13.1 may comprise a number or comparators arranged in parallel for the total length of the serial word.
  • the phone 40 comprises a first device 22.2 that has a parallel input side for connecting it via a parallel bus 24 to a controller or an application engine 22.1.
  • the first device 22.2 further comprises a serial output for connecting it via a serial link 25 to a second device 23.2.
  • the first devices 22.2 and the controller 22.1 may both be located in the lower chassis 41 of the phone 40.
  • the second device 23.2 together with a display 23.1 may be located in the upper chassis 42 of the phone 40.
  • the second device 23.2 has a serial input side 25 and a parallel output side 26.
  • the serial link 25 is designed for the transmission of a serial data stream and it provides for a connection between the serial output side of the first device 22.2 and the serial input side of the second device 23.2.
  • This serial link 25 may be realized by means of a flexible foil carrying the required number of conductive lines.
  • serial link 25 comprising just one channel for the transmission of payload (RGB) comprising the image signals and the control signals (HS, VS, DE) for horizontal and vertical synchronizations. More than one channel may be provided. One may obtain the synchronization from one channel only, but one can also obtain the synchronization from more channels.
  • the first device 22.2 comprises an encoding unit (e.g. an encoding unit 12.3 similar to the one depicted in Fig. 8) implementing the generation of a characteristic sequence of bits, as discussed in connection with the inventive methods.
  • This encoding unit is connectable to the first device 22.2.
  • the second device 23.2 may comprise a decoding unit implementing the extraction of the characteristic sequence of bits. This decoding unit is connectable to the second device 23.2.
  • Fig. 9 the position of a hinge is indicated by means of the dotted line 29.
  • the upper chassis 42 of the phone 40 can be flipped around an axis that runs parallel to the line 29.
  • the bridges 12, 22.2 and 13, 23.2 typically have separate pins for link power and ground. These pins are not depicted in the Fig. 8 and 9.
  • the bridge 12, 22.2 accept parallel CMOS input data including color pixel data R[7:0], G[7:0], B[7:0], horizontal synchronization bit HS, vertical synchronization bit VS, data enable bit DE and pixel clock PCLK.
  • the bridges 12, 22.2 generate the characteristic word and/or the horizontal synchronization pattern, as discussed in connection with the inventive methods and they serialize theses data.
  • the bridges 12, 22.2 output a high-speed serial data stream on up to three differential output channels. In Fig. 8 and in Fig. 9 implementations are shown with just one differential output D0+, DO-.
  • the PLL 12.2 may be an integrated low-jitter PLL. It is employed to generate internally the bit clock used for the serialization of video input data Dat[0] ... Dat[17] and the controlling signals DE, HS 5 VS and the bits representing the characteristic word and/or the horizontal synchronization pattern.
  • the bridge 12, 22.2 outputs along with the serial output data DO+, DO- a differential pixel clock on a differential output pair CLK+ and CLK-.
  • the bridge 13, 23.2 accepts serial differential data inputs DO+, DO- and the differential input clock CLK+ and CLK- from the signaling channel (serial link 15 or 25) and deserializes the received data into parallel output data on the parallel bus 16 or 26.
  • This bus 16, 26 may carry the following signals, for instance: R[7:0], G[7:0], B[7:0], HS, VS, DE along with pixel clock PCLK generated by logic from the bitclock (CLK) and the synchronization hardware.
  • the decoding unit 13.3 extracts the line number of the actual line whenever a characteristic word in the region header is detected. This information is sent to a display driver where it is used to rearrange the lines using the extracted the line number.
  • the decoding unit 13.3 detects this pattern to enable at the receiving side a word/line re-alignment (re-synchronization) within the serial data stream. This word/line re-alignment being done on a regular basis.
  • the transmitter-serializer (12 or 22.2) can be used to serialize parallel input data into 1 or more high-speed serial data channels.
  • the receiver-deserializer bridge (13 or 23.2) may be realized so that it is able to deserialize up to 3 high-speed serial data channels into parallel data signals, for instance.
  • the number of high-speed serial channels is made configurable from 1 to 3 depending on the bandwidth needed.
  • the data link speed is determined by the PCLK (pixel clock) rate and the number of serial channels selected.
  • the present invention is well suited for the transmission of RGB formatted image signals, e.g. RGB888 video data, via a serial high-speed link to the display.
  • RGB formatted image signals e.g. RGB888 video data
  • the present invention allows to provide a transparent interface between a baseband (e.g. located in a lower chassis 41) and a display portion (e.g. located in an upper chassis 42) of a mobile phone 40, for instance.
  • the bridge 22.2 for instance, can be employed in the lower chassis 41 and the bridge 23.2 in the upper chassis 42.
  • the bridges 22.2, 23.2 allow to establish a connection between a controller 22.1 in the lower chassis 41 and a display, e.g. an LCD display panel 23.1, in the upper chassis 42.
  • the signal routing can be as follows: controller 22.1 + bridge 22.2 + serial link 25 (e.g., a flexible foil) + bridge 23.2 ⁇ * ⁇ display 23.1.
  • LVDS low voltage differential signaling
  • sub- LVDS sub- LVDS
  • SLVS low voltage differential signaling
  • a high-speed serial link targeting a specific circuit iunction and having a tightly defined area of application is presented.
  • the present invention allows to interconnect the system board and the display module in mobile phones and other types of handheld devices, especially those with a clamshell design.
  • the present invention allows reliable display interface connections to be made that can be used in clamshell phones, for instance.
  • the display interface chips comprise a serializer and deserializer pair that is designed to replace the conventional parallel approaches. If combined with a flexible interconnect, one can realize new clamshell designs.
  • the invention can be used in mobile phone, e.g. high resolution mobile phones, and in portable applications with video capability, for instance.
  • the advantage of the inventive line alignment methods is that no extra overhead is needed in order to incorporate the respective characteristic bit sequences in the serial data stream. Instead of having meaningless information one uses the available bits. This allows at the receiving side of the serial interface to do the re-alignment.
  • a synchronization method is proposed, which allows line realignment within a video frame at the receiving side of the serial link. It is an advantage of this synchronization method that the line realignment within a video frame is achieved without affecting the horizontal synchronization method proposed in connection with one of the embodiments of the present invention.

Abstract

L'invention concerne un premier appareil (22.2) comprenant un premier côté d'entrée (14) parallèle et un côté de sortie (15) sérielle. Un second dispositif (13) comprend un côté d'entrée (15) sérielle et un côté de sortie (16) parallèle. Une interface connecte le côté de sortie (16) parallèle du second dispositif (13) à un panneau d'affichage (23.1). Une liaison sérielle (15) est utilisée pour transmettre un flux de données sérielles et établit une connexion entre le côté de sortie (15) sérielle du premier dispositif (12) et le côté d'entrée (15) sérielle du second dispositif (13). Ladite liaison sérielle (15) comprend au moins un canal destiné à transmettre une charge (RGB) comprenant des signaux d'image et des signaux de commande (CLK, HS, VS, DE) afin d'effectuer des synchronisations horizontales et verticales. Les signaux de commande (HS, VS, DE) permettent de distinguer un certain nombre de régions dans le flux de données sérielles, chacune de ces régions étant caractérisée par une combinaison unique des signaux de commande (HS, VS, DE). Une unité de codage (12.3) est utilisée pour générer une séquence caractéristique de bits. Ladite unité de codage (12.3) est connectée au premier dispositif (12). Un bloc de construction (13.1) peut être utilisé pour synchroniser des mots et pour passer d'une conversion sérielle à une conversion parallèle.
PCT/IB2006/050714 2005-03-11 2006-03-08 Procede permettant de commander a distance un appareil d'affichage base sur ledit procede et dispositif portable comprenant ledit appareil WO2006095313A1 (fr)

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EP05101895 2005-03-11
EP05101895.0 2005-03-11
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WO2008137055A1 (fr) * 2007-05-03 2008-11-13 James Boomer Procédé et circuit d'entrelacement, de sérialisation et désérialisation des données de caméra et de clavier
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TWI698092B (zh) * 2017-11-23 2020-07-01 円星科技股份有限公司 用於高速序列資料通訊系統的編碼和解碼架構及其相關方法、實體層電路、發射器與接收器及其中的通訊系統
US11012087B2 (en) 2017-11-23 2021-05-18 M31 Technology Corporation Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof
CN116052578A (zh) * 2023-03-31 2023-05-02 深圳曦华科技有限公司 一种显示芯片系统中码片输入输出同步控制方法及装置
CN116052578B (zh) * 2023-03-31 2023-08-04 深圳曦华科技有限公司 一种显示芯片系统中码片输入输出同步控制方法及装置

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