WO2006093297A1

WO2006093297A1 - Intermittent reception control apparatus

Info

Publication number: WO2006093297A1
Application number: PCT/JP2006/304169
Authority: WO
Inventors: Naoyuki Yamamoto
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2005-03-04
Filing date: 2006-03-03
Publication date: 2006-09-08
Also published as: JP2008124524A

Abstract

An intermittent reception control apparatus wherein only upon reception of a signal from any base station, a high-rate, highly precise VCTCXO is activated to elongate a standby time even in a case where a signal transmitted from the base station of another cell is received. In this apparatus, a timing control part (1002) decides a reception timing of the signal of PCH of the local cell such that the signal of PCH of the local cell is received immediately after the timing at which the signal of BCCH of the other cell is received. A cell switching part (1003) switches the cells of the other end of communication in accordance with the reception timing decided by the timing control part (1002). When receiving the radio wave from the local cell, an activation time setting part (1004) calculates how many frames of sleeps are possible until the next reception of received radio waves (i.e., an intermittent period), and sets data, which corresponds to the intermittent period, to the registers of a time synchronization timer and of a sleep timer via a CPU bus.

Description

Specification

Intermittent reception controller

Technical field

The present invention relates to an intermittent reception control device applied to a wireless terminal communication device such as a mobile phone.

Background art

[0002] A necessary operation during standby of a mobile phone is to regularly receive a signal transmitted mainly using a paging channel (PCH: Paging Channel) of the base station power of the own cell. PCH is allocated with a period of several hundred milliseconds and several seconds, and reception takes only several tens of milliseconds, and other times only maintain time synchronization. is there. Receiving signals from the base station requires a high-speed and high-accuracy voltage-controlled temperature-compensated crystal oscillator (VCTCXO). VCTCXO is also used to maintain time synchronization that occupies most of the waiting time. The time synchronization timer was circulated while it was running. However, due to the increase in standby time in recent years, the clock clock (RTC: Real Time Clock), which is low speed and low precision, is used to maintain time synchronization, and VCTCXO is activated only when receiving a signal from the base station. A method has been proposed (see, for example, Patent Document 1).

[0003] In this method of starting VCTCXO only when a signal is received from the base station, various error components caused by the stop of the high-speed clock are suppressed within the time width of the reception window, and finally the base of the own cell. A signal transmitted using local power PCH (hereinafter referred to as “PCH signal of own cell”) is received, and the received position of the synchronization word is calculated in the receiving window to calculate the received power. Time synchronization is maintained by performing time tracking based on the results.

[0004] The necessary operations during the standby of the mobile phone include a period of several tens of seconds or several minutes in addition to periodically receiving the PCH signal of the own cell as described above. You must also receive a signal from the base station. For example, in the GSM (Global System for Mobile Communications) method, the field strength is reduced from up to six base stations in other cells. Signals transmitted using the Chronization Channel (SCH) must be received once every 30 seconds, and broadcast control is performed from base stations of other cells with a maximum field strength of 6 Signals transmitted using the channel (BCCH broadcast Control Channel) (hereinafter referred to as “BCCH signals of other cells”) must be received once every 5 minutes.

Patent Document 1: JP 2000-49682 A (Page 4)

Disclosure of the invention

Problems to be solved by the invention

[0005] However, a method of using a low-speed and low-accuracy RTC to maintain time synchronization and activating VCTCXO only for receiving signals from the base station, receiving signals from base stations in other cells. If applied as it is, time synchronization cannot be maintained.

[0006] That is, in order to maintain the time synchronization described above, the PCH signal of its own cell is received by activating the high-precision VCT CXO, and the time synchronization with the PCH signal of its own cell is highly accurate using VCTCXO. It is assumed that VCTCXO will be stopped in a state where it can be removed, so if the VC TCXO is stopped in a state where the BCCH signal and time synchronization of other cells are accurately taken using VCTCXO, The time synchronization with the PCH signal of the own cell is not accurate, and if this is repeated, the error components are accumulated and the error components are added, exceeding the time width of the reception window, and time synchronization is performed. It cannot be maintained.

[0007] Therefore, when receiving a signal from a base station in another cell, a high-speed clock is required until the signal from the base station in the own cell is received and the signal of the base station power in another cell is received. As a result, power consumption cannot be reduced and standby time cannot be extended! /,When! Have a challenge! /

[0008] An object of the present invention is to activate a high-speed and high-accuracy VCTCXO only when receiving a signal from a base station and extend a standby time even when receiving a signal from a base station of another cell. It is providing the intermittent reception control apparatus which can do.

Means for solving the problem

[0009] The intermittent reception control apparatus according to the present invention provides a first control that is transmitted from a base station of the own cell using a paging channel in a part of the first period every first period of a predetermined length. Provided in a communication terminal device that intermittently receives a signal and intermittently receives a second control signal transmitted from the base station power of another cell every second period longer than the first period, and has a relatively low speed and low accuracy. In an intermittent reception control device that uses a clock to maintain time synchronization and receives the first and second control signals using a relatively high-speed and high-accuracy high-speed clock, the second control signal is Within the first period to be received, timing control means for controlling reception timing so as to start reception of the first control signal after completion of reception of the second control signal, and control of the timing control means Based on the cell switching means for switching the cell of the communication partner, and within the first period for receiving the second control signal, the reception start power of the second control signal until the reception of the first control signal is completed. In the period said high speed black A configuration that includes an activation means for activating the click, the.

The invention's effect

[0010] According to the present invention, in a short period of receiving a signal transmitted from a base station of another cell, immediately after receiving a signal transmitted from the base station of another cell, Receive the signal of the own cell, and activate the high-speed clock only during the period from the start of reception of the signal transmitted by the base station of another cell until the completion of reception of the signal transmitted by the base station of the own cell. can do. As a result, even when a signal transmitted from a base station in another cell is received, as in the case of receiving a signal transmitted from the base station in its own cell, only when a signal is received from the base station, high speed is received. In addition, high-precision VCTCXO can be activated, reducing power consumption and extending standby time.

Brief Description of Drawings

FIG. 1 is a block diagram showing the configuration of an intermittent reception control apparatus according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing the configuration of a time synchronization timer according to Embodiment 1.

FIG. 3 is a timing diagram of the time synchronization timer at the start of the counter in the first embodiment.

[FIG. 4] Timing diagram of time synchronization timer at frame interrupt in embodiment 1.

FIG. 5 is a timing diagram of the time synchronization timer at the end of the counter in the first embodiment.

FIG. 6 is a block diagram showing a configuration of a sleep timer in the first embodiment

FIG. 7 is a timing diagram of the sleep timer in the first embodiment.

FIG. 8 is a block diagram showing a configuration of a frequency error measurement unit in the first embodiment. FIG. 9 is a timing diagram of the frequency error measurement unit in the first embodiment.

FIG. 10 is a block diagram showing a CPU configuration in the first embodiment.

[Fig. 11] Sequence diagram for receiving PCH signal of base station power of own cell in embodiment 1.

[FIG. 12] Sequence diagram when receiving a BCCH signal of the base station of another cell in the first embodiment

FIG. 13 is a sequence diagram when a BCCH signal is received from a base station of another conventional cell. FIG. 14 is a frame mapping diagram of a common control channel in GSM according to Embodiment 1 of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

[0013] (Embodiment 1)

FIG. 1 is a block diagram showing the configuration of the intermittent reception control apparatus of the present invention. As shown in the figure, the intermittent reception control apparatus 100 is connected to the reception processing unit 113 shown in the figure via a bus. The reception processing unit 113 receives a signal transmitted from a base station (not shown) via an antenna, and performs a radio reception process (such as AZD conversion and down-conversion) on the received signal to generate a baseband signal. Output to the intermittent reception control device 100.

The intermittent reception control device 100 includes a high-speed clock 101, a time synchronization timer 102, a low-speed clock 103, a sleep timer 104, a frequency error measurement unit 105, and a CPU 106. The sleep timer 104 uses the low-speed clock 103 as the clock source, the CPU start interrupt signal S108 to the CPU 106, the high-speed clock start signal S109 to the high-speed clock 101, the time synchronization timer start signal S110 to the time synchronization timer 102, and the frequency error measurement start The signal S 111 is supplied to the frequency error measuring unit 105. The high-speed clock 101 starts when the high-speed clock start signal S 109 from the sleep timer 104 is at the H (High) level, and stops when it is at the L (Low) level. The time synchronization timer 102 starts when the time synchronization timer start signal S110 from the sleep timer 104 is at H level using the high-speed clock 101 as a clock source, and stops when it is at L level. While the time synchronization timer 102 is running, the frame interrupt signal S107 is sent to the CPU10. Supply to 6. The frequency error measurement unit 105 uses the high-speed clock 101 and the low-speed clock 103 as the clock source and starts up with the H-level pulse of the frequency error measurement start signal S111, and sends the frequency error measurement end interrupt signal S112 to the CPU 106 when the frequency error measurement ends. Supply. The CPU 106 receives the frame interrupt signal S107, the CPU start interrupt signal S108, and the frequency error measurement end interrupt signal S112, and also registers the time synchronization timer 102, sleep timer 104, and frequency error measurement unit 105. To access.

Next, details of the time synchronization timer 102, the sleep timer 104, the frequency error measuring unit 105, and the CPU 106 will be described using FIG. 2 to FIG. 10, respectively. The frequency of the high-speed clock 101 is 26 MHz, which is common in the GSM system, and the frequency of the low-speed clock 103 is 32.768 kHz, which is common as a clock for clocks.

FIG. 2 is a block diagram showing the configuration of the time synchronization timer 102. The time synchronization timer 102 includes a 1Z24 frequency divider 201, a rising edge detection unit 202, a time synchronization counter 203, a counter start time setting register 204, a counter end time register 205, a frame interrupt time setting register 206, Comparator 207 and flip-flop 208 are provided, and time synchronization counter 203 circulates from 0 to 4999 using 26 MHz, which is a high-speed clock, divided by 24 by 1Z24 frequency divider 201 using 1.083 MHz as a clock source. The counter start time setting register 204, the counter end time register 205, and the frame interrupt time setting register 206 are connected to the CPU bus.

[0017] The operation of the time synchronization timer 102 will be described with reference to FIGS. Figure 3 shows the timing diagram of the time synchronization timer 102 at the start of the counter. At the rising edge of the time synchronization timer start signal S110, the data in the counter start time setting register 204 set through the CPU bus is loaded into the time synchronization counter 203, and the 1Z24 frequency divider 201 starts generating a 1.083 MHz signal. Thus, the operation of the time synchronization counter 203 is started.

FIG. 4 shows a timing chart of the time synchronization timer 102 at the time of frame interruption. While the time synchronization timer start signal S110 is at the H level, the data of the frame interrupt time setting register 206 and the output of the time synchronization counter 203 are compared by the comparator 207. After the delay of one cycle of 1.083MHz by 208, Interrupt signal S107 is generated.

FIG. 5 shows a timing chart of the time synchronization timer 102 at the end of the counter. At the fall of the time synchronization timer start signal S110, the 1Z24 frequency divider 201 stops the 1.083 MHz signal generation, and the time synchronization counter 203 stops operating. At this time, the CPU 106 can read the output of the time synchronization counter 203 from the counter end time register 205. The time-synchronized timer start signal S110 is generated using a low-speed clock of 32.768 kHz as the clock source and is not synchronized with the high-speed clock of 26 MHz. Error 301 is generated. In addition, because it is not synchronized with 1.0833MHz, which is a high-speed clock of 26MHz divided by 24, as shown in Fig. 5, an error 501 for one cycle of 1.008MHz at maximum occurs.

FIG. 6 is a block diagram showing the configuration of the sleep timer 104. The sleep timer 104 includes a sleep counter 601, a counter start setting register 602, a rising edge detection unit 603, a CPU start interrupt time setting register 604, a high speed clock start time setting register 605, and a time synchronization timer start time setting register. 606, frequency error measurement start time setting register 607, sleep counter end time setting register 608, comparator 609 force 613, and flip-flops 614 to 620. CPU start interrupt time setting register 604, high-speed clock start time setting register 605, time synchronization timer start time setting register 606, frequency error measurement start time setting register 607, and sleep counter end time setting register 608 Data is set by the CPU 106 in advance.

FIG. 7 shows a timing chart of the sleep timer 104. By setting 1 to the counter start setting register 602 from the CPU 106, the EN input signal 630 to the sleep counter 601 becomes H level, and the sleep counter 601 starts operation with a low-speed clock of 32.768 kHz as the clock source. Further, the high-speed clock start signal S109 and the time synchronization timer start signal S110 become L level. The data in CPU start interrupt time setting register 604 and the output of sleep counter 601 are compared by comparator 609. When the two match, the flip flop 614 delays by one cycle of 32.768 kHz, and then the CPU start interrupt Signal S108 is generated. When the data of the high-speed clock start time setting register 605 and the output of the sleep counter 601 are compared by the comparator 610 and they match, the flip-flop 615 After that, the high-speed clock start signal S109 becomes H level after being delayed by one cycle of 32.768kHz. The data of the time synchronization timer start time setting register 606 and the output of the sleep counter 6 01 are compared by the comparator 611. When the two match, the flip-flop 6 16 delays by one cycle of 32.768 kHz and then time synchronization Timer start signal S110 becomes H level. Frequency error measurement Start-up time setting register 607 data and sleep power counter 601 output are compared by comparator 612. When they match, frequency error measurement is performed after a delay of 32.768 kHz by flip-flop 617. Activation signal S111 is generated. The data of the sleep counter end time setting register 608 and the output of the sleep counter 601 are compared by the comparator 613. When the two match, the counter is set by the flip-flop 618 and delayed by one cycle of 32.768 kHz. RESET input signal to 602 is generated. As a result, the EN input signal power ^S L level to the sleep counter 601 is set, and the sleep counter 601 stops its operation.

FIG. 8 is a block diagram showing the configuration of the frequency error measurement unit 105. The frequency error measurement unit 105 includes a low-speed clock counter 801, a 5 × multiplier 802, a high-speed clock counter 803, a power counter start setting register 804, a low-speed clock counter end time setting register 805, and a low-speed clock counter end time. A register 806, a high-speed clock counter end time register 807, a comparator 808, and flip-flops 809 to 810 are included. In the low-speed clock power counter end time setting register 805, data is previously set by the CPU 106 through the CPU bus.

FIG. 9 shows a timing chart of the frequency error measurement unit 105. The power to set 1 to the counter start setting register 804 from the CPU 106, and the frequency error measurement start signal SI11 to H level, the EN input signal S830 to the low speed clock counter 801 and the high speed clock counter 803 becomes H level. . As a result, the low-speed clock counter 801 starts operation using the low-speed clock 32.768 kHz as the clock source, and the high-speed clock counter 803 clocks the high-speed clock 26 MHz multiplied by 5 times with the 5 × multiplier 802 to 130 Hz. Start operation as a source. The data of low-speed clock counter end time setting register 805 and the output of low-speed clock counter 801 are compared by comparator 808, and when they match, the frequency error is measured after being delayed by one cycle of 32.768kHz by flip-flop 809. End interrupt signal Signal S 112 is generated, and both the low-speed clock counter 801 and the high-speed clock counter 803 stop operating. At this time, the outputs of the low-speed clock counter 801 and the high-speed clock counter 803 can be read by the CPU 106 from the low-speed clock counter end time register 806 and the high-speed clock counter end time register 807, respectively. Note that 32.768 kHz, which is the clock source of the low-speed clock counter 801, and 130 MHz, which is the clock source of the high-speed clock counter 803, are not synchronized. An error of the period (901 and 902) is generated.

FIG. 10 is a block diagram showing the configuration of the CPU 106. The CPU 106 includes a demodulation processing unit 1001, a timing control unit 1002, a cell switching unit 1003, and an activation time calculation unit 1004.

The demodulation processing unit 1001 receives the frame interrupt signal S 107 and performs demodulation processing on the baseband signal output from the reception processing unit 113 through the CPU bus.

[0026] When it is determined that the BCCH signal of the other cell is transmitted within the short period in which the PCH signal of the own cell is transmitted, the timing control unit 1002 completes the reception of the BCCH signal of the other cell. The reception timing of the PCH signal of the own cell is determined so that the reception of the PCH signal of the own cell is started immediately after the timing to perform. The timing control unit 1002 sends the timing information indicating the timing of starting reception of the PCH signal of the own cell and the timing of starting reception of the BCCH signal of the other cell to the cell switching unit 1003 and the activation time calculating unit 1004. Output.

Cell switching section 1003 outputs cell switching signal S 114 to reception processing section 113 according to the timing information. Specifically, cell switching section 103 outputs cell switching signal S114 for switching the communication partner to its own cell to reception section 113 at the timing of starting reception of the PCH signal of its own cell, and receives PCH signals of other cells. The cell switching signal S114 for switching the communication partner to another cell at the timing of starting reception of the signal is output to the receiving unit 113. The reception processing unit 113 switches the communication partner to either the own cell or another cell in response to the cell switching signal S114.

[0028] When the activation time calculation unit 1004 receives the PCH signal of its own cell, it calculates the number of frames that can sleep until the next received wave to be received (hereinafter referred to as "intermittent period"). Data corresponding to the intermittent period is stored in each register of the synchronous timer 102 and the sleep timer 104. Set via CPU bus.

Next, the operation of intermittent reception control apparatus 100 configured as described above will be described using the sequence diagrams of FIGS. 11 to 13. In FIGS. 11 to 13, the time axis is taken from left to right, and the low-speed clock 103, high-speed clock 101, sleep timer 104, CPU 106, CPU start interrupt signal 108, high-speed clock start signal S 109, time synchronization The timing chart of timer start signal S110, frequency error measurement start signal Slll, frequency error measurement end interrupt signal S112, time synchronization timer 102, frame interrupt signal S107, reception window, and reception wave is shown. Further, the specific time of the low-speed clock will be described as (0), (1), (2), etc.

FIG. 11 is a sequence diagram when receiving the PCH signal of the own cell and further receiving the PCH signal of the own cell after a certain period. At time (0), the CPU activation interrupt signal S108 is generated and the CPU 106 is activated. Based on this interrupt signal, the timing control unit 1002 in the CPU 106 determines the timing for receiving the PCH signal of its own cell, and the activation time calculation unit 1004 determines the counter start time setting register of the time synchronization timer 102 from the reception timing. The data to be set in the register 204 is calculated, and the calculated data is set in the counter start time setting register 204. The calculation is based on the data of the low-speed clock counter end time register 806 of the frequency error measuring unit 105, the data of the high-speed clock counter end time register 807, and the counter of the time synchronization timer 102 obtained by the previous frequency error measurement. Calculates the force received in the reception window where the data received in the time register 205, the data set in the time synchronization timer activation time setting register 606 of the sleep timer 104, and the synchronization word reception position of the PCH signal received last time And calculated time tracking amount. That is, the activation time calculation unit 1004 determines how many clocks of 1.083 MHz corresponds to the interval in which the time synchronization timer activation signal S110 power level corresponds to the low-speed clock counter end time register 806 of the frequency error measurement unit 105. It is calculated from the ratio of the data and the data in the high-speed clock counter end time register 807, and is added to the data in the power counter end time register 205 of the time synchronization timer 102, and the time tracking amount is added. Calculate the remainder of 5000.

[0031] At time (1), the high-speed clock activation signal S109 becomes H level and the high-speed clock 101 is activated. At time (2), the time synchronization timer start signal S110 becomes H level, The value of the counter start time setting register 204 set by the time synchronization counter 203 at time (0) also starts counting. At time (3), frequency error measurement start signal S111 is generated and frequency error measurement is started. At time (4), the sleep timer 104 stops. At time (5), the frequency error measurement ends, and a frequency error measurement end interrupt signal S 112 is generated. At time (6), from the information about the reception timing determined by the timing control unit 1002 in the CPU 106, the activation time calculation unit 1004 calculates how many frames can sleep (intermittent cycle). In the example shown in FIG. 11, since the received wave to be received next is the signal of the own cell, activation time calculation section 1004 calculates the time from P1 to the next P1 in FIG. 11 as an intermittent period. Then, the activation time calculation unit 1004 includes a CPU activation interrupt time setting register 604, a high-speed clock activation time setting register 605, a time synchronous timer activation time setting register 606, a frequency error measurement activation time setting register 607, Data corresponding to the intermittent period is set in the leave counter end time setting register 608, and 1 is further set in the counter start setting register 602 of the sleep timer 104. As a result, the sleep timer 104 is started, the high-speed clock start signal S 109 becomes L level and the high-speed clock stops, and the time synchronization timer start signal S 110 becomes L level and the time synchronization timer 102 stops. . At time (7), the demodulation processing unit 1001 in the CPU 106 stops itself. Here, from time (2) to time (6), the reception processing unit 113 receives four bursts of PCH signals shown from P1 to P4. The size of the reception window at this time is the sum of the error shown in Figs. 3 and 5 and the error of the time synchronization timer calculated based on the frequency error measurement result in Fig. 9 for the received wave. It needs to be open more widely than it does.

[0032] FIG. 12 is a sequence diagram in the case of receiving a BCCH signal of another cell in a short period. As described above, the present invention is based on receiving the PCH signal of the own cell and receiving the PCH signal of the own cell without receiving a gap after receiving the BCCH signal of the other cell. The feature is that time synchronization is maintained. This will be described in detail below.

[0033] From time (0) to time (5) is the same as in FIG. Here, after time (2), reception processing section 113 receives four bursts of BCCH signals of other cells shown in B1 to B4. After that, the reception processing unit 113 displays the PCH signal of its own cell shown in S1 to S4 in 4 bars. The timing control unit 1002 determines the reception timing so that the cell switching signal S114 is output to the reception processing unit 113 according to the determined reception timing information, and the reception processing unit 113 receives the base station of its own cell phone. Receive a signal. When the reception processing unit 113 receives the PCH signal of its own cell, the activation time calculation unit 1004 in the CPU 106 calculates the data to be set in the counter start time setting register 204 of the next time synchronization timer 102. The amount of tracking used for the calculation can be calculated using the reception timing of the PCH signal of the own cell. That is, after the reception processing unit 113 receives four bursts of the PCH signal of its own cell shown in S1 to S4, the same operation as the operation at time (6) and time (7) in FIG. 14 is performed at the time in FIG. This is done as (6) and time (7).

That is, according to the present invention, from time (2) to time (5), the reception processing unit 113 receives 4 bursts of BCCH signals of other cells indicated by B1 force and B4. Immediately thereafter, the cell switching unit 1002 outputs a cell switching signal S114 to the reception processing unit 113, and the reception processing unit 113 switches the communication partner from the base station of another cell to the base station of its own cell. It receives 4 bursts of the PCH signal of its own cell shown in S4. Then, at time (6), the activation time calculation unit 1004 in the CPU 106 calculates the intermittent period until the next reception of the PCH signal of the own cell using the timing at which the PCH signal of the own cell is received. In response to the intermittent period, the activation time calculation unit 1004 activates the sleep timer 104. As a result, the high-speed clock stops and the time synchronization timer stops. Then, at time (7), the demodulation processing unit 1001 in the CPU stops.

[0035] As a result, the clock clock (RTC), which is low speed and low accuracy, is used to maintain time synchronization, and the VCTCXO is activated only when a signal is received from the base station. An intermittent reception control apparatus that can be applied to a signal having a base station power is realized. It also makes it possible to extend the standby time of wireless devices.

On the other hand, FIG. 13 shows a sequence diagram when a signal from the base station power of another cell is received after receiving a signal from the base station of the own cell within a short period. In other words, FIG. 13 shows an example in which the reception timing, which is a feature of the present invention, is not adjusted.

[0037] First, at time (0), when the CPU activation interrupt signal 108 is input from the sleep timer 104 to the CPU 106, the CPU 106 becomes active. Next, from the sleep timer 104 at time (1) When the high-speed clock start signal S109 is input, the high-speed clock 101 is started. When the time synchronization timer start signal S110 is input from the sleep timer 104 at time (2), the time synchronization timer 102 becomes active. At time (3), the frequency error measurement activation signal S111 is generated, and the frequency error measurement unit 105 starts frequency error measurement. Then, the sleep timer 104 is stopped at time (4), the frequency error measurement is ended at time (5), and the frequency error measurement end interrupt signal S112 is generated. At time (6), the sleep timer 104 starts, the high-speed clock start signal S109 becomes L level and the high-speed clock 101 stops, and the time synchronization timer start signal S110 becomes L level and the time synchronization timer 102 stops. To do. At time (7), the CPU 106 stops itself.

[0038] After time (2), 4 burst signals of the own cell PH shown in P1 to P4 are received. When the timing control unit 1002 in the CPU 106 determines that the next received wave to be received is the BCCH signal of another cell, the activation time calculation unit 1004 receives the BCCH signal of the other cell. The time until the next PCH signal of the own cell is received is calculated as the intermittent period. As a result, the high-speed clock 101 and the time synchronization timer 102 do not stop and continue to operate until a frame for receiving a BCCH signal of another cell shown in B1 to B4. That is, the high-speed clock 101 cannot be stopped until the BCCH signal of another cell is received, current consumption increases, and it becomes difficult to shorten the standby time.

FIG. 14 shows a frame mapping diagram of the control channel in the GSM scheme. In the GSM system, the control channel frame circulates in 51 cycles. In the figure, CCCH is the common control channel and FCCH is the frequency correction channel. Since BCCH and CCCH are normal bursts, any of 4 bursts of signals from the base station of the own cell may be selected as long as they are BCCH signals or CCCH signals. For example, 4 bursts of frame numbers (# 5, # 6, # 7, # 8) may be selected, or 4 bursts of (# 8, # 9, # 12, # 13) may be selected. Alternatively, instead of using 4 normal bursts, it is possible to receive one burst of SCH signal and obtain the time tracking amount. In short, the PCH from the own cell immediately after the timing of receiving the BCCH signal from another cell. Is now received! /! [0040] As described above, according to the present invention, after receiving the signal of the base station power of another cell, the base station power signal of the own cell is received and the time synchronization is maintained. An intermittent reception control device that can also be applied to signals from the cell base station is obtained, and the standby time of the wireless terminal communication device can be extended. It is assumed that synchronization is acquired in advance for base stations in other cells.

[0041] In the present embodiment, the power described using specific numerical values such as clock frequency as an example of the GSM system is not limited to the GSM system, and can be applied to various communication systems.

[0042] Based on Japanese Patent Application 2005—060148, filed on April 4, 2005. This content [all included here.

Industrial applicability

[0043] The intermittent reception control apparatus according to the present invention is an intermittent reception control apparatus that can be applied to a signal of a base station of another cell, and is useful as a wireless terminal communication apparatus that can extend the standby time. It is.

Claims

The scope of the claims

[1] intermittently receiving a first control signal transmitted using a base channel power of the own cell in a part of the first period for each first period of a predetermined length, Provided in a communication terminal device that intermittently receives a second control signal transmitted from the base station power of another cell every second period longer than one period,

In the intermittent reception control device for maintaining time synchronization using a relatively low-speed and low-accuracy low-speed clock and receiving the first and second control signals using a relatively high-speed and high-accuracy high-speed clock,

Timing control means for controlling reception timing so that reception of the first control signal is started after completion of reception of the second control signal within the first period of receiving the second control signal. ,

A cell switching means for switching a communication partner cell based on the control of the timing control means;

An activation means for activating the high-speed clock during a period from the start of reception of the second control signal to the completion of reception of the first control signal within the first period of receiving the second control signal;

An intermittent reception control apparatus comprising:

[2] The second control signal is a broadcast control channel, a common control channel, or a synchronization channel signal.

The intermittent receiving device according to claim 1.