JP2008124524A - Intermittent reception control apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an intermittent reception control apparatus applicable to reception of a signal from a base station in another cell, the control apparatus achieving elongation of a standby time. <P>SOLUTION: The intermittent reception control apparatus has a high-rate clock, a low-rate clock, a time synchronization timer, a sleep timer, a frequency error measuring means and a CPU. The frequency error measuring means measures a frequency error between the high-rate clock and low-rate clock and is controlled with a frequency error measurement start signal from the sleep timer and by the CPU, whereas the time synchronization timer is operated with the high-rate clock and the sleep timer is operated with the low-rate clock. The CPU is controlled with a frame interruption signal from the time synchronization timer, a CPU start interruption signal from the sleep timer, and a frequency error measurement end interruption signal from the frequency error measuring means. Consequently, the intermittent reception control apparatus receives a signal from a base station in its cell after receiving a signal from the base station in the other cell to maintain time synchronism. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an intermittent reception control device applied to a mobile station of a wireless communication device such as a mobile phone.

An operation required during standby of the mobile phone is to periodically receive a paging channel (PCH) which is a signal mainly from the base station of the own cell. The PCH is assigned with a period of several hundred milliseconds to several seconds, and the reception only takes time of several milliseconds to several tens of milliseconds, and other times only maintain time synchronization. . Receiving a signal from the base station requires a high-speed and high-accuracy voltage-controlled temperature-compensated crystal oscillator (VCTCXO), and maintaining VCTCXO while maintaining the time synchronization that occupies most of the waiting time. The synchronous timer was circulated. However, in order to extend the standby time in recent years, a method has been proposed in which a low-speed and low-precision clock (RTC) is used to maintain time synchronization, and VCTCXO is activated only when a signal is received from a base station. (For example, refer to Patent Document 1).
JP 2000-49682 A (page 4)

  However, as a necessary operation during the standby of the mobile phone, a signal from a base station of another cell, although it has a long period of several tens of seconds or several minutes, other than periodically receiving PCH as described above, Must also receive. For example, in the GSM system, a synchronization channel (SCH) from a base station of another cell having a maximum electric field strength of 6 must be received once every 30 seconds, and the field strength of the other cell having a maximum electric field strength of 6 The broadcast control channel (BCCH) from the base station must be received once every 5 minutes.

  On the other hand, the conventional intermittent reception control apparatus suppresses various error components caused by the stop of the high-speed clock within the time width of the reception window, and finally receives PCH which is a signal from the base station of the own cell. The time synchronization is maintained by calculating where the reception position of the synchronization word is received in the reception window and performing time tracking based on the calculation result.

  However, this method cannot be applied to reception of signals from base stations in other cells. Because time tracking to maintain time synchronization is not possible for signals from base stations in other cells, various error components caused by stopping the high-speed clock cannot be canceled out. This is because the components are integrated and eventually exceed the time width of the reception window. Therefore, when receiving a signal from a base station of another cell, there is a problem that the high-speed clock cannot be stopped.

  FIG. 13 shows a block diagram of a conventional intermittent reception control apparatus. The intermittent reception control apparatus 1000 includes a high-speed clock 101, a time synchronization timer 102, a low-speed clock 103, a sleep timer 104, a frequency error measuring unit 105, and a CPU 106.

  FIG. 14 shows a sequence diagram when receiving a BCCH from a base station of another conventional cell. In FIG. 14, the time axis is taken from left to right, and the low speed clock 103, high speed clock 101, sleep timer 104, CPU 106, CPU start interrupt signal 108, high speed clock start signal 109, time synchronization timer start signal 110, frequency error measurement. The timing diagram of the start signal 111, the frequency error measurement end interrupt signal 112, the time synchronization timer 102, the frame interrupt signal 107, the reception window, and the reception wave is shown. In FIG. 14, the specific time of the low-speed clock will be described as (0), (1), (2), and the like. First, at time (0), when the CPU activation interrupt signal 108 is input from the sleep timer 104 to the CPU 106, the CPU 106 becomes active. Next, when the high-speed clock activation signal 109 is input from the sleep timer 104 at time (1), the high-speed clock 101 is activated. When the time synchronization timer activation signal 110 is input from the sleep timer 104 at time (2), the time synchronization timer 102 becomes active. At time (3), a frequency error measurement start signal 111 is generated, and the frequency error measurement means 105 starts frequency error measurement. Then, the sleep timer 104 stops at time (4), the frequency error measurement ends at time (5), and the frequency error measurement end interrupt signal 112 is generated. At time (6), the sleep timer 104 starts, the high-speed clock start signal 109 becomes L level and the high-speed clock 101 stops, and the time synchronization timer start signal 110 becomes L level and the time synchronization timer 102 stops. . At time (7), the CPU 106 stops itself.

  After time (2), four bursts of the PCH of the own cell indicated by P1 to P4 are received. If the CPU 106 determines that the next received wave to be received is the BCCH from the base station of another cell, the high-speed clock 101 and the time synchronization timer 102 are not stopped and the bases of the other cells shown in B1 to B4 are not stopped. Waiting for a frame to receive BCCH from the station. As described above, conventionally, the high-speed clock 101 cannot be stopped until the BCCH of the base station of another cell is received. Therefore, the current consumption increases and it is difficult to shorten the standby time.

  The present invention solves the above-described conventional problem, and uses a clock (RTC) having a low speed and low accuracy for maintaining time synchronization, and the VCTCXO is activated only when a signal is received from a base station. However, an object of the present invention is to provide an intermittent reception control apparatus that can be applied to reception of signals from base stations in other cells and can extend the standby time.

  In order to solve the above-described conventional problem, the intermittent reception control apparatus of the present invention includes a high-speed clock, a time synchronization timer, a low-speed clock, a sleep timer, a frequency error measurement unit, and a CPU, Time synchronization is maintained by receiving a signal from the base station of the own cell after receiving a signal from the base station.

  According to the intermittent reception control device of the present invention, the time synchronization is maintained by receiving the signal from the base station of the own cell after receiving the signal from the base station of the other cell and maintaining the time synchronization. A low-speed and low-accuracy clock (RTC) is used for maintenance, and the VCTCXO is activated only when a signal is received from the base station, and is intermittently applicable to signals from base stations in other cells. A reception control device is obtained, and the standby time of the wireless communication device can be extended.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 shows a block diagram of the intermittent reception control apparatus of the present invention. The intermittent reception control apparatus 100 includes a high-speed clock 101, a time synchronization timer 102, a low-speed clock 103, a sleep timer 104, a frequency error measuring unit 105, and a CPU 106. The sleep timer 104 uses the low-speed clock 103 as a clock source, the CPU activation interrupt signal 108 to the CPU 106, the high-speed clock activation signal 109 to the high-speed clock 101, the time synchronization timer activation signal 110 to the time synchronization timer 102, and the frequency error measurement activation signal. 111 is supplied to the frequency error measuring means 105, respectively. The high-speed clock 101 starts when the high-speed clock start signal 109 from the sleep timer 104 is at H (High) level, and stops when it is at L (Low) level. The time synchronization timer 102 starts when the time synchronization timer activation signal 110 from the sleep timer 104 is at the H level using the high-speed clock 101 as a clock source, and stops when it is at the L level. Further, the frame interrupt signal 107 is supplied to the CPU 106 while the time synchronization timer 102 is activated. The frequency error measuring means 105 is started by using the high-speed clock 101 and the low-speed clock 103 as clock sources and by the H level pulse of the frequency error measurement start signal 111, and supplies the frequency error measurement end interrupt signal 112 to the CPU 106 when the frequency error measurement ends. . The CPU 106 receives the frame interrupt signal 107, the CPU activation interrupt signal 108, and the frequency error measurement end interrupt signal 112, and accesses the registers of the time synchronization timer 102, the sleep timer 104, and the frequency error measuring means 105.

  Next, details of the time synchronization timer 102, the sleep timer 104, and the frequency error measuring means 105 will be described with reference to FIGS. The frequency of the high-speed clock 101 is 26 MHz, which is common in the GSM system, and the frequency of the low-speed clock 103 is 32.768 kHz, which is common as a clock for a clock.

  FIG. 2 shows a block diagram of the time synchronization timer 102. The time synchronization timer 102 includes a 1/24 frequency divider 201, a rising edge detection unit 202, a time synchronization counter 203, a counter start time setting register 204, a counter end time register 205, and a frame interrupt time setting register 206. The time synchronization counter 203 circulates from 0 to 4999 using a clock source of 1.083 MHz, which is obtained by dividing the high-speed clock 26 MHz by the 1/24 frequency divider 201, with a comparator 207 and a flip-flop 208. . The counter start time setting register 204, the counter end time register 205, and the frame interrupt time setting register 206 are connected to the CPU bus.

  The operation of the time synchronization timer 102 will be described. FIG. 3 shows a timing chart of the time synchronization timer 102 at the start of the counter. At the rise of the time synchronization timer activation signal 110, the data of the counter start time setting register 204 set through the CPU bus is loaded into the time synchronization counter 203, and the 1.04 MHz signal generation is started in the 1/24 frequency divider 201. Then, the operation of the time synchronization counter 203 is started.

  FIG. 4 shows a timing chart of the time synchronization timer 102 at the time of frame interruption. While the time synchronization timer activation signal 110 is at the H level, the data of the frame interrupt time setting register 206 and the output of the time synchronization counter 203 are compared by the comparator 207. After being delayed by one cycle of 083 MHz, the frame interrupt signal 107 is generated.

  FIG. 5 shows a timing chart of the time synchronization timer 102 at the end of the counter. When the time synchronization timer activation signal 110 falls, the 1/24 frequency divider 201 stops the 1.083 MHz signal generation, and the time synchronization counter 203 stops operating. At this time, the output of the time synchronization counter 203 can be read by the CPU 106 from the counter end time register 205. The time synchronization timer start signal 110 is generated using a low-speed clock of 32.768 kHz as a clock source and is not synchronized with the high-speed clock of 26 MHz. Therefore, as shown in FIG. Error 301 occurs. Further, since it is not synchronized with 1.083 MHz obtained by dividing the high-speed clock 26 MHz by 24, an error 501 corresponding to one cycle of 1.083 MHz at maximum is also generated as shown in FIG.

  A block diagram of the sleep timer 104 is shown in FIG. The sleep timer 104 includes a sleep counter 601, a counter start setting register 602, a rising edge detection unit 603, a CPU activation interrupt time setting register 604, a high-speed clock activation time setting register 605, and a time synchronization timer activation time setting register 606. And a frequency error measurement start time setting register 607, a sleep counter end time setting register 608, comparators 609 to 613, and flip-flops 614 to 620. The CPU 106 stores the CPU activation interrupt time setting register 604, the high-speed clock activation time setting register 605, the time synchronization timer activation time setting register 606, the frequency error measurement activation time setting register 607, and the sleep counter end time setting register 608 in advance. Set the data.

  FIG. 7 shows a timing chart of the sleep timer 104. By setting 1 to the counter start setting register 602 from the CPU 106, the EN input signal 630 to the sleep counter 601 becomes H level, and the sleep counter 601 starts operation with a low-speed clock of 32.768 kHz as a clock source. Further, the high-speed clock activation signal 109 and the time synchronization timer activation signal 110 become L level. The data of the CPU activation interrupt time setting register 604 and the output of the sleep counter 601 are compared by the comparator 609, and when they match, the CPU activation interrupt is delayed by one cycle of 32.768 kHz by the flip-flop 614. A signal 108 is generated. The data of the high-speed clock start time setting register 605 and the output of the sleep counter 601 are compared by the comparator 610, and when they match, the high-speed clock start signal 109 is delayed by one cycle of 32.768 kHz by the flip-flop 615. Becomes H level. The data of the time synchronization timer start time setting register 606 and the output of the sleep counter 601 are compared by the comparator 611. When the two match, the time synchronization timer is started after being delayed by one cycle of 32.768 kHz by the flip-flop 616. The signal 110 becomes H level. The data of the frequency error measurement start time setting register 607 and the output of the sleep counter 601 are compared by the comparator 612. When the two match, the flip-flop 617 delays by one cycle of 32.768 kHz and starts the frequency error measurement. A signal 111 is generated. The data of the sleep counter end time setting register 608 and the output of the sleep counter 601 are compared by the comparator 613. When the two match, the counter start setting register 602 is delayed by one cycle of 32.768 kHz by the flip-flop 618. A RESET input signal is generated. As a result, when the EN input signal to the sleep counter 601 becomes L level, the sleep counter 601 stops its operation.

  FIG. 8 shows a block diagram of the frequency error measuring means 105. Low-speed clock counter 801, five-fold multiplier 802, high-speed clock counter 803, counter start setting register 804, low-speed clock counter end time setting register 805, low-speed clock counter end time register 806, and high-speed clock counter end time register 807, a comparator 808, and flip-flops 809 to 810. The CPU 106 sets data in advance in the low-speed clock counter end time setting register 805 through the CPU bus.

  FIG. 9 shows a timing chart of the frequency error measuring means 105. When the CPU 106 sets 1 to the counter start setting register 804 or the frequency error measurement activation signal 111 becomes H level, the EN input signal 830 to the low speed clock counter 801 and the high speed clock counter 803 becomes H level. As a result, the low-speed clock counter 801 starts operating with a low-speed clock of 32.768 kHz as a clock source, and the high-speed clock counter 803 starts operating with a high-speed clock of 26 MHz multiplied by 5 by a 5-times multiplier 802 as a clock source. To do. The data of the low-speed clock counter end time setting register 805 and the output of the low-speed clock counter 801 are compared by the comparator 808, and when they match, the frequency error is measured after being delayed by one cycle of 32.768 kHz by the flip-flop 809. An end interrupt signal 112 is generated, and both the low-speed clock counter 801 and the high-speed clock counter 803 stop operating. At this time, the outputs of the low-speed clock counter 801 and the high-speed clock counter 803 can be read by the CPU 106 from the low-speed clock counter end time register 806 and the high-speed clock counter end time register 807, respectively. Note that 32.768 kHz, which is the clock source of the low-speed clock counter 801, and 130 MHz, which is the clock source of the high-speed clock counter 803, are not synchronized with each other. Error (901 and 902).

  FIG. 10 is a sequence diagram when receiving PCH from the base station of the own cell. At time (0), a CPU activation interrupt signal 108 is generated and the CPU 106 is activated. Based on this interrupt signal, the CPU 106 calculates data to be set in the counter start time setting register 204 of the time synchronization timer 102 and sets the calculated data. The calculation is performed by the data of the low-speed clock counter end time register 806, the data of the high-speed clock counter end time register 807, and the counter end time of the time synchronization timer 102 obtained by the frequency error measurement performed previously. The data in the register 205, the data set in the time synchronization timer activation time setting register 606 of the sleep timer 104, and the time tracking amount calculated where in the reception window the reception position of the PCH synchronization word received last time is received. Calculate using. That is, the number of clocks corresponding to 1.083 MHz corresponding to the interval in which the time synchronization timer activation signal 110 is at the L level corresponds to the data in the low-speed clock counter end time register 806 of the frequency error measuring means 105 and the end of the high-speed clock counter. It is calculated from the ratio with the data in the time register 807, added to the data in the counter end time register 205 of the time synchronization timer 102, the time tracking amount is added, and the remainder of 5000 which is the period of the time synchronization counter 203 is calculated. At time (1), the high-speed clock activation signal 109 becomes H level and the high-speed clock 101 is activated. At time (2), the time synchronization timer activation signal 110 becomes H level, and the time synchronization counter 203 starts counting from the value of the counter start time setting register 204 set at time (0). At time (3), the frequency error measurement start signal 111 is generated and the frequency error measurement is started. At time (4), the sleep timer 104 stops. At time (5), the frequency error measurement ends, and a frequency error measurement end interrupt signal 112 is generated. At the time (6), the CPU 106 determines how many frames can sleep by determining what the received wave is to be received next. The CPU activation interrupt time setting register 604, the high-speed clock activation time setting register 605, the time synchronization timer activation time setting register 606, the frequency error measurement activation time setting register 607, and the sleep counter end time setting register 608 are preliminarily stored in the data. And the CPU 106 sets 1 in the counter start setting register 602 of the sleep timer 104 to start the sleep timer 104, the high-speed clock start signal 109 becomes L level, the high-speed clock stops, and time synchronization The timer activation signal 110 becomes L level and the time synchronization timer 102 stops. At time (7), the CPU 106 stops itself. Here, during time (2) to time (6), four bursts of PCH indicated by P1 to P4 are received. The size of the reception window at this time is a value obtained by adding the error shown in FIGS. 3 and 5 and the error of the time synchronization timer calculated based on the frequency error measurement result in FIG. 9 to the received wave. It needs to be opened wider than it does.

  FIG. 11 is a sequence diagram when receiving BCCH from a base station of another cell according to the present invention. The present invention is based on receiving a signal from the base station of the own cell and receiving a signal from the base station of the own cell without receiving a gap after receiving a signal from the base station of another cell. The feature is that time synchronization is maintained. This will be described in detail below.

  From time (0) to time (5) is the same as in FIG. Here, after time (2), four bursts of BCCH from base stations of other cells shown in B1 to B4 are received. Thereafter, four bursts of signals from the base station of the own cell shown in S1 to S4 are received. Where the reception position of the synchronization word was received in the reception window when calculating the data to be set in the counter start time setting register 204 of the next time synchronization timer 102 by receiving a signal from the base station of the own cell The amount of time tracking calculated is calculated. Specifically, after receiving four bursts of signals from the base station of the own cell shown in S1 to S4, the same operation as that at time (6) and time (7) in FIG. 10 is performed at time (6) in FIG. And the operation at time (7).

  That is, the present invention receives 4 bursts of BCCH from base stations of other cells indicated by B1 to B4 from time (2) to time (5). Thereafter, four bursts of signals from the base station of the own cell shown in S1 to S4 are received. At time (6), it is determined what received wave is to be received next, how many frames can be sleeped, the sleep timer is started, the high-speed clock is stopped, and the time synchronization timer is stopped. The CPU is stopped at time (7).

  As a result, the clock clock (RTC), which is low speed and low accuracy, is used for maintaining time synchronization, and the VCTCXO is activated only when receiving a signal from the base station. An intermittent reception control apparatus that can also be applied to signals is realized. And it is possible to extend the standby time of the wireless device.

  As described above, according to the present invention, after receiving a signal from the base station of another cell, the base station of the other cell is configured to receive the signal from the base station of the own cell and maintain time synchronization. An intermittent reception control device that can be applied to a signal from a station can be obtained, and the standby time of the wireless communication device can be extended. It is assumed that synchronization has already been acquired for base stations in other cells.

  FIG. 12 is a frame mapping diagram of the common control channel (CCCH) in the GSM scheme, which circulates in a cycle of 51 frames. FCCH is a frequency correction channel. Here, the four bursts of the signal from the base station of the own cell are normal bursts as long as they are BCCH and CCCH in FIG. For example, four bursts of frame numbers (# 5, # 6, # 7, # 8) or four bursts of (# 8, # 9, # 12, # 13) may be used. Alternatively, the time tracking amount may be obtained by receiving one burst of SCH instead of four normal bursts.

  In the present embodiment, the GSM scheme is described as an example using specific numerical values such as a clock frequency, but the present invention is not limited to the GSM scheme and can be applied to various communication schemes.

  The intermittent reception control apparatus according to the present invention is an intermittent reception control apparatus that can be applied to signals from base stations in other cells, and is useful as a wireless communication apparatus that can extend the standby time.

Block diagram of the intermittent reception control apparatus in Embodiment 1 of the present invention Block diagram of a time synchronization timer in Embodiment 1 of the present invention Timing diagram of time synchronization timer at start of counter in embodiment 1 of the present invention Timing chart of time synchronization timer at the time of frame interruption in Embodiment 1 of the present invention Timing chart of time synchronization timer at end of counter in embodiment 1 of the present invention Block diagram of sleep timer in embodiment 1 of the present invention Timing chart of sleep timer in embodiment 1 of the present invention Block diagram of frequency error measuring means in Embodiment 1 of the present invention Timing chart of frequency error measuring means in Embodiment 1 of the present invention Sequence diagram when receiving PCH from base station of own cell in Embodiment 1 of the present invention Sequence diagram for receiving BCCH from base station of other cell in Embodiment 1 of the present invention Frame mapping diagram of common control channel in GSM in Embodiment 1 of the present invention Block diagram of a conventional intermittent reception control device Sequence diagram for receiving BCCH from base station of other conventional cell

Explanation of symbols

101 High-speed clock 102 Time synchronization timer 103 Low-speed clock 104 Reap timer 105 Frequency error measuring means 106 CPU
107 frame interrupt signal 108 CPU start interrupt signal 109 high speed clock start signal 110 time synchronization timer start signal 111 frequency error measurement start signal 112 frequency error measurement end interrupt signal 201 1/24 frequency divider 202, 603 rising detection means 203 Time synchronization counter 204 Counter start time setting register 205 Counter end time register 206 Frame interrupt time setting register 207, 609, 610, 611, 612, 613, 808 Comparator 208, 614, 615, 616, 617, 618, 809 Flip-flop 601 Sleep counter 602 Counter start setting register 604 CPU activation interrupt time setting register 605 High-speed clock activation time setting register 606 Time synchronization timer activation time setting register 607 Frequency error Constant start time setting register 608 Sleep counter end time setting register 801 Low speed clock counter 802 Multiplier 803 High speed clock counter 804 Counter start setting register 805 Low speed clock counter end time setting register 806 Low speed clock counter end time register 807 High speed clock counter end time register

Claims (2)

In an intermittent reception control device comprising a high-speed clock, a time synchronization timer, a low-speed clock, a sleep timer, a frequency error measuring means, and a CPU, after receiving a signal from a base station of another cell, An intermittent reception control device that maintains time synchronization by receiving a signal from a station. The signal from the base station of the other cell and the base station of the own cell is a signal of a broadcast control channel (BCCH), a common control channel (CCCH), or a synchronization channel (SCH). 2. The intermittent reception control device according to 1.

Images