WO2006080666A1

WO2006080666A1 - Front end module

Info

Publication number: WO2006080666A1
Application number: PCT/KR2005/003229
Authority: WO
Inventors: Hong-Keun Park
Original assignee: Lg Innotek Co., Ltd
Priority date: 2004-10-01
Filing date: 2005-09-29
Publication date: 2006-08-03
Also published as: KR20060029307A; KR100608289B1

Abstract

An FEM is provided. The FEM includes a first substrate having a plurality of sheets stacked therein, a second substrate having a plurality of sheets stacked therein and sequentially disposed with respect to the first substrate, a first chip mounted on an inner space of the first substrate, and a second chip mounted on an inner space of the second substrate. Consequently, a chip for power amplification and a chip for a duplexer are not interfered with each other and a size of the FEM is minimized.

Description

Description FRONT END MODULE

Technical Field

[1] The present invention relates to a front end module (FEM), and more particularly, to an FEM that can be more miniaturized and have enhanced operation characteristics with an improved structure of the FEM. Background Art

[2] A front end module (FEM) is used in a mobile phone and a mobile communication device. The FEM is one module united a power amplifier for amplifying a transmission signal power with a duplexer for separating a transmission/reception frequency band. Recently, the FEM is configured with one module having not only the power amplifier and the duplexer but also a power ditector. Additionally, the power ditector is a component for a transmission output terminal.

[3] A related art structure of the FEM includes a single substrate with a multilayer structure, a bare-chip for power amplification, a duplexer, and a passive element. The bare-chip for power amplification is disposed on a top layer of the substrate and electrically connected to the substrate by wire. The duplexer is disposed on the top layer of the substrate, connected to the substrate electrically, and packaged first. The passive element (e.g. an inductor, a capacitor, etc.) is disposed on the top layer of the substrate.

[4] An operation of each component will now be described in more detail. The bare- chip for power amplification generates a high heat and amplifies power of a transmission signal in the mobile communication device. The duplexer separates a transmission signal from a reception signal in the mobile communication device. Moreover, the passive element is provided to optimize signal matching and performance.

[5] However, since the related art FEM has the bare-chip for power amplification, the duplexer, and the passive element all together mounted on the single substrate in a top of the multilayer substrate, there is a disadvantage that an overall size of the FEM, especially an area of the substrate increases. As the size of the substrate increases, there is a problem that the size of the device (e.g. a mobile communication device with the FEM) also increases. Furthermore, since passive elements in plurality are exposed and mounted on the top of the substrate, the size of the substrate significantly increases.

[6] Moreover, since the bare-chip for power amplification and the duplexer are adjacent to each other on the single substrate, a high heat generated from the bare-chip for power amplification is radiated to the duplexer. Consequently, there is a problem that the performance of the duplexer decreases and furthermore, the entire performance of the FEM decreases. With the same reason, high frequencies from the bare-chip for power amplification or the duplexer can affect each component. Consequently, the operation reliability of the each component can be affected. Disclosure of Invention Technical Problem

[7] Accordingly, the present invention is directed to an FEM that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[8] An object of the present invention is to provide an FEM with stable operation of each component and improved operation reliability, the FEM is provided to prevent performance degradation by not affecting an operation of the duplexer with heat in the bare-chip for power amplification.

[9] Another object of the present invention is to provide an FEM with a minimized mounting space for being mounted inside a mobile communication device without components interfering with each other. Technical Solution

[10] To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided an FEM including a first substrate including a plurality of sheets stacked therein, a second substrate including a plurality of sheets stacked therein and sequentially disposed with respect to the first substrate, a first chip mounted on an inner space of the first substrate, and a second chip mounted on an inner space of the second substrate.

[11] According to another aspect of the present invention, there is provided an FEM including a first substrate including a plurality of sheets stacked therein by a LTCC (low temperature co-fired ceramic) process, a plurality of passive elements and a first chip mounted inside the first substrate, a second substrate including a plurality of sheets stacked therein by the LTCC process and an recessed space with heat-radiating holes, and connected to the first substrate electrically by attaching the second substrate to a bottom of the first substrate, a second chip disposed around the heat-radiating holes of the second substrate, and generating more heat than the first chip, and a lid attached to a top of the first substrate.

[12] According to a further another aspect of the present invention, there is provided an

FEM including a first substrate including a plurality of sheets stacked therein by a LTCC process, a second substrate including a plurality of sheets stacked therein by the LTCC process and attached to the first substrate, heat-radiating holes provided on opening of the second substrate, a first chip mounted on the first substrate, and a second chip mounted on the second substrate and generating heat.

Advantageous Effects

[13] Since a mounting space of an FEM is minimized according to the present invention, there is an advantage that a mounting space required inside a mobile communication device is reduced. [14] Additionally, since heat generated from a bare-chip for power amplification inside the FEM is radiated to the outside without affecting a duplexer, there is an advantage that operation reliability of the FEM improves. [15] Moreover, since a passive element can be provided to a substrate inside a multilayer substrate with a predetermined structure pattern, the number of the passive elements mounted to the substrate can be reduced. Consequently, the size of the FEM can be minimized significantly.

Brief Description of the Drawings [16] FIG. 1 is an exploded perspective view of an FEM according to an embodiment of the present invention; and [17] FIG. 2 is a sectional view an FEM according to an embodiment of the present invention.

Best Mode for Carrying Out the Invention [18] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to accompanying drawings. [19] FIG. 1 is an exploded perspective view of an FEM according to an embodiment of the present invention. [20] Referring to FIG. 1, the FEM 100 includes a first substrate 110 with a multilayer manufactured by a low temperature co-fired ceramic (LTCC) process, a second substrate 120 with a multilayer manufactured by same LTCC process, a first bare-chip

130 for a duplexer and a passive element 140 provided to the first substrate 110, a second bare-chip 150 for power amplification provided to the second substrate 120, and a lid 160 provided to a top of the first substrate 110. It is desirable that the substrate is a ceramic substrate. [21] In the LTCC process, a metal with a predetermined circuit is coated on a green sheet (a ceramic tape), and a metal substrate and a ceramic substrate are manufactured at the same time by a firing process in a low temperature after stacking green sheets. [22] Then, a plurality of via-holes is formed on a sheet, and a conductive metal is printed on the via-holes.

[23] Description of the each component will now be described in more detail.

[24] The first substrate 110 has a plurality of stacked sheets 110a and 110b. A circuit

113 is printed on the each sheet 110a and 110b. Then, space 115 is formed on the sheet 110a which is disposed on a top of the first substrate 110. A first via-hole 117 is formed on the first sheet 110a to electrically connect the plurality of sheets 110a and 110b to each other. If there are additional sheets between the sheets 110a and 110b, a via-hole with the same purpose can be provided.

[25] Additionally, the sheet 110b is disposed on a bottom of the first substrate 110. The sheet 110b includes a first bare-chip 130 for a duplexer for separating a transmission/ reception frequency band, and a passive element 140 (e.g. an inductor, a capacitor, etc.) for optimizing matching and performance of the first bare-chip 130. Then, the first bare-chip 130 is electrically connected to the first substrate by wire 131.

[26] Additionally, second via-holes 119 are formed on the sheet 110b to attach the first substrate 110 to the second substrate 120 to each other and to connect them electrically at the same time. A conductive metal is printed inside and around the first via-hole 117 and the second via-holes 119, and also epoxy is filled inside the second via-holes 119. The conductive metal is used to allow current to flow between the sheets. The epoxy is used for attachment between the first substrate 110 and the second substrate 120, and to connect between the substrates 110 and 120 electrically by spraying conductive silver (Ag).

[27] Additionally, the space 115 of the sheet 110a is made to have a size into which the first bare-chip 130 and the passive element 140 can be fit. If there are additional sheets between the sheets 110a and 110b as a middle layer, it is desirable that a same feature of the space 115 is provided in the additional sheets such that the first base chip 130 and the passive element 140 can fit into the space.

[28] Additionally, the lid 160 is provided on the top of the first substrate 110 to protect a plurality of inside components such as the first bare-chip 130, etc.

[29] The second substrate 120 has a plurality of stacked sheets 120a, 120b and 120c. A circuit 121 is printed on the each sheet 120a, 120b and 120c. Moreover, a top of the second substrate 120 is attached to the bottom of the first substrate 110. Fourth via- holes 127 are formed on a position aligned with the second via-holes 119 to attach the first substrate 110 to the second substrate 120. Epoxy is filled inside the fourth via- holes 127. As described before, the epoxy is used to connect electrically between substrates 110 and 120 through the via-holes 127 and 129 by spraying silver. Attachment between the substrates 110 and 120 is achieved around the second via- holes 119 and the fourth via-holes 127 by the epoxy.

[30] Space 123 is formed on an about center of the sheet 120a, which is disposed on a top of the second substrate 120 and the sheet 120b, which is disposed on a middle of the second substrate 120. Furthermore, the space 123 of the sheet 120a is larger than that of the sheet 120b. The second bare-chip 150 for power amplification is disposed inside the space 123 of the sheet 120b. [31] Additionally, the sheets 120a, 120b and 120c are adjacent vertically. Third via- holes 125 are formed on sheets 120a, 120b and 120c, respectively, to connect them electrically to each other. Thus, the each sheet 120a, 120b and 120c is electrically connected by the third via-holes 125. The fourth via-holes 127 are formed on the sheet 120a corresponding to the second via-holes 119. A conductive metal is printed inside and around the third via-hole 125 and the fourth via-holes 127, and epoxy is filled inside the fourth via-holes 127. As described before, the first substrate 110 and the second substrate 120 are attached mutually and connected electrically by the second via-holes 119 and the fourth via-holes 127.

[32] Additionally, a heat-radiating hole 129 is formed on an about center of the sheet

120c. The bare-chip 150 for power amplification is mounted on the bottom sheet 120c with the heat-radiating hole 129 and is connected to the second substrate 120 electrically by a wire 151. Thus, since heat generated from the second bare-chip 150 is radiated to the outside through the heat-radiating hole 129, the heat is not radiated to the top and thus the first bare-chip 130 is not affected by the heat.

[33] Additionally, since the first substrate 110 with the first bare-chip 130 and the second substrate 120 with the second bare-chip 150 are divided into a different section, respectively, the heat from the second bare-chip 150 is not radiated to the first bare- chip 130 furthermore. As described before, the first bare-chip 130 is a component that requires thermal stability as a duplexer. Since the first bare chip 130 and the second bare chip 150 are mounted on a different substrate, respectively, the possibility of high frequencies from each component affecting the other components is reduced, and thus the operation reliability of the each component improves.

[34] Additionally, the circuit 121 on the second substrate 120 can play a role as an inductance or a capacitance. Here, the circuit 121 plays a role as a passive element. It is desirable to be limited to a relatively small capacity value since the circuit 121 is printed inside the second substrate 120. Furthermore, when a passive element with high capacity is needed, it is desirable that an additional component is provided on the first substrate 110. Since the relatively small-sized first bare-chip 130 for a duplexer is mounted on the first substrate 110, there is a sufficient space for the additional components. Additionally, it is desirable that the thickness of the FEM 100 reduces and the entire size of the FEM reduces by providing the passive elements to either the first substrate 110 or the second substrate 120.

[35] FIG. 2 is a sectional view an FEM according to an embodiment of the present invention.

[36] Referring to FIG. 2, the first bare-chip 130 and the second bare-chip 150 are mounted on a bottom of an inner space of the first substrate 110 and a bottom of an inner space of the second substrate 120, respectively. The first substrate 110 is stacked over the second substrate 120. Thus, the entire size of the FEM 100, especially area can be reduced. Once the FEM 100 becomes smaller, the size of a mobile communication device with the FEM can be smaller as a result.

[37] Additionally, since the first bare-chip 130 for a duplexer and the second bare-chip

150 for power amplification are disposed on the substrates 110 and 120, respectively, there is an advantage that the influence of high heat and high frequencies can be suppressed between the bare-chips 130 and 150.

[38] Additionally, a passive element with low capacity is provided on the second substrate 120 in a circuit form and an additional passive substrate 140 with high capacity is mounted on the first substrate 110. Thus, there is an advantage that the entire size of the FEM 100, especially thickness reduces.

[39] Additionally, since the electrical connections between the substrates or sheets are reliable using the via-holes, operation reliability of the FEM improves much more.

[40] Additionally, since each substrate is manufactured by the LTCC process, the size of the FEM is small initially.

[41] On the other hand, nonconductive epoxy 155 is used to protect the wire 151 to be firmly connected to the second substrate 120. Also, the second bare-chip 150 is supported by the nonconductive epoxy 155. Mode for the Invention

[42] A following embodiment within the spirit and scope of the invention will now be described.

[43] First, a component for power amplification with high heat is mounted on a second substrate, and a component for a duplexer that requires excellent operation reliability is mounted on a first substrate. With a similar logic, other components (e.g. a power detector, etc.) can be disposed on a specific substrate according to generation of heat and reliability requirement.

[44] Second, epoxy is inserted around via-holes on a pair of substrates. Then, the pair of substrates is attached to each other by the epoxy. Using the same method with the epoxy, the pair of substrates can be attached at not only a perimeter of the via-holes but also at perimeter of the substrate. However, if the via-holes are connected electrically and attached to each other at the same time, there is an advantage that mechanical connection and electrical connection between the substrates can be achieved simultaneously.

[45] Third, a second substrate with heating component is disposed on a bottom, and a first substrate with component that requires reliability is disposed on a top. If heat- radiating hole can be provided to the first substrate, it is possible that the heating component can be disposed on the first substrates. Industrial Applicability

[46] There is an advantage that since a first bare-chip for a duplexer and a second bare- chip for power amplification are mounted on a bottom of an inner space of a first substrate 110 and a bottom of an inner space of a second substrate, respectively, the FEM can be miniaturized.

[47] Additionally, since a first bare-chip and a second bare-chip are separated and installed, and heat generated from the second bare-chip is radiated through a heat- radiating hole, the first bare-chip is not affected by the heat from the second bare-chip. Additionally, since the first bare-chip and the second bare-chip are not affected to each other by high frequencies, there is an advantage that the operation reliability of each chip improves.

[48]

Claims

[I] An FEM (front end module) comprising: a first substrate including a plurality of sheets stacked therein; a second substrate including a plurality of sheets stacked therein, the second substrate sequentially disposed with respect to the first substrate; a first chip mounted on an inner space of the first substrate; and a second chip mounted on an inner space of the second substrate.

[2] The FEM according to claim 1 , wherein the first chip is a duplexer or a bare- chip.

[3] The FEM according to claim 1, wherein the second chip is a chip for power amplification or a heating chip.

[4] The FEM according to claim 1 , wherein the first substrate is disposed above the second substrate and a lid is disposed above the first substrate.

[5] The FEM according to claim 1, wherein heat-radiating holes are formed on the sheet of the second substrate.

[6] The FEM according to claim 1, wherein a passive element as an additional component is disposed on the one substrate, and a passive element as a circuit structure is disposed on the another substrate.

[7] The FEM according to claim 1, wherein the at least one substrate includes a passive element as a circuit on the sheet or a passive element as an additional component.

[8] The FEM according to claim 1, wherein the substrates are electrically connected to the each other by via-holes.

[9] The FEM according to claim 1, wherein the second chip is supported by non- conductive epoxy.

[10] The FEM according to claim 1, wherein the substrates are ceramic substrates.

[I I] The FEM according to claim 1, wherein the substrates are attached to each other by via-holes.

[12] An FEM comprising : a first substrate including a plurality of sheets stacked therein by a LTCC (low temperature co-fired ceramic) process; a plurality of passive elements and a first chip mounted inside the first substrate; a second substrate including a plurality of sheets stacked therein by the LTCC process and an recessed space with heat-radiating holes, and connected to the first substrate electrically by attaching the second substrate to a bottom of the first substrate; a second chip disposed around the heat-radiating holes of the second substrate, and generating more heat than the first chip; and a lid attached to a top of the first substrate. [13] The FEM according to claim 12, further comprising: a first via-hole connecting a plurality of sheets in the first substrate electrically to the each other; and second via-holes disposed on the lowermost sheet in the first substrate to attach the first substrate to the second substrate and to connect to the each other electrically at the same time. [14] The FEM according to claim 12, wherein a mounting space of the second chip is provided by forming an opening in a center of the uppermost sheet and the middle sheet in the second substrate. [15] The FEM according to claim 12, further comprising: a third via-hole connecting the plurality of sheets in the second substrate electrically to the each other; and fourth via-holes disposed on the uppermost sheet in the second substrate to attach the second substrate to the first substrate and to connect electrically to the each other at the same time. [16] The FEM according to claim 12, wherein the first substrate and the second substrate are connected electrically and attached to the each other at the same time by corresponding via-holes. [17] The FEM according to claim 12, wherein the chip is disposed on an inner space of the substrate. [18] The FEM according to claim 12, wherein the chip is mounted on the first sheet in the substrate and space for accommodating the chip is provided on a top of the first sheet. [19] An FEM comprising: a first substrate including a plurality of sheets stacked therein by a LTCC process; a second substrate including a plurality of sheets stacked therein by the LTCC process and attached to the first substrate; heat-radiating holes provided on opening of the second substrate; a first chip mounted on the first substrate; and a second chip mounted on the second substrate and generating heat. [20] The FEM according to claim 19, wherein the second chip is a bare-chip for power amplification and the first chip is a chip for a duplexer.