WO2006069420A1 - Procede et systeme de communication de donnees - Google Patents

Procede et systeme de communication de donnees Download PDF

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Publication number
WO2006069420A1
WO2006069420A1 PCT/AU2005/001978 AU2005001978W WO2006069420A1 WO 2006069420 A1 WO2006069420 A1 WO 2006069420A1 AU 2005001978 W AU2005001978 W AU 2005001978W WO 2006069420 A1 WO2006069420 A1 WO 2006069420A1
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WO
WIPO (PCT)
Prior art keywords
time
pair
signal
cycle
symbol
Prior art date
Application number
PCT/AU2005/001978
Other languages
English (en)
Inventor
Ewan Parsons
Peter Foord
Original Assignee
Phase 6 Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from AU2004907366A external-priority patent/AU2004907366A0/en
Application filed by Phase 6 Pty Ltd filed Critical Phase 6 Pty Ltd
Priority to AU2005321752A priority Critical patent/AU2005321752A1/en
Publication of WO2006069420A1 publication Critical patent/WO2006069420A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404—Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/542—Methods of transmitting or receiving signals via power distribution lines using zero crossing information

Definitions

  • the present invention relates to a system and method for data communication over an alternating current power distribution network.
  • the present invention may be used to enable demand side management of electrical loads connected to the power distribution network.
  • the present invention is not intended to be so limited and thus may also be applicable to other applications.
  • the present invention may be used in automatic meter reading.
  • ripple control technique involves modulating a power signal to superimpose a small-bandwidth audio signal onto the power signal. This type of ripple control often uses different audio frequencies to communicate different bits of a code.
  • this technique provides a slow data rate relative to the frequency of the power signal.
  • BPL broadband over power lines
  • the present invention provides a system for, and method of, sending and/or receiving data over an alternating current power distribution network carrying a power signal.
  • the present invention provides a method of sending data over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the method including: defining one or more time-frames in each cycle of a pair of cycles of the power signal, each time-frame of the first cycle of the pair of cycles having a corresponding time-frame in the second cycle to provide a pair of corresponding time-frames; and applying a modulation signal to at least one time-frame of each pair of corresponding time-frames to provide, over a continuum of time values of each time- frame of a pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.
  • modulation signals are applied to each time-frame of corresponding time-frames to provide, relative to a reference common to each of those time-frames, a phase difference that permits a receiver to reconstruct the symbol sequence by performing a difference calculation between power signal level values associated with corresponding time- frames of the first and second cycle of a cycle pair.
  • the fundamental frequency ⁇ components, and the harmonics thereof, of the power signal may be removed.
  • time-frame are to be understood to be references to a discrete time segment, bounded by an upper and a lower time value, of a cycle of a power signal. Each cycle may include one or more time- frames.
  • each time-frame of a first cycle of the power signal as forming, with a time-frame in a second cycle of a pair of cycles of the power signal, a pair of "corresponding" time-frames.
  • references to "corresponding" time-frames are to be understood to be time-frames of the first and second cycle that have substantially the same time-wise relationship with each cycle.
  • each time-frame of a pair of corresponding time-frames will be bounded by substantially the same upper and lower time values of a respective cycle of a power signal relative to a reference common to each cycle.
  • the reference will be a positive "zero-crossing" of each cycle of the power signal.
  • the amplitude and frequency of the power signal will vary according to the type and arrangement of the alternating current power distribution network.
  • the power signal may be a high voltage power signal from the high tension side of a power distribution transformer.
  • the power signal is between 11000 Volts and 33000 Volts
  • the power signal may be a mains voltage power signal obtained from the output of a mains power distribution transformer
  • the power signal is a 240V AC 50Hz power signal
  • hi another embodiment, the power signal is a 110V AC 60Hz power signal.
  • the phase-difference is about 180 degrees.
  • a 180° phase difference may be a 180° phase shift so that modulation signals of paired modulation signals are offset with respect to one another relative to the common reference.
  • An embodiment that provides a pair of modulation signals having a 180° phase-offset is expected to provide additional benefits, hi particular, it is expected to allow the use of a simple transmitter arrangement for applying the modulation signals.
  • the 180° phase difference may be a phase inversion so the paired modulation signals are inverted with respect to one another relative to the common reference.
  • each modulation signal is a periodic signal having a substantially constant frequency in the range of between four to eighty times greater than the frequency of the power signal.
  • the frequency of the modulation signal may be in the range of 400Hz to 4000Hz.
  • the frequency of the modulation signal is 1800Hz. It is preferred that each modulation signal is a single cycle of a periodic signal. However, each modulation signals may include multiple cycles of a periodic signal.
  • the modulation signal of the first cycle has a different time-wise location with respect to a respective time-frame.
  • the modulation signals of a pair of modulation signals coincide time- wise, at least over an extent, relative to a reference common to the corresponding time-frames.
  • the extent over which the modulation signals coincide is one half-cycle of the paired modulation signals.
  • the relative magnitude relationship between the modulation signals and the relative location of the time- wise coincident half-cycles with respect to the common reference varies according to the symbol type.
  • each cycle pair includes a pair of corresponding time-frames for each symbol in the sequence.
  • the pair of cycles are consecutive cycles of the power signal. However, it is not essential that the pair of cycles be consecutive cycles. Indeed, in an embodiment, the pair of cycles are separated by one or more other cycles of the power signal.
  • each time-frame may be divided into plural time-slots.
  • the phase-difference may be provided by locating each modulation signal of a pair of modulation signals representing different symbol-types in different ones of a pair of time-slots, hi one embodiment, each time- slot has a width that corresponds to the duration of a half-cycle of the modulation signal.
  • a predefined symbol-set may have any suitable number of symbols.
  • a symbol-set that includes n symbols will be referred to as a base- « symbol-set.
  • the symbol-set includes two symbols (that is, a "base-2" symbol-set).
  • another embodiment of the invention includes a symbol-set that includes four symbols (that is, a "base-4" symbol-set).
  • a single byte of data is communicated by a pair of consecutive cycles of the power signal, hi such an embodiment, each power signal cycle includes eight time-frames, and each time-frame contains one data-bit in the form of a single cycle of a modulating signal.
  • other embodiments of the invention may transmit more, or less data, again depending on the relationship of the frequency of the modulating signal to the frequency power signal.
  • Each modulation signal may occupy a complete time-frame of the power signal or, alternatively, it may occupy a portion of a time-frame.
  • the relationship between a modulation signal and a time-frame of the power signal, at least in terms of the location of the modulation signal within a time-frame, and the extent to which it occupies that frame varies according to the symbol that is being represented by the modulating signal.
  • Such a modulation scheme is expected to provide further improvements in data-rate since additional symbols may be represented as modulation signals that are time-shifted within a time-frame.
  • the present invention also provides a transmitter for sending data over a power distribution network carrying an alternating current periodic power signal, the data including a sequence of symbols from a predefined symbol-set, the transmitter including: timing means for defining one or more time-frames in each cycle of a pair of cycles of the power signal, each time-frame of the first cycle of the pair of cycles having a corresponding time- frame in the second cycle so as to provide a pair of corresponding time-frames; and signal injector means for applying a modulation signal to at least one time- frame of each pair of corresponding time- frames to provide, over a continuum of time values of each time-frame of a pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.
  • the present invention also provides a method of receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the method including: detecting a pair of cycles of the power signal including a modulation signal in at least one time frame of corresponding time-frames of a first cycle and a second cycle of the pair of cycles; sensing, for each time-frame of a pair of corresponding time-frames of the first cycle and the second cycle, a set of signal level values; processing the sensed level values for corresponding time-frames of the pair of cycles to generate a difference signal; and decoding the symbol type associated with the difference signal.
  • either the first cycle or the second cycle of the pair of cycles includes one or more modulation signals and the other signal, that is, either the second cycle or the first cycle, is an "average" single cycle of the power signal that has been obtained by averaging multiple cycles of the power signal.
  • the detected pair of cycles of the power signal includes a cycle that has been obtained by way of an averaging process. Such an embodiment is expected to permit improved data- rates in that adjacent cycles of the power signal may contain modulation signals for different symbols of the symbol sequence.
  • the present invention also provides a receiver for receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the receiver including: a detector detecting a pair of cycles of the power signal including a modulation signal in at least one time frame of corresponding time-frames of a first cycle and a second cycle of the pair of cycles; and a signal processor sensing, for each time-frame of a pair of corresponding time- frames of the first cycle and the second cycle, a set of signal level values, processing the sensed level values for corresponding time-frames of the pair of cycles to generate a difference signal and decoding the symbol type associated with the difference signal.
  • the present invention also provides a transmitter for sending data over a power distribution network carrying an alternating current periodic power signal, the data including a sequence of symbols from a predefined symbol-set, the transmitter including: timing means for defining one or more time-frames in each cycle of a pair of cycles of the power signal so that each time-frame of a first cycle of the pair of cycles has a corresponding time-frame in a second cycle of the cycle pair; and a signal injector means for applying, in a pair of corresponding time-frames, to the first cycle and the second cycle, a modulation signal to form a pair of modulation signals representing a symbol-type of a symbol in the sequence; wherein relative to a reference common to each pair of corresponding time frames, paired modulation signals of those time-frames have a phase-difference so that the modulation signals of a pair of modulation signals coincide time-wise over at least an extent of each modulation signal of that pair.
  • the present invention also provides a receiver for receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined symbol-set, the receiver including: a detector detecting a pair of cycles of the power signal, each cycle of the pair including modulation signals located in corresponding time-frames to provide a pair of modulation signals which, relative to a reference common to each of the corresponding time-frames, have a phase-difference so that each modulation signal pair coincide time- wise over at least an extent; and a processor processing each detected pair of cycles of the power signal to provide a difference value for each modulation signal pair and using each difference value to identify the symbol-type represented by each pair of modulation signals.
  • a particular advantage of the present invention is that it provides a relatively high-speed and robust method of communicating data over an alternating current power distribution network.
  • Fig.l is a system block diagram of a system according to an embodiment of the present invention for sending data over a power distribution network carrying an alternating current power signal;
  • Fig.2 is a simplified block diagram for a transmitter suitable for use with the embodiment illustrated in Fig.1 ;
  • Fig.2A is a signal diagram showing consecutive cycles of an alternating current power signal
  • Fig. 2B depicts a simplified flow diagram of an embodiment of a method for transmitting data according to an embodiment of the invention
  • Fig.3 is a block diagram of a timing controller suitable for incorporating in modulator of Fig.2;
  • Fig.4 is a signal timing diagram illustrating timing relationships between a single cycle of a power signal, an IRQ and an IRQ counter;
  • Fig.4A shows a time-slot arrangement of a time-frame of the power signal shown in Fig.5;
  • Fig.5 is a signal diagram illustrating the occupation of different time-slots of a time-frame of a power signal for each symbol of a base-2 symbol-set;
  • Fig.5A is a signal diagram illustrating an example of a different occupation of time-slots of a time-frame of a power signal according for each symbol of a base-2 symbol-set;
  • Fig.6 is a simplified schematic diagram of a signal injector suitable for incorporating in the transmitter of Fig.2;
  • Fig.6 A is a signal diagram illustrating the relationship between a control signal and the signal current (I m ) of the signal injector
  • Fig.6B is a signal diagram illustrating the relationship between a power signal cycle, capacitor voltage and signal current (I m );
  • Fig. ⁇ C is a diagram showing a typical signal energy of a modulation signal
  • Fig.7 is a signal diagram showing an example of a pair of cycles of the power signal containing modulation signals;
  • Fig.7A is an example of a pair of modulation signals for a "symbol 0";
  • Fig.7B is an example of a pair of modulation signals for a "symbol 1"
  • Fig.8 is a set of signal diagrams illustrating examples of the effect of impedance variations on the generation of a signal voltage
  • Fig.9 is a simplified block diagram of an embodiment of a receiver suitable for use with a system in accordance with an embodiment of the present invention
  • Fig.9 A is a detailed block diagram of a receiver suitable for use with a system in accordance with an embodiment of the present invention
  • Fig.10 is a simplified signal diagram showing an example derivation of a difference signal
  • Fig.1OA is a flow diagram of a receiver process
  • Fig.1OB is a signal diagram showing an example of sampling a modulation signal
  • Fig.lOC is a timing diagram of a process for demodulating a "1" symbol of a base-2 symbol set
  • Fig.1OD is a timing diagram of a process for demodulating a "0" symbol of a base-2 symbol set
  • Fig.11 shows an example of a demodulation cycle
  • Fig.12 is a timing diagram of a process for demodulating a "1" symbol of a base-2 symbol set
  • Fig.l2A is a timing diagram of a process for demodulating a "0" symbol of a base-2 symbol set
  • Fig.13 is a block diagram of a system according to another embodiment of the present invention.
  • Fig.14 is a schematic diagram of a transceiver according to an embodiment of the present invention.
  • Fig.15. is a table including example instruction codes for an embodiment of the present invention.
  • the present invention will be described in terms of an embodiment that supports the sending of data over an alternating current power distribution network carrying a 240 V AC 50Hz power signal.
  • the present invention is not to be limited to such a power distribution network.
  • the described embodiment of the present invention communicates one-byte (that is, 8-bits) of data in a pair of consecutive cycles of the power signal.
  • a transmission system in accordance with the present invention that uses a base-2 symbol set (that is, a binary system) and a 50Hz power signal frequency, will provide an overall data rate of 200bps.
  • a base-4 system may transmit two-bytes of data in a pair of consecutive cycles and thus provides an overall data rate of 400bps.
  • each cycle of a pair of consecutive cycles includes eight modulation signals, one for each bit.
  • each modulation signal is a single cycle of an 1800Hz sinusoidal-like signal.
  • Fig.l depicts a system 100 for sending data over a power distribution network 102 carrying a 240 V AC 50Hz alternating current power signal.
  • the system 100 includes a power substation 104, a transmitter 105, a distribution transformer 106, and receivers 108.
  • the substation 104 includes an alternating current (AC) power generator that provides a high voltage power signal, typically 11000 VAC 50Hz.
  • the high voltage power signal is converted by the distribution transformer 106 into a three phase 415 VAC 50Hz output.
  • Each single phase of the three phase output provides a low voltage power signal 110, typically 240V AC 50Hz.
  • Fig.l depicts a single phase circuit 112 for clarity.
  • the transmitter 105 and the receivers 108 are located in the single phase circuit 112 side of the network 102.
  • the transmitter 105 applies modulation signals to predefined time-frames of a pair of cycles of the power signal 110 so to enable data to be sent over the power distribution network 102.
  • the data is communicated as a message 114 to one or more receivers 108.
  • the message 114 may originate from, for example, a service provider responsible for managing the power distribution network or it may originate from another entity.
  • the transmitter 105 is shown on the load side of the distribution transformer 106, it could equally be located on the power generation side.
  • the transmitter 105 accepts the message 114 as a data stream consisting of a sequence of symbols from a predefined symbol set and applies modulation signals to a pair of cycles of the alternating current power signal 110 to communicate the message to one or more selected receiver(s) 108.
  • the selected receiver(s) 108 may be a specific one of the receivers 108, or a selected set of the receivers 108, or it may be all of the receivers 108.
  • the receivers 108 detect a pair of cycles of the alternating current power signal 110 including modulation signals which have been applied by the transmitter 105 and demodulate the power signal 110 to reconstruct the message 114.
  • Fig.2 depicts an embodiment of a transmitter 105 suitable for use with an embodiment of the present invention.
  • the transmitter 105 includes a timing means (shown as timing controller 200) and a signal injector 202.
  • the timing controller 200 receives a message 114, consisting of a sequence of symbols from a predefined symbol-set for transmission to one or more of the receivers 108, and defines one or more time- frames in each cycle of a pair of cycles of the power signal so that each time-frame of a first cycle of the pair of cycles has a corresponding time-frame in a second cycle.
  • the timing controller 200 activates the signal injector 202 to apply a modulation signal, in at least one of the time- frames of a pair of corresponding time-frames of the first cycle and the second cycle.
  • modulation signals are applied to each time- frame of a pair of corresponding time-frames to thereby form a pair of modulation signals representing a symbol-type of a symbol in the sequence.
  • the modulation signals of a pair of corresponding time-frames are applied so as to provide, over a continuum of time values of each time- frame of a pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.
  • each time-frame of a pair of corresponding time-frames include a modulation signal. Indeed, in an alternative embodiment, only one of the time-frames of a pair of corresponding time-frames includes a modulation signal.
  • Fig.2A depicts a signal diagram of a pair 206 of consecutive cycles of the power signal 110.
  • the applying of the modulation signals to a pair of cycles 206 of the power signal 110 involves applying modulation signals to a first cycle 204 (shown as Cycle n) of the pair of cycles 206 of the power signal 110 to provide, in different time-frames of that cycle 204, a modulation signal for each symbol of the symbol sequence of the message.
  • a modulation signal is also applied to a second cycle 208 (shown as Cycle n+1) of the pair of cycles 206 to provide, in the corresponding time-frames of the second cycle 208, an associated modulation signal to form, for each symbol, a pair of modulation signals for each symbol of the sequence.
  • first cycle 204 and the second cycle 208 are shown as consecutive cycles. However, it is to be appreciated that the first cycle 204 and the second cycle 208 need not be consecutive. Indeed, in another embodiment the first cycle 204 and the second cycle 208 could be separated by one or more other cycles of the power signal.
  • paired modulation signals of those time-frames have a phase-difference so that, over a continuum of time values of each time-frame of a pair of corresponding time- frames, a signal difference is provided that is indicative of a symbol-type of the symbol sequence.
  • paired modulation signals coincide time-wise over at least an extent of each modulation signal of that pair. Whilst it is not essential that paired modulation signals coincide time-wise, it is preferred that the modulation signals coincide time-wise over at least an extent of each modulation signal of a pair of corresponding time-frames so as to reduce the overall width of the time-frames.
  • a difference processing technique applied to pairs of cycles containing modulation signals.
  • the difference processing cancels the fundamental frequency and harmonic component of the power signals, but provides a difference signal that is decodable to identify the symbol-type represented by each pair of modulation signals.
  • the modulation scheme employed by the invention will be described in more detail later.
  • a simplified flow diagram of an embodiment of the method for transmitting data, as described above, is depicted in Fig.2B.
  • Fig.3 depicts an embodiment of a timing controller 200 suitable for incorporating in an embodiment of a transmitter in accordance with the present invention.
  • the timing controller 200 includes a positive "zero-crossing" detector 300, a phase locked loop (PLL) 302, an input register 304, a controller 306 and a clock 308.
  • the zero-crossing detector 300, the PLL 302, the input register 304, and the clock 308 may be implemented in software, hardware or firmware, hi one embodiment, the zero-crossing detector 300, the PLL 302, the input register 304, and the clock 308 are implemented using a MSP430 processor including program memory containing executable instructions, in the form of a software program, for implementing the zero- crossing detector 300, the PLL 302, the input register 304, and the clock 308.
  • the zero-crossing detector 300 senses the power signal 110 and generates an output signal 310 that is synchronised with positive zero- crossing events of the power signal 110.
  • a zero- crossing event is detected every 2OmS.
  • the zero-crossing detector 300 is enabled by the controller 306 about 300 ⁇ s before an estimated location of a positive zero-crossing event to reduce the likelihood of false zero crossings from voltage disturbances on the power signal 110.
  • a "positive zero-crossing event" occurs when magnitude of the power signal 110 varies from a negative value to a positive value.
  • the PLL 302 is configured to generate an output signal 314 that is synchronised with the detection of zero crossing events.
  • the PLL 302 provides an output signal 314 having the same frequency as, and a fixed phase relationship with the power signal 110. That is to say, the output signal 314 has a precise timing relationship with the power signal 110 so that output signal 314 of the PLL 302 is phase aligned with the power signal 110.
  • the output signal 314 is a OV to 3.3V 50Hz signal that is phased aligned with the power signal 110.
  • the controller 306 senses the PLL output signal 314 and monitors that signal to generate a synchronisation signal 314 which is asserted on positive zero-crossing events of the PLL output signal 314.
  • the synchronisation signal 314 is asserted every 2OmS.
  • an internal counter of the controller (not shown), triggered by the clock 308, is reset.
  • the internal counter provides a count sequence having a duration that substantially corresponds with, or is less than, the period of a single cycle of the power signal 110.
  • the duration of the count sequence is about 2OmS.
  • each count 400 (shown as time-frame counts 1 to 8) of the count sequence defines the beginning of, and identifies, a respective time-frame 402 of a single cycle 204, 208 (ref. Fig. 2A) of a pair 206 of cycles of the power signal 110.
  • the number of time-frames 402 of each cycle 204, 208 (ref. Fig. 2A) of a pair 206 of cycles of the power signal 110 corresponds with the number of symbols that are able to be represented in a pair of consecutive cycles 204, 208 of the power signal 110 using a modulation signal pair.
  • each cycle 204, 208 includes eight time-frames 402.
  • each count of the internal counter corresponds with a respective time-frame
  • each n th count of N counts of the internal counter also corresponds with the n l symbol in a symbol sequence having a sequence length of N symbols.
  • each cycle 204, 208 of the pair of cycles 206 will include eight time- frames 402, that is, one for each symbol that is represented in the pair of cycles 206 as a pair of modulation signals.
  • each modulation signal 508 of a pair of modulation signals representing a symbol-type will be located within corresponding time-frames 402-A, 402-B of each cycle 204, 208 of a pair of cycles 204, 208 of the power signal 110.
  • each count of the internal counter also triggers an interrupt request (IRQ) 404 on the controller 306.
  • IRQ interrupt request
  • each IRQ 404 calls an associated interrupt service routine (ISR) that provides a further count sequence, triggered by an IRQ counter clock 406, to provide a count for each time-frame 402.
  • ISR interrupt service routine
  • Each count of the ISR counter effectively defines the beginning of a time-slot 408 of a time-frame 402 of each single cycle 204, 208 (ref. Fig. 2A) of the power signal 110.
  • the interval between consecutive counts of the ISR counter clock 406, associated with the same IRQ (and thus the same time-frame) correspond, time-wise, to the time period of one-half cycle of the modulation signal.
  • each time-slot 408 (ref. Fig.4A) has a width that is substantially the same as the duration of a half-cycle of the modulation signal.
  • a single cycle of a modulation signal 508 will substantially completely occupy a pair of sequential time-slots 500, 502, 504, 506.
  • the width of a single time-slot 408 (ref. Fig.4A) for an 1800Hz modulating signal is about 277 ⁇ S.
  • the first- modulation signal 508-1, 508-3 of a pair of modulation signals 508-1, 508-2 and 508-3, 508-4, representing a symbol type (in this case, the modulation signals of time frame 402-A) will occupy a different respective pair of sequential time-slots 408 of a time-frame 402-A of the first cycle 204.
  • the modulation signal 508-1 of the first cycle 204 will have a different time-wise location with respect to a respective time-frame 402-A as compared to modulation signal 508-3 of the first cycle 204 of a modulation signal pair representing a different symbol type.
  • the number of time-slots 408 of a time-frame 402 depends upon the base of the symbol-set. For example, and again as is depicted in Fig.5, for a base-2 symbol set a time-frame 402 will comprise at least three time-slots 408.
  • the number of time-slots has been limited according to the base of the symbol-set, as shown in Fig.5 A, other embodiments of the invention may use a number of time-slots that is independent of the base of the symbol-set.
  • Such an embodiment may be apply, for example, where the modulation signals of corresponding time-frames do not time- wise coincide to any extent relative to a reference common to each time frame of the pair of corresponding time-frames, but instead are spaced apart time-wise relative to the common reference, hi such an embodiment, the modulation signals will still have a phase difference that allows a receiver to generate a difference signal that is decidable to identify the symbol type represented by the pair of modulation signals.
  • the controller 306 runs a main-program loop, comprising a set of program instructions resident in program memory that periodically polls a flag to determine whether the input register 304 contains a new symbol sequence for transmission.
  • the flag is polled on sensing each positive zero- crossing event of the power-signal 110.
  • the controller 306 resets the internal counter and sets a "cycle count" bit to identify the first cycle 204 of the pair of consecutive cycles of the power signal 110 to be modulated with the symbol-sequence. For each count of the internal counter, and thus for each time-frame 408 (ref.
  • the controller 306 reads the bit-pattern, or the bit, of the first symbol of the symbol sequence and identifies the symbol-type represented by 1978
  • controller 306 retrieves a "first-cycle" control code from program memory.
  • the "first-cycle" control code represents a code for generating a serial output, as a control signal 316, to the signal injector 202 synchronous with the IRQ counter clock 406 (ref. Fig.4), to activate the signal injector 202 to apply modulation signals to at least one time-frame of the first cycle 204 of a pair of cycles 206 of the power signal 110.
  • the length of the "first-cycle" control code is set by base of the symbol-set and identifies which pair of sequential times-lots of a time- frame 402 is to be occupied by the modulation signal for a respective symbol.
  • the controller 306 checks a respective bit of the control code (for example, for the first IRQ count, the first bit of the control code is the respective bit) and, if the respective bit of the control code is asserted, a control signal 316 is output to activate the signal injector 202 to apply a half- cycle of the modulation signal to that time slot of a time frame 402 of the first cycle 204 corresponding to the internal counter.
  • the characteristics of the control signal 316 depend upon the arrangement of the signal injector 202.
  • Fig.6 depicts a signal injector 202 arrangement suitable for use with an embodiment of the present invention. Although the present embodiment will be described in relation to the illustrated signal injector 202, it is to be appreciated that other signal injector arrangements may be used.
  • the signal injector 202 shown in Fig.6 includes a series arrangement of an alternistor 600, a capacitor 602 and an inductor 604.
  • the series arrangement of the capacitor 602 and the inductor 604 provides an oscillator circuit that, in use, provides a positive half-cycle current (I m ) 608 in response to a first pulse 612 of a control signal 316 and a negative half-cycle current (I m ) 610 in response to a subsequent pulse 614 of the control signal 316.
  • an alternistor 600 is an alternating current switch which is turned on by a pulse to its gate electrode and turns off when current through it drops to zero.
  • the capacitor 602 and the inductor 604 form a series resonant circuit having a resonant frequency which determines the frequency of the modulating signal.
  • Fig.6 A depicts an example of a control signal 316 for use with the illustrated signal injector 202. Again, it is to be appreciated that the actual characteristics of the control signal 316 will depend on the arrangement of the signal injector 202. In the signal diagram illustrated in Fig.6A, the control signal 316 includes spaced apart 50 ⁇ S pulses.
  • the operation of the signal injector 202 will now be described in more detail.
  • the power signal 110 initially has a positive voltage and the capacitor voltage is negative, from a prior charging cycle.
  • the timing for the prior charging cycle of the capacitor 602 will be described in more detail later.
  • the alternistor 600 When the alternistor 600 is "switched on” by pulse 612, the stored negative charge in the capacitor 602, together with the positive voltage of the power signal (at least during the period that the alternistor arrangement 600 remains switched on), results in the production of a large positive current I m as a result of the capacitor 602 discharging through the inductor 604.
  • the voltage responsible for generating the positive current I m will typically be twice that of the power signal voltage 110.
  • the capacitor 602 After discharge, the capacitor 602 starts recharging as energy returns to the capacitor 602 from the inductor 604. During recharging, the capacitor voltage increases above the voltage of the power signal 110 and, at that point, the signal current I m reduces until it reaches zero and the alternistor arrangement 600 "opens". After the alternistor arrangement 600 has opened, no further signal current I m flows in the series arrangement. However, the capacitor 402 remains charged at a positive voltage. Thus, when the alternistor 600 is switched on by the second pulse 614, the capacitor 602 again discharges through the inductor and a similar discharge pattern occurs. However, for this discharge cycle the signal current I m flows in the opposite direction relative to the previous discharge cycle.
  • the above-described technique permits individual half cycles of signal current I m to be generated under the control of the control signal 316.
  • a typical charging and discharging cycle, and the resultant circuit current I m is shown in Fig. 6B.
  • the prior charging cycle which is the illustrated embodiment is required to start the oscillation the alternistor 600, is provided by activating the signal injector 202 to generate a "start pulse" 616 just before the positive going zero crossing of the power signal 110.
  • the start pulse is located about 2mS prior to the positive zero-crossing. The location of the start pulse 616 results in a prior charging cycle in which the capacitor 602 is charged with a negative voltage.
  • control of the timing of the generation of the start pulse 616 is achieved by the controller 306 synchronising the timing of the generation of the start pulse relative to the positive zero-crossing event of the cycle of the power signal 100 immediately prior to the first cycle of the pair of power signals to which modulation signals are to be applied.
  • the signal injector 202 is also activated to generate "dummy pulses" 618.
  • "dummy pulses" 618 are required to maintain a relative difference between the power signal level and the capacitor voltage during time frames 402 so as to sustain oscillation of signal current I m .
  • the "dummy pulses" are applied at the voltage peaks of the power signal, hi this respect, the dummy pulses are so called because they do not form part of the data. It will be appreciated that other signal injector arrangements may not generated “dummy pulses", but may nevertheless be capable of applying modulation signals to the power signal 110.
  • the applying of modulation signals to the second cycle 208 (ref. Fig.2A) of a pair of cycles 206 (ref. Fig. 2A) of the power signal 110 uses a similar technique to that described above, except that the modulation of the second cycle 208 of the power signal 110 uses different control codes.
  • the control codes associated with the modulation of the second cycle 208 will have a difference in structure so the modulation signal of the second cycle 208 will occupy a different time-slot pair of a time-frame 402 of the second cycle 208 that corresponds with a time-frame of the first-cycle 204.
  • the use of different time-slots pairs provides, between modulation signals for the same symbol-type, a phase difference of 180 degrees with respect to a reference common to corresponding time-frames.
  • the common reference is the beginning of each time-frame 402 of a pair of corresponding time- frames.
  • the beginning of each time- frame 402 has a time-wise location that has been established relative to the "positive zero crossing" of the cycle of the power signal 110 to be modulated.
  • the signal current I m results in a modulation signal being applied to the power signal as a signal voltage, due to the source impedance of the power distribution network.
  • the required signal voltage is quite high.
  • sufficient signal voltage, and thus modulation signal energy can easily be achieved with transmitter peak currents of about five amps, hi this respect, the typical energy of a modulation signal is shown in Fig. ⁇ C.
  • Fig.7 depicts an example of a pair of cycles 204, 208 of the power signal 110 containing modulation signals in corresponding time- frames 402- A, 402-B.
  • each cycle 204, 208 of the pair of cycles 206 includes eight time-frames 402-A, 402-B.
  • Each time-frame 402-A of the first cycle 204 of the pair of cycles 206 has a corresponding time-frame 402-B in the second cycle 208 of the cycle pair 206.
  • each pair of corresponding time-frames 402-A, 402-B includes a modulation signal that has been applied to the first cycle 204 and the second cycle 208 respectively, to form a pair of modulation signals representing a symbol-type of a symbol in the sequence.
  • paired modulation signals of those time- frames 402- A, 402-B have a phase-difference of 180 degrees so that the modulation signals of a pair of modulation signals coincide time-wise over at least an extent of each modulation signal of that pair, hi the present case, the pair of modulation signals representing "symbol 0" coincide time-wise in "time-slot 2". hi addition, the pair of modulation signals representing "symbol 1" also coincide time- wise in "time-slot 2".
  • the source impedance of the distribution network 102 will vary depending on the distance of the receivers 108 from the distribution transformer 106 (ref. Fig.l). For example, for distances close to the distribution transformer 106 the network impedance will be low and almost entirely reactive. On the other hand, at the end of a long network (for example, 4km) the resistive component is more significant but still well within the capability of the transmitter.
  • Fig.8 depicts waveform diagrams illustrating the effect of a variation in the ratio of reactance to resistance.
  • a suitable receiver arrangement is able to demodulate data, modulated onto a pair of consecutive cycles of the power signal 110, irrespective of the phase variation caused by network variations in the ratio of reactance to resistance.
  • Fig.9 depicts a simplified block diagram of a receiver 108 according to an embodiment of the present invention.
  • the receiver 108 includes a cycle-pair detector 900 and a signal processor 902.
  • the cycle-pair detector 900 detects pair of cycles of the power signal that include a modulation signal in at least one time frame of corresponding time-frames of a first cycle and a second cycle of the pair of cycles.
  • the signal processor 902 senses, for each time-frame of a pair of corresponding time-frames of the first cycle and the second cycle, a set of signal level values, and processes the sensed level values for corresponding time- frames of the pair of cycles to generate a difference signal.
  • the signal processor 902 then decodes the symbol type associated with the difference signal.
  • Fig.9A depicts an embodiment of a receiver 108 in more detail.
  • the signal processor 902 includes a zero-crossing detector 904, an analog-to-digital converter (ADC) 906, a phase locked loop (PLL) 908, a controller 910, a clock 912 and a decoder 914.
  • the zero-crossing detector 904, the PLL 908, the controller 910, the clock 912 and the decoder 914 may be implemented in software, hardware or firmware.
  • the zero-crossing detector 904, the ADC 906, the PLL 908, the controller 910, the clock 912 and the decoder 914 are implemented using a MSP430 processor including program memory containing executable instructions, in the form of a software program.
  • the configuration of the receiver 108 illustrated in Fig.9A also permits the receiver 108 to detect and decode other modulating schemes, including conventional ripple control data communication.
  • the receiver 106 is downwardly compatible with other types of "ripple" modulation schemes.
  • the zero-crossing detector 904 generates an output signal 916 that is synchronised with positive zero-crossing events of the power signal 110.
  • a zero-crossing event is detected every 2OmS.
  • the zero-crossing detector 904 is enabled by the controller 910 about 300 ⁇ s before an estimated location of a positive zero-crossing event to reduce the likelihood of false zero crossings from voltage disturbances on the power signal 110.
  • the PLL 908 is configured to generate an output signal 917 that is synchronised with the detection of positive zero-crossing events of the power signal 110.
  • the PLL 908 provides an output signal 917 having the same frequency as, and a fixed phase relationship with the power signal 110. That is to say, the output signal 917 has a precise timing relationship with the power signal 110 so that output signal 917 of the PLL 908 is phase aligned with the power signal 110.
  • the output signal 916 is a OV to 3.3V 50Hz signal that is phased aligned with the power signal 110.
  • the controller 910 senses the PLL output signal 917 and monitors that signal to control the timing of the sensing of the power signal level values by the ADC 906 so that the controller 910 is able to construct a set of level values for each time-frame of corresponding time-frames of a pair of cycles of the power signal.
  • the processing of a pair 206 of power signals 110 to decode data encoded thereon is based on generating a difference signal for sets of signal values for corresponding time-frames 402-A, 402-B (ref. Fig.5) of the pair of cycles 206 of the power signal 110.
  • the generating of the difference signal cancels the fundamental frequency component, and harmonic components, of the power signal.
  • the resultant difference signal 1000 is indicative of the symbol-type represented by a pair of modulation signals.
  • the difference signal 1000 is obtained as a result of the modulation signals of corresponding time-frames having a phase-difference with respect to one-another, relative to a reference common to each time-frame.
  • a simplified flow diagram for a method of receiving data according to an embodiment of the invention is illustrated at
  • Sets of signal level values, for each time-frame of corresponding time-frames, may be sampled using any suitable technique.
  • One suitable technique is depicted in Fig.1OB.
  • the ADC 906 samples each cycle of the power signal 110 with a 12 bit ADC sampling signal 1002 having a sampling frequency of 115200Hz.
  • the ADC 906 samples two-thousand three hundred and four samples for each cycle of the power signal. Groups of sixteen samples are then summed to provide one-hundred and forty-four summed values for each 20ms cycle of the power signal. m order to subtract identical points on the power signal, all sampling is synchronised to positive zero-crossings of the power signal.
  • the period of the power signal varies slowly over a small range and there is also normally jitter in the zero crossing due to load induced noise. Therefore the PLL 908 output is generated in software to give a jitter free closely tracking 50Hz zero crossing.
  • sampling times of the ADC 906 are then locked, by the controller 910 (ref. Fig.9A), to the zero crossing of the signal 916 (ref. Fig.9A).
  • the controller 910 In each single cycle of the power signal, eight time frames are defined and each is aligned with the one-hundred and forty four summed samples, which in turn are locked to the zero-crossing of the signal 916. Signal processing is then carried out in each time-frame.
  • Fig.1OC depicts an example of the signal processing of a pair of corresponding time-frames 402-A, 402-B.
  • the time base of the representation of modulation signal 508 has been expanded.
  • six of the one-hundred and forty-four summed samples for each cycle are processed.
  • the decoding of a symbol entails obtaining summed signal level values (O M, M) for each cycle of the pair of consecutive cycles, processing the sets of level values to obtain a difference signal (D m ), and correlating the set of difference values (D m ) with square wave correlation signals (Kp, Kq) having a phase difference of 90° to provide two sets of correlated values (P, Q).
  • the square wave correlation signals (Kp, Kq) have the same frequency as the modulating signal, that is 1800Hz. By using two correlation signals in this way, slight phase variations in the modulation signal, of the type described with reference to Fig.8, will not prevent demodulation of a cycle of the power signal 110 including modulation signals.
  • the sets of correlated values (P, Q) are summed to provide a summed value.
  • the summed value is used by the decoder 914 (ref. Fig. 9A) to identify the symbol-type associated with the difference value.
  • the magnitude of the difference signals, and thus the respective summed values, will be different for different symbols.
  • the magnitude of the summed value is used by the decoder 914 to decode different symbols represented by pairs of modulation signals.
  • K p and Kq are square waves of frequency 1800Hz and magnitude 1 or -1. K p and Kq are shifted 90° from each other. So to correlate D m with K p , D m is multiplied by either 1 or -1 according to K p .
  • decoding is started one cycle after detecting the first modulation signal of the first cycle of a pair of cycles including modulation signals.
  • the detection of the first modulation signal of the first cycle may be accomplished by way of any suitable means.
  • the first modulation signal of the first cycle of a pair of cycles will have a higher magnitude.
  • the sum of the six summed values (D0...D5) for the first time-frame of the first cycle of a pair of cycles of the power signal will be significant even though, at that stage, it will not be the difference of two modulation signals.
  • the first "symbol" of the first cycle of a pair of cycles of the modulated power signal 110 is used for synchronising the decoder 914 to a pair of cycles including modulation signals.
  • synchronisation of the decoder 914 is controlled by control signals 920 provided to the controller 910 by the cycle-pair detector 900.
  • D0...D5 are each 16 bit values obtained by summing sixteen 12 bit values from the ADC 906 under the control of the controller 910.
  • a start flag (F start ) is set to identify the first cycle of a pair of cycles including modulation signals. Then at the first time-frame in the next cycle of the power signal (that is, the next 20ms cycle) a second flag (F V aiid) is set to indicate that decoding can start.
  • the only processing performed by the cycle-pair detector 900 is for the first symbol. In the example, this processing is conducted every 20ms because no synchronisation to a 40ms group (that is, two 20ms cycles) can be made until this valid symbol is received.
  • this processing is conducted every 20ms because no synchronisation to a 40ms group (that is, two 20ms cycles) can be made until this valid symbol is received.
  • must be greater than Sthresh for a symbol to be received.
  • Sthresh is a threshold magnitude value.
  • both cycles of a cycle pair need not include modulation signals.
  • Fig.12 and Fig.l2A depict an example of the demodulation of a pair of cycles of a power signal in which only one cycle of the pair includes modulation signals.
  • the data sent over the power distribution network 102 (ref. Fig.l) will vary according to the application of the system.
  • the data may include a command to isolate particular appliances, or consumer devices, from the power distribution network, to facilitate load shedding.
  • Fig. 13 depicts an example system block diagram of a system
  • a meter reading subsystem 1302 an intelligent air-conditioning control subsystem 1304, load shedding subsystem 1306, demand side supply management subsystem 1308, and inter-device data communication subsystem 1310.
  • Each sub-system may include a standalone receiver of the type described earlier, or a transceiver that includes a receiver and a transmitter (again, of the type described previously).
  • Fig.14 depicts a schematic diagram of an embodiment of a transceiver 1400.
  • a system according to present invention need not include all of the illustrated sub-systems, nor need it be limited to the examples illustrated. Indeed, it is envisaged that the present invention will find application in a broad range of different applications in which data communication over a power distribution network may be deployed, either uni-directionally or bi-directionally. Indeed, as is evident from Fig.13, a system according to the present invention may support uni-directional, or bi-directional, data communication.
  • subsystem 1302 is an example of an embodiment of the present invention that employs a bidirectional communication
  • subsystem 1304 is an example of a subsystem that employs uni-directional data communication. In either case, data will be communicated in "packets" comprising multiple bytes.
  • a gateway may include a receiver 108, a transmitter 105, or a transceiver 1400 (ref. Fig. 14) in the form of a combination of a receiver 108 and a transmitter 105.
  • the sub-systems In a bidirectional system, the sub-systems typically operate in a distributed configuration whereby a master controller (shown as gateway 1312) controls data communications to the receivers of the different sub-systems.
  • a system that uses a gateway 1312 also permits response signals from those sub-systems that include a transmitter. In such a system, each sub-system may only respond to requests originating from the gateway 1312. Packets sent from the gateway 1312 to a sub-system will typically include data instructing the sub-system as to what type of operation is required and how to interpret any additional data bytes in the packet. On the other hand, packets sent from a subsystem to the gateway 1312 will typically include data that acknowledges received commands, and/or sends requested data to the gateway 1312.
  • a gateway 1312 can also operate in broadcast, or retransmit mode in which case no reply is required from a sub-system.
  • the reply packet will typically be used to acknowledge the receipt of a gateway packet
  • each packet includes an even number of bytes coupled into words.
  • An example packet structure is as follows:
  • the gateway 1312 may use a customer device address to communicate with specific sub-systems. However, a sub-system will also typically echo its own address to the gateway 1312.
  • Table 5 includes example of commands that may sent to a sub-system that includes a "power-on-line relay". Such a relay is a single-channel, single phase receiver that receives power signals including modulation signals and decodes the instructions for controlling a device connected to the relay. Each command includes an associated command number.
  • Table 6 includes an example structure of a data message for communication to sub-system at address "12" instructing that sub-system to "Close relay 1 at address 12".
  • Table 7 includes an example structure of a reply message from the receiver at address "12" in acknowledging reception of the message of Table 5.
  • Table 8 includes an example structure of a data message for communication to receiver at address "234" instructing that receiver to "Read meter 1 from address 234"
  • Table 9 includes an example structure of a reply from the receiver at address
  • the instruction message has been corrupted. Corruption can be due to noise on the power system or to a collision with another message. If a reply is not received then the command needs to be retransmitted. In such a case, the sender needs to wait until the replier has had time to reply.
  • the type of command sent will determine the expected length of reply so that repeated collisions do not occur the wait time before retransmission needs to be randomly variable in each unit, but within limits.
  • the wait time will be typically be in increments of 160ms and will be between 160 and 4000ms.
  • a system may use an instruction set that conforms to the "Contact ID" security standard, hi such an embodiment, codes are translated by the gateway 1312 and either sent, or received, as a three-digit number command which may be transmitted as a local one byte command. Examples of suitable three-digit codes are provided in Fig.14.
  • the gateway acts as a filter of local commands by decoding addresses sent via radio or internet. These are typically by transformer address or network location. Each gateway may have multiple system addresses depending upon which database is active. hi such an embodiment, sub-systems respond to commands for on/off and the data (for example, meter data) is attached to command responses.
  • the gateway 1312 can also support open protocols and vendor protocols for automation and metering by translating to a simple one-byte contactID code for use, for example, with security systems.
  • the gateway 1312 may be is used to monitor energy usage in real time to give both an energy supplier and a customer far greater control over energy use.
  • sub-system appliances may communicate with the gateway 1312 wirelessly or via the power lines.
  • a customer may be able to access the gateway 1312, using a computer terminal 1314 communicatively coupled to the gateway 1312 via a communications network 1316, to operate, for example, an air conditioner thermostat remotely via the gateway.
  • Such an application may also enable remote control of air conditioning loads during periods of peak energy usage by responding to modulated power signals from the substation 104.
  • a gateway 1312 may also allow the monitoring of electricity used during peak periods and provide the ability to achieve dynamic metering from existing meters.
  • Other examples of services which may utilise the present invention include:
  • Security products and services including homeland security; Maintenance and installation services; and • Electricity and Emissions Trading.
  • a gateway will typically translate open standards to bridge devices, appliances, and meters. Typically messages may be translated into IPV6 the internet version 6 address structure in order to handle mass applications. Each gateway has range of IPV6 equivalent to each state of each device and meter. As will be appreciated, IPV6 has 128 bit addressing instead of the 32 bits used in IPV4 which is currently limited by standard internet. IPV6 is also more secure and the lower order bits are used to address the subsystems downstream of the gateway 1312 while the higher order bits are used to identify a specific gateway 1312.
  • a gateway may also be used as a protocol bridge between ranges of automation devices. For example, in one application, the gateway polls meter information and presents the data in modbus format for interfacing into building management systems.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

La présente invention concerne un procédé permettant d'envoyer des données sur un réseau de distribution de puissance (102) au moyen d'un signal d'alimentation en courant alternatif (110). Les données comprennent une séquence de symboles provenant d'un ensemble défini de types de symboles. Un ou plusieurs cadres temporels (402) sont définis dans chaque cycle (204, 208) d'une paire (206) de cycles du signal d'alimentation (110). Chaque cadre temporel (402-A) du premier cycle (204) de la paire (206) de cycles présente un cadre temporel correspondant (402-B) dans le second cycle (208) afin d'obtenir une paire de cadres temporels correspondants (402-A, 402-B). Un signal de modulation est appliqué à au moins un cadre temporel de chaque paire de cadres temporels correspondants afin d'obtenir, dans le prolongement des valeurs temporelles de chaque cadre temporel d'une paire de cadres temporels, une différence de signal entre chaque cadre temporel indiquant un type de symbole de la séquence de symboles.
PCT/AU2005/001978 2004-12-31 2005-12-30 Procede et systeme de communication de donnees WO2006069420A1 (fr)

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AU2004907366A AU2004907366A0 (en) 2004-12-31 Multipath ripple mechanism for secure power-on-line control
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