AU2005101076A4 - Data communication system and method - Google Patents

Description

WO 2006/069420 PCT/AU20051001978 -1- 0 o DATA COMMUNICATION SYSTEM AND METHOD This application claims priority from Australian Provisional Patent Application O No. 2004907366 filed on 31 December 2004, and Australian Provisional Patent Application No. 2005906676 filed on 30 November 2005, the contents of which are to be taken as incorporated herein by this reference.

0 0FIELD OF INVENTION

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The present invention relates to a system and method for data communication O 10 over an alternating current power distribution network. In a typical application, the l present invention may be used to enable demand side management of electrical loads connected to the power distribution network. However, the present invention is not intended to be so limited and thus may also be applicable to other applications. For example, the present invention may be used in automatic meter reading.

BACKGROUND OF THE INVENTION Various systems and methods are known for data comnunication over an alternating current power distribution network. Typically, such systems and methods rely on modulating an alternating current signal (hereinafter, the 'power signal') using a modulation technique that imparts information onto that signal. Modulation techniques that modulate information onto a power signal are often referred to as "ripple control".

Unfortunately, established ripple control techniques provide, by today's standards, a slow data-rate.

One known ripple control technique involves modulating a power signal to superimpose a small-bandwidth audio signal onto the power signal. This type of ripple control often uses different audio frequencies to communicate different bits of a code.

However, for each bit, the associated audio signal is transmitted for multiple cycles of the power signal. Thus, the total time required to transmit a single bit exceeds the period of a single cycle of the power signal. Accordingly, this technique provides a slow data rate relative to the frequency of the power signal.

Emerging techniques, such as broadband over power lines (BPL), provide a higher data rate than established ripple control techniques. However, such systems WO 2006/069420 PCT/AU2005/001978 -2o 0 operate using high frequency modulation signals that introduce increased design 0 complexity.

SIt would be an advantage if a communication system and method could be 0 provided that provided an improved data rate compared to established ripple control techniques, but that has a reduced design complexity as compared to emerging, high data rate, techniques.

0 SUMMARY OF THE INVENTION

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In general terms, the present invention provides a system for, and method of, 0 10 sending and/or receiving data over an alternating current power distribution network 0 carrying a power signal.

In one form, the present invention provides a method of sending data over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the method including: defining one or more time-frames in each cycle of a pair of cycles of the power signal, each time-frame of the first cycle of the pair of cycles having a corresponding time-frame in the second cycle to provide a pair of corresponding time-frames; and applying a modulation signal to at least one time-frame of each pair of corresponding time-frames to provide, over a continuum of time values of each timeframe of a pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.

In an embodiment, modulation signals are applied to each time-frame of corresponding time-frames to provide, relative to a reference common to each of those time-frames, a phase difference that permits a receiver to reconstruct the symbol sequence by performing a difference calculation between power signal level values associated with corresponding time-frames of the first and second cycle of a cycle pair.

In this way, the fundamental frequency,components, and the harmonics thereof, of the power signal may be removed.

Throughout this specification, references will be made to the term "time-frame" References to "time-frame" are to be understood to be references to a discrete time WO 2006/069420 PCT/AU2005/001978 -3o O segment, bounded by an upper and a lower time value, of a cycle of a power signal.

O Each cycle may include one or more time-frames.

In addition, references will also be made to each time-frame of a first cycle of O the power signal as forming, with a time-frame in a second cycle of a pair of cycles of the power signal, a pair of "corresponding" time-frames. Where used throughout this specification, references to "corresponding" time-frames are to be understood to be time-frames of the first and second cycle that have substantially the same time-wise 0 0 relationship with each cycle. In other words, each time-frame of a pair of corresponding time-frames will be bounded by substantially the same upper and lower time values of a O 10 respective cycle of a power signal relative to a reference common to each cycle.

C Typically, the reference will be a positive "zero-crossing" of each cycle of the power signal.

The amplitude and frequency of the power signal will vary according to the type and arrangement of the alternating current power distribution network. The power signal may be a high voltage power signal from the high tension side of a power distribution transformnner. For example, in one embodiment, the power signal is between 11000 Volts and 33000 Volts. In another embodiment, the power signal may be a mains voltage power signal obtained from the output of a mains power distribution transformer. In one embodiment, the power signal is a 240VAC 50Hz power signal. In another embodiment, the power signal is a 11 OVAC 60Hz power signal.

In an embodiment in which modulation signals are applied to each time-frame of corresponding time-frames to provide a phase difference, the phase-difference is about 180 degrees. A 180° phase difference may be a 1800 phase shift so that modulation signals of paired modulation signals are offset with respect to one another relative to the common reference. An embodiment that provides a pair of modulation signals having a 180° phase-offset is expected to provide additional benefits. In particular, it is expected to allow the use of a simple transmitter arrangement for applying the modulation signals. Alternatively, the 180° phase difference may be a phase inversion so the paired modulation signals are inverted with respect to one another relative to the common reference.

In an embodiment, each modulation signal is a periodic signal having a substantially constant frequency in the range of between four to eighty times greater WO 2006/069420 PCT/AU2005/001978 -4o O than the frequency of the power signal. Thus, in an embodiment that modulates a o power signal, the frequency of the modulation signal may be in the range of 400Hz to 6) 4000Hz. In a preferred embodiment, the frequency of the modulation signal is 1 OOHz.

O It is preferred that each modulation signal is a single cycle of a periodic signal.

However, each modulation signals may include multiple cycles of a periodic signal.

Preferably, for each symbol-type represented by a pair of modulation signals, the modulation signal of the first cycle has a different time-wise location with respect to a 0 respective time-frame.

In an embodiment, the modulation signals of a pair of modulation signals O 10 coincide time-wise, at least over an extent, relative to a reference common to the 0, corresponding time-frames. In one embodiment, the extent over which the modulation signals coincide is one half-cycle of the paired modulation signals. According to that embodiment, the relative magnitude relationship between the modulation signals and the relative location of the time-wise coincident half-cycles with respect to the common reference, varies according to the symbol type.

In an embodiment, each cycle pair includes a pair of corresponding time-frames for each symbol in the sequence.

It is preferred that the pair of cycles are consecutive cycles of the power signal.

However, it is not essential that the pair of cycles be consecutive cycles. Indeed, in an embodiment, the pair of cycles are separated by one or more other cycles of the power signal.

In an embodiment, each time-frame may be divided into plural time-slots. In an embodiment that applies modulation signals to each time-frame of corresponding timeframes so as to provide a phase-difference, the phase-difference may be provided by locating each modulation signal of a pair of modulation signals representing different symbol-types in different ones of a pair of time-slots. In one embodiment, each timeslot has a width that corresponds to the duration of a half-cycle of the modulation signal.

A predefined symbol-set may have any suitable number of symbols. For the purpose of this specification, a symbol-set that includes n symbols will be referred to as a base-n symbol-set.

WO 2006/069420 PCT/AU2005/001978 o o In an embodiment, the symbol-set includes two symbols (that is, a "base-2" (Nl o symbol-set). However, it is to be appreciated that the invention is not to be so limited.

For example, another embodiment of the invention includes a symbol-set that includes 0 four symbols (that is, a "base-4" symbol-set).

In an embodiment, a single byte of data is communicated by a pair of consecutive cycles of the power signal. In such an embodiment, each power signal cycle 0 includes eight time-frames, and each time-frame contains one data-bit in the form of a Ssingle cycle of a modulating signal. However, other embodiments of the invention may transmit more, or less data, again depending on the relationship of the frequency of the In O 10 modulating signal to the frequency power signal.

"l Each modulation signal may occupy a complete time-frame of the power signal or, alternatively, it may occupy a portion of a time-frame. Indeed, in one embodiment, the relationship between a modulation signal and a time-frame of the power signal, at least in terms of the location of the modulation signal within a time-frame, and the extent to which it occupies that frame, varies according to the symbol that is being represented by the modulating signal. Such a modulation scheme is expected to provide further improvements in data-rate since additional symbols may be represented as modulation signals that are time-shifted within a time-frame.

The present invention also provides a transmitter for sending data over a power distribution network carrying an alternating current periodic power signal, the data including a sequence of symbols from a predefined symbol-set, the transmitter including: timing means for defining one or more time-frames in each cycle of a pair of cycles of the power signal, each time-frame of the first cycle of the pair of cycles having a corresponding time-frame in the second cycle so as to provide a pair of corresponding time-frames; and signal injector means for applying a modulation signal to at least one time-frame of each pair of corresponding time-frames to provide, over a continuum of time values of each time-frame of a. pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.

The present invention also provides a method of receiving data sent over a power distribution network carrying an alternating current power signal, the data WO 2006/069420 PCT/AU2005/001978 -6- 0 O including a sequence of symbols from a predefined set of symbol-types, the method O including: U detecting a pair of cycles of the power signal including a modulation signal in at O least one time frame of corresponding time-frames of a first cycle and a second cycle of C¢3 the pair of cycles; sensing, for each time-frame of a pair of corresponding time-frames of the first 0 cycle and the second cycle, a set of signal level values;

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processing the sensed level values for corresponding time-frames of the pair of 0 cycles to generate a difference signal; and O 10 decoding the symbol type associated with the difference signal.

0 In an embodiment, either the first cycle or the second cycle of the pair of cycles includes one or more modulation signals and the other signal, that is, either the second cycle or the first cycle, is an "average" single cycle of the power signal that has been obtained by averaging multiple cycles of the power signal. Thus, in one embodiment, the detected pair of cycles of the power signal includes a cycle that has been obtained by way of an averaging process. Such an embodiment is expected to permit improved datarates in that adjacent cycles of the power signal may contain modulation signals for different symbols of the symbol sequence.

The present invention also provides a receiver for receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the receiver including: a detector detecting a pair of cycles of the power signal including a modulation signal in at least one time fi-rame of corresponding time-frames of a first cycle and a second cycle of the pair of cycles; and a signal processor sensing, for each time-frame of a pair of corresponding timeframes of the first cycle and the second cycle, a set of signal level values, processing the sensed level values for corresponding time-frames of the pair of cycles to generate a difference signal and decoding the symbol type associated with the difference signal.

The present invention also provides a transmitter for sending data over a power distribution network carrying an alternating current periodic power signal, the data WO 2006/069420 PCT/AU2005/001978 -7- 0 O including a sequence of symbols from a predefined symbol-set, the transmitter O including: Stiming means for defining one or more time-frames in each cycle of a pair of O cycles of the power signal so that each time-frame of a first cycle of the pair of cycles e¢ 5 has a corresponding time-frame in a second cycle of the cycle pair; and a signal injector means for applying, in a pair of corresponding time-frames, to the first cycle and the second cycle, a modulation signal to form a pair of modulation 0 0 signals representing a symbol-type of a symbol in the sequence;

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wherein relative to a reference common to each pair of corresponding time O 10 frames, paired modulation signals of those time-frames have a phase-difference so that the modulation signals of a pair of modulation signals coincide time-wise over at least an extent of each modulation signal of that pair.

Finally, the present invention also provides a receiver for receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined symbol-set, the receiver including: a detector detecting a pair of cycles of the power signal, each cycle of the pair including modulation signals located in corresponding time-frames to provide a pair of modulation signals which, relative to a reference common to each of the corresponding time-frames, have a phase-difference so that each modulation signal pair coincide timewise over at least an extent; and a processor processing each detected pair of cycles of the power signal to provide a difference value for each modulation signal pair and using each difference value to identify the symbol-type represented by each pair of modulation signals.

A particular advantage of the present invention is that it provides a relatively high-speed and robust method of communicating data over an alternating current power distribution network.

DESCRIPTION OF THE DRAWINGS The present invention will now be described in relation to various embodiments illustrated in the accompanying drawings. However, it must be appreciated that the following description is not to limit the generality of the above description.

In the drawings: WO 2006/069420 PCT/AU2005/001978 -8o O Fig.1 is a system block diagram of a system according to an embodiment of the O present invention for sending data over a power distribution network carrying an Salternating current power signal; 0 Fig.2 is a simplified block diagram for a transmitter suitable for use with the

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embodiment illustrated in Fig. 1; Fig.2A is a signal diagram showing consecutive cycles of an alternating current 0 power signal;

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0 Fig. 2B depicts a simplified flow diagram of an embodiment of a method for

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Stransmitting data according to an embodiment of the invention; O 10 Fig.3 is a block diagram of a timing controller suitable for incorporating in

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C1 modulator of Fig.2; Fig.4 is a signal timing diagram illustrating timing relationships between a single cycle of a power signal, an IRQ and an IRQ counter; Fig.4A shows a time-slot arrangement of a time-frame of the power signal shown in is a signal diagram illustrating the occupation of different time-slots of a time-frame of a power signal for each symbol of a base-2 symbol-set; is a signal diagram illustrating an example of a different occupation of time-slots of a time-frame of a power signal according for each symbol of a base-2 symbol-set; Fig.6 is a simplified schematic diagram of a signal injector suitable for incorporating in the transmitter of Fig.2; Fig.6A is a signal diagram illustrating the relationship between a control signal and the signal current (Im) of the signal injector; Fig.6B is a signal diagram illustrating the relationship between a power signal cycle, capacitor voltage and signal current (Im); Fig.6C is a diagram showing a typical signal energy of a modulation signal; Fig.7 is a signal diagram showing an example of a pair of cycles of the power signal containing modulation signals; Fig.7A is an example of a pair of modulation signals for a "symbol 0"; Fig.7B is an example of a pair of modulation signals for a "symbol 1"; WO 2006/069420 PCT/AU2005/001978 -9o O Fig.8 is a set of signal diagrams illustrating examples of the effect of impedance O variations on the generation of a signal voltage; r^ Fig.9 is a simplified block diagram of an embodiment of a receiver suitable for O use with a system in accordance with an embodiment of the present invention; e¢ n 5 Fig.9A is a detailed block diagram of a receiver suitable for use with a system in accordance with an embodiment of the present invention; is a simplified signal diagram showing an example derivation of a difference signal; 0 Fig. 1 OA is a flow diagram of a receiver process; O 10 Fig.10B is a signal diagram showing an example of sampling a modulation signal; is a timing diagram of a process for demodulating a symbol of a base-2 symbol set; Fig.lOD is a timing diagram of a process for demodulating a symbol of a base-2 symbol set; Fig. 11 shows an example of a demodulation cycle; Fig.12 is a timing diagram of a process for demodulating a symbol of a base-2 symbol set; Fig.12A is a timing diagram of a process for demodulating a symbol of a base-2 symbol set; Fig. 13 is a block diagram of a system according to another embodiment of the present invention; Fig.14 is a schematic diagram of a transceiver according to an embodiment of the present invention; and Fig. 15. is a table including example instruction codes for an embodiment of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS Reference will now be made in detail to the present preferred embodiments of the invention illustrated in the accompanying drawings. In describing the preferred embodiments and applications of the invention, specific terminology is employed for the sake of clarity. However, the invention is not intended to be limited to the specific WO 2006/069420 PCT/AU2005/001978 o o terminology so selected, and it is understood that each specific element includes all O technical equivalents that operate in a similar manner in similar communication systems Sto accomplish a similar purpose.

0 In this description, the present invention will be described in terms of an embodiment that supports the sending of data over an alternating current power distribution network carrying a 240VAC 50Hz power signal. However, it is to be 0 understood that the present invention is not to be limited to such a power distribution Snetwork.

The described embodiment of the present invention communicates one-byte O 10 (that is, 8-bits) of data in a pair of consecutive cycles of the power signal. Thus, a transmission system in accordance with the present invention, that uses a base-2 symbol set (that is, a binary system) and a 50Hz power signal frequency, will provide an overall data rate of 200bps. As will be explained in more detail later, higher data rates may be achieved using higher order symbol-sets. By way of example, a base-4 system may transmit two-bytes of data in a pair of consecutive cycles and thus provides an overall data rate of 400bps.

In an 8-bit transmission system that employs a base-2 symbol-set, each cycle of a pair of consecutive cycles includes eight modulation signals, one for each bit. In the present case, each modulation signal is a single cycle of an 1800Hz sinusoidal-like signal.

Fig.1 depicts a system 100 for sending data over a power distribution network 102 carrying a 240VAC 50Hz alternating current power signal. The system 100 includes a power substation 104, a transmitter 105, a distribution transformer 106, and receivers 108.

The substation 104 includes an alternating current (AC) power generator that provides a high voltage power signal, typically 11000 VAC 50Hz. The high voltage power signal is converted by the distribution transformer 106 into a three phase 415 VAC 50Hz output. Each single phase of the three phase output provides a low voltage power signal 110, typically 240VAC 50Hz. In the present case, Fig. depicts a single phase circuit 112 for clarity.

In the embodiment illustrated, the transmitter 105 and the receivers 108 are located in the single phase circuit 112 side of the network 102.

WO 2006/069420 PCT/AU2005/001978 -11o o The transmitter 105 applies modulation signals to predefined time-frames of a o pair of cycles of the power signal 110 so to enable data to be sent over the power distribution network 102. In the present case, the data is communicated as a message O 114 to one or more receivers 108. The message 114 may originate from, for example, a service provider responsible for managing the power distribution network or it may originate from another entity. In this respect, although in the illustrated embodiment the transmitter 105 is shown on the load side of the distribution transformer 106, it Scould equally be located on the power generation side.

Irrespective of where the transmitter 105 is located in the network 102, the O 10 transmitter 105 accepts the message 114 as a data stream consisting of a sequence of C,1 symbols from a predefined symbol set and applies modulation signals to a pair of cycles of the alternating current power signal 110 to communicate the message to one or more selected receiver(s) 108. In this respect, the selected receiver(s) 108 may be a specific one of the receivers 108, or a selected set of the receivers 108, or it may be all of the receivers 108.

As will be explained in more detail later, the receivers 108 detect a pair of cycles of the alternating current power signal 110 including modulation signals which have been applied by the transmitter 105 and demodulate the power signal 110 to reconstruct the message 114.

Fig.2 depicts an embodiment of a transmitter 105 suitable for use with an embodiment of the present invention. As shown, the transmitter 105 includes a timing means (shown as timing controller 200) and a signal injector 202.

The timing controller 200 receives a message 114, consisting of a sequence of symbols from a predefined symbol-set for transmission to one or more of the receivers 108, and defines one or more time-frames in each cycle of a pair of cycles of the power signal so that each time-frame of a first cycle of the pair of cycles has a corresponding time-frame in a second cycle.

In the illustrated embodiment, for each time-frame, the timing controller 200 activates the signal injector 202 to apply a modulation signal, in at least one of the timeframes of a pair of corresponding time-frames of the first cycle and the second cycle. In the embodiment illustrated, modulation signals are applied to each time-frame of a pair WO 2006/069420 PCT/AU2005/001978 -12- 0 O of corresponding time-frames to thereby form a pair of modulation signals representing O a symbol-type of a symbol in the sequence.

SAs will be explained below, the modulation signals of a pair of corresponding O time-frames are applied so as to provide, over a continuum of time values of each timeframe of a pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.

Although the illustrated embodiment will be described as applying, in a pair of 0 corresponding time-frames, a modulation signal to the first cycle and the second cycle of a pair of cycles of the power signal, it is not essential that each time-frame of a pair O 10 of corresponding time-frames include a modulation signal. Indeed, in an alternative 0 embodiment, only one of the time-frames of a pair of corresponding time-frames includes a modulation signal.

Fig.2A depicts a signal diagram of a pair 206 of consecutive cycles of the power signal 110. As described above, in the illustrated embodiment, the applying of the modulation signals to a pair of cycles 206 of the power signal 110 (ref. Fig. 1) involves applying modulation signals to a first cycle 204 (shown as Cycle n) of the pair of cycles 206 of the power signal 110 to provide, in different time-frames of that cycle 204, a modulation signal for each symbol of the symbol sequence of the message.

For each modulation signal applied to the first cycle 204, a modulation signal is also applied to a second cycle 208 (shown as Cycle n+l) of the pair of cycles 206 to provide, in the corresponding time-frames of the second cycle 208, an associated modulation signal to form, for each symbol, a pair of modulation signals for each symbol of the sequence.

Again, in the present case, the first cycle 204 and thc second cycle 208 are shown as consecutive cycles. However, it is to be appreciated that the first cycle 204 and the second cycle 208 need not be consecutive. Indeed, in another embodiment the first cycle 204 and the second cycle 208 could be separated by one or more other cycles of the power signal.

In the present case, and as will be explained in more detail later, relative to a reference common to each pair of corresponding time fiames, paired modulation signals of those time-frames have a phase-difference so that, over a continuum of time values of WO 2006/069420 PCT/AU2005/001978 13o O each time-frame of a pair of corresponding time-frames, a signal difference is provided Cl O that is indicative of a symbol-type of the symbol sequence.

SIn the present case, paired modulation signals coincide time-wise over at least an O extent of each modulation signal of that pair. Whilst it is not essential that paired modulation signals coincide time-wise, it is preferred that the modulation signals coincide time-wise over at least an extent of each modulation signal of a pair of corresponding time-frames so as to reduce the overall width of the time-frames.

SDuring processing of a pair of cycles of the power signal containing modulation signals by a receiver 108, a difference processing technique applied to pairs of cycles O 10 containing modulation signals. The difference processing cancels the fundamental frequency and harmonic component of the power signals, but provides a difference signal that is decodable to identify the symbol-type represented by each pair of modulation signals. The modulation scheme employed by the invention will be described in more detail later. A simplified flow diagram of an embodiment of the method for transmitting data, as described above, is depicted in Fig.2B.

Fig.3 depicts an embodiment of a timing controller 200 suitable for incorporating in an embodiment of a transmitter in accordance with the present invention.

As shown, the timing controller 200 includes a positive "zero-crossing" detector 300, a phase locked loop (PLL) 302, an input register 304, a controller 306 and a clock 308. The zero-crossing detector 300, the PLL 302, the input register 304, and the clock 308 may be implemented in software, hardware or firmware. In one embodiment, the zero-crossing detector 300, the PLL 302, the input register 304, and the clock 308 are implemented using a MSP430 processor including program memory containing executable instructions, in the form of a software program, for implementing the zerocrossing detector 300, the PLL 302, the input register 304, and the clock 308.

In the illustrated embodiment, the zero-crossing detector 300 senses the power signal 110 and generates an output signal 310 that is synclhronised with positive zcrocrossing events of the power signal 110. For a 240VAC 50Hz power signal, a zerocrossing event is detected every In the illustrated embodiment, the zero-crossing detector 300 is enabled by the controller 306 about 300jis before an estimated location of a positive zero-crossing WO 2006/069420 PCT/AU2005/001978 14o O event to reduce the likelihood of false zero crossings from voltage disturbances on the Spower signal 1 10. In this respect, it will be understood that a "positive zero-crossing Q event" occurs when magnitude of the power signal 110 varies from a negative value to a O positive value.

The PLL 302 is configured to generate an output signal 314 that is synchronised with the detection of zero crossing events. In the present the PLL 302 provides an output signal 314 having the same frequency as, and a fixed phase relationship with the Spower signal 110. That is to say, the output signal 314 has a precise timing relationship with the power signal 110 so that output signal 314 of the PLL 302 is phase aligned O 10 with the power signal 110. In the present case, the output signal 314 is a OV to 3.3V signal that is phased aligned with the power signal 110.

The controller 306 senses the PLL output signal 314 and monitors that signal to generate a synchronisation signal 314 which is asserted on positive zero-crossing events of the PLL output signal 314. Thus, in the illustrated embodiment, where the power signal is a 50Hz power signal, the synchronisation signal 314 is asserted every When the synchronisation signal 314 is asserted, an internal counter of the controller (not shown), triggered by the clock 308, is reset. The internal counter provides a count sequence having a duration that substantially corresponds with, or is less than, the period of a single cycle of the power signal 110. Thus, in the present case the duration of the count sequence is about As is depicted in Fig.4, each count 400 (shown as time-frame counts 1 to 8) of the count sequence defines the beginning of, and identifies, a respective time-frame 402 of a single cycle 204, 208 (ref. Fig. 2A) of a pair 206 of cycles of the power signal 110.

In the present case, the number of time-frames 402 of each cycle 204, 208 (ref.

Fig. 2A) of a pair 206 of cycles of the power signal 110 corresponds with the number of symbols that are able to be represented in a pair of consecutive cycles 204, 208 of the power signal 110 using a modulation signal pair. Thus, in the illustrated embodiment, which communicates eight symbols in a pair 206 of cycles 204, 208 of the power signal 110, each cycle 204, 208 includes eight time-frames 402.

In this respect, because each count of the internal counter corresponds with a respective time-frame, each nth count of N counts of the internal counter also corresponds with the nth symbol in a symbol sequence having a sequence length of N WO 2006/069420 PCT/AU2005/001978 o O symbols. Thus, and again using a base-2 symbol-set as an example, if 8 symbols (as 8- O bits of data) are communicated in a pair 206 of cycles 204, 208 of the power signal 110, Seach cycle 204, 208 of the pair of cycles 206 will include eight time-frames 402, that is, O one for each symbol that is represented in the pair of cycles 206 as a pair of modulation M¢ 5 signals. As shown in Fig.5, each modulation signal 508 of a pair of modulation signals representing a symbol-type will be located within corresponding time-frames 402-A, 402-B of each cycle 204, 208 of a pair of cycles 204, 208 of the power signal 110.

0 Referring again to Fig.4, in the illustrated embodiment, each count of the internal counter also triggers an interrupt request (IRQ) 404 on the controller 306. In O 10 the embodiment illustrated, each IRQ 404 calls an associated interrupt service routine (ISR) that provides a further count sequence, triggered by an IRQ counter clock 406, to provide a count for each time-frame 402.

Each count of the ISR counter effectively defines the beginning of a time-slot 408 of a time-frame 402 of each single cycle 204, 208 (ref. Fig. 2A) of the power signal 110.

In the illustrated embodiment, the interval between consecutive counts of the ISR counter clock 406, associated with the same IRQ (and thus the same time-frame), correspond, time-wise, to the time period of one-half cycle of the modulation signal.

Thus, in the present case, each time-slot 408 (ref. Fig.4A) has a width that is substantially the same as the duration of a half-cycle of the modulation signal. Thus, as is shown in Fig.5, a single cycle of a modulation signal 508 will substantially completely occupy a pair of sequential time-slots 500, 502, 504, 506. In the present case, the width of a single time-slot 408 (ref. Fig.4A) for an 1800Hz modulating signal is about 277uS.

Referring again to Fig.5, for each pair of corresponding time-frames 402-A, 402-B, different pairs of sequential time-slots 500, 502 and 504, 506 of each time-frame are associated with different symbols of the symbol-set.

For each symbol-type, the first- modulation signal 508-1, 508-3 of a pair of modulation signals 508-1, 508-2 and 508-3, 508-4, representing a symbol type (in this case, the modulation signals of time frame 402-A) will occupy a different respective pair of sequential time-slots 408 of a time-frame 402-A of the first cycle 204. In this way, for different symbol-types, the modulation signal 508-1 of the first cycle 204 will WO 2006/069420 PCT/AU2005/001978 -16o o have a different time-wise location with respect to a respective time-frame 402-A as (N1 O compared to modulation signal 508-3 of the first cycle 204 of a modulation signal pair Srepresenting a different symbol type.

0 In the embodiment illustrated, the number of time-slots 408 of a time-frame 402 depends upon the base of the symbol-set. For example, and again as is depicted in for a base-2 symbol set a time-frame 402 will comprise at least three time-slots "0 408.

0' Although in the illustrated embodiment the number of time-slots has been limited according to the base of the symbol-set, as shown in Fig.5A, other embodiments In O 10 of the invention may use a number of time-slots that is independent of the base of the C,1 symbol-set. Such an embodiment may be apply, for example, where the modulation signals of corresponding time-frames do not time-wise coincide to any extent relative to a reference common to each time frame of the pair of corresponding time-frames, but instead are spaced apart time-wise relative to the common reference. In such an embodiment, the modulation signals will still have a phase difference that allows a receiver to generate a difference signal that is decidable to identify the symbol type represented by the pair of modulation signals.

Having described different suitable structures of the time-frames 402 of cycles 204, 208 (ref. Fig. 2A) of a pair of cycles 206 of the power signal 110, and a suitable time-slot 408 arrangement, the transmission of a sequence of symbols from a base-2 symbol-set will now be described.

First, with reference again to Fig.3, the controller 306 runs a main-program loop, comprising a set of program instructions resident in program memory that periodically polls a flag to determine whether the input register 304 contains a new symbol sequence for transmission. In the present case, the flag is polled on sensing each positive zerocrossing event of the power-signal 110.

If the flag has been set, the controller 306 resets the internal counter and sets a "cycle count" bit to identify the first cycle 204 of the pair of consecutive cycles of the power signal 110 to be modulated with the symbol-sequence.

For each count of the internal counter, and thus for each time-frame 408 (ref.

Fig.4A) of the power signal 110, the controller 306 reads the bit-pattern, or the bit, of the first symbol of the symbol sequence and identifies the symbol-type represented by WO 2006/069420 PCT/AU2005/001978 -17each bit (or bit-pattern). Having identified the symbol-type, the controller 306 then retrieves a "first-cycle" control code from program memory.

The "first-cycle" control code represents a code for generating a serial output, as a control signal 316, to the signal injector 202 synchronous with the IRQ counter clock 406 (ref. Fig.4), to activate the signal injector 202 to apply modulation signals to at least one time-frame of the first cycle 204 of a pair of cycles 206 of the power signal 110.

In the embodiment illustrated, the length of the "first-cycle" control code is set by base of the symbol-set and identifies which pair of sequential times-lots of a timeframe 402 is to be occupied by the modulation signal for a respective symbol.

An example of a set of "first-cycle" control codes for a base-2 symbol-set is provided in Table 1 (where X represents an occupied time-slot).

TABLE 1 An example of a set of "first-cycle" control codes for a base-4 symbol set is provided in Table 2 (where X represents an occupied time-slot).

TABLE 2 Having retrieved a "first-cycle" control code from program memory, for each count of the IRQ counter (and thus for each time-slot) the controller 306 checks a respective bit of the control code (for example, for the first IRQ count, the first bit of the WO 2006/069420 PCT/AU2005/001978 -18o O control code is the respective bit) and, if the respective bit of the control code is o asserted, a control signal 316 is output to activate the signal injector 202 to apply a half- Scycle of the modulation signal to that time slot of a time frame 402 of the first cycle 204 o corresponding to the internal counter. The characteristics of the control signal 316 depend upon the arrangement of the signal injector 202.

Fig.6 depicts a signal injector 202 arrangement suitable for use with an embodiment of the present invention. Although the present embodiment will be described in relation to the illustrated signal injector 202, it is to be appreciated that other signal injector arrangements may be used.

O 10 The signal injector 202 shown in Fig.6 includes a series arrangement of an 0, altemistor 600, a capacitor 602 and an inductor 604.

As shown in Fig.6A, the series arrangement of the capacitor 602 and the inductor 604 provides an oscillator circuit that, in use, provides a positive half-cycle current (Im) 608 in response to a first pulse 612 of a control signal 316 and a negative half-cycle current (Im) 610 in response to a subsequent pulse 614 of the control signal 316.

As shown in Fig.6, the series arrangement of the alternistor 600, the capacitor 602 and the inductor 604 is connected directly across the signal lines of the power distribution network 102. As will be appreciated, an alternistor 600 is an alternating current switch which is turned on by a pulse to its gate electrode and turns off when current through it drops to zero. The capacitor 602 and the inductor 604 fonrm a series resonant circuit having a resonant frequency which determines the frequency of the modulating signal.

Fig.6A depicts an example of a control signal 316 for use with the illustrated signal injector 202. Again, it is to be appreciated that the actual characteristics of the control signal 316 will depend on the arrangement of the signal injector 202. In the signal diagram illustrated in Fig.6A, the control signal 316 includes spaced apart pulses.

The operation of the signal injector 202 will now be described in more detail.

First, referring again to Fig.6, after a positive zero-crossing event has been detected, and for the first cycle 204 (ref. Fig. 2A) of a pair 206 of consecutive cycles of the power signal 110, the power signal 110 initially has a positive voltage and the capacitor WO 2006/069420 PCT/AU2005/001978 -19o voltage is negative, from a prior charging cycle. The timing for the prior charging cycle O of the capacitor 602 will be described in more detail later.

SWhen the alternistor 600 is "switched on" by pulse 612, the stored negative O charge in the capacitor 602, together with the positive voltage of the power signal (at r n 5 least during the period that the alternistor arrangement 600 remains switched on), results in the production of a large positive current Im as a result of the capacitor 602 discharging through the inductor 604. For the first time frame of the first cycle 204, and as a result of the timing of the prior charging cycle of the capacitor 602 with respect to the power signal 110, the voltage responsible for generating the positive current Im O 10 will typically be twice that of the power signal voltage 110.

C During discharge, the capacitor 602 voltage reduces to zero. However, since the power signal level is still positive, a positive current Im is maintained through the alternistor arrangement 600 and thus the altemistor arrangement 600 remains closed.

After discharge, the capacitor 602 starts recharging as energy returns to the capacitor 602 from the inductor 604. During recharging, the capacitor voltage increases above the voltage of the power signal 110 and, at that point, the signal current Im reduces until it reaches zero and the alternistor arrangement 600 "opens", After the alternistor arrangement 600 has opened, no further signal current Im flows in the series arrangement. However, the capacitor 402 remains charged at a positive voltage.

Thus, when the altemistor 600 is switched on by the second pulse 614, the capacitor 602 again discharges through the inductor and a similar discharge pattern occurs. However, for this discharge cycle the signal current Im flows in the opposite direction relative to the previous discharge cycle.

As will be appreciated, the above-described technique permits individual half cycles of signal current Im to be generated under the control of the control signal 316.

In this respect, a typical charging and discharging cycle, and the resultant circuit current Im is shown in Fig. 6B. As shown, the prior charging cycle, which is the illustrated embodiment is required to start the oscillation the alternistor 600, is provided by activating the signal injector 202 to generate a "start pulse" 616 just before the positive going zero crossing of the power signal 110. In the present case, the start pulse is located about 2mS prior to the positive zero-crossing. The location of the start pulse WO 2006/069420 PCT/AU2005/001978 O 616 results in a prior charging cycle in which the capacitor 602 is charged with a O negative voltage.

:S In the embodiment illustrated, the control of the timing of the generation of the O start pulse 616 is achieved by the controller 306 synchronising the timing of the generation of the start pulse relative to the positive zero-crossing event of the cycle of the power signal 100 immediately prior to the first cycle of the pair of power signals to which modulation signals are to be applied.

0 As shown in Fig. 6B, the signal injector 202 is also activated to generate "dummy pulses" 618. In the illustrated embodiment of the signal injector 202, "dummy O 10 pulses" 618 are required to maintain a relative difference between the power signal level 0, and the capacitor voltage during time frames 402 so as to sustain oscillation of signal current Thus, the "dummy pulses" are applied at the voltage peaks of the power signal. In this respect, the dummy pulses are so called because they do not form part of the data. It will be appreciated that other signal injector arrangements may not generated "dummy pulses", but may nevertheless be capable of applying modulation signals to the power signal 110.

In view of the above, and as is shown in Fig.6B, when the voltage of the power signal 110 is increasing in a positive direction, the half cycles of signal current Im are positive immediately followed by a negative followed by a gap of no current, to ensure that the signal current Im will continue to oscillate without the current dying away.

On the other hand, when the voltage of the power signal 110 is going in the reverse direction the reverse pattern is used.

The applying of modulation signals to the second cycle 208 (ref. Fig.2A) of a pair of cycles 206 (ref. Fig. 2A) of the power signal 110 uses a similar technique to that described above, except that the modulation of the second cycle 208 of the power signal 110 uses different control codes. In particular, the control codes associated with the modulation of the second cycle 208 will have a difference in structure so the modulation signal of the second cycle 208 will occupy a different time-slot pair of a time-fiame 402 of the second cycle 208 that corresponds with a time-frame of the first-cycle 204.

In the present case, the use of different time-slots pairs provides, between modulation signals for the same symbol-type, a phase difference of 180 degrees with respect to a reference common to corresponding time-frames. In this case, the common WO 2006/069420 PCT/AU2005/001978 -21 o O reference is the beginning of each time-frame 402 of a pair of corresponding time- C'i O frames. As described above, in the embodiment illustrated the beginning of each time- Sframe 402 has a time-wise location that has been established relative to the "positive O zero crossing" of the cycle of the power signal 110 to be modulated.

An example of "second-cycle" control codes for a base-2 symbol set is provided in Table 3 (where X represents an occupied time-slot).

0 o WO 2006/069420 PCT/AU2005/001978 -22-

O

O TABLE 3 SECOND CYCLE TIME SLOT SSYMBOL 1 2 3 CONTROL

SCODE

0 X X 011 1 X X -110 o An example of "second cycle" control codes for a base-4 symbol set is provided o in Table 4 (where X represents an occupied time-slot).

0 TABLE 4 CSECOND CYCLE TIME SLOT BIT

CONTROL

SYMBOL 1 2 3 4 5 6 PATTERN

CODE

0 00 X X 011000 1 01 X X 000011 2 10 X X 001100 3 11 X X 110000 The signal current Im results in a modulation signal being applied to the power signal as a signal voltage, due to the source impedance of the power distribution network. As each transmission consists of only one cycle of 1800Hz current, the required signal voltage is quite high. However, sufficient signal voltage, and thus modulation signal energy, can easily be achieved with transmitter peak currents of about five amps. In this respect, the typical energy of a modulation signal is shown in Fig.6C.

Fig.7 depicts an example of a pair of cycles 204, 208 of the power signal 110 containing modulation signals in corresponding time-frames 402-A, 402-B. As shown, each cycle 204, 208 of the pair of cycles 206 includes eight time-frames 402-A, 402-B.

Each time-frame 402-A of the first cycle 204 of the pair of cycles 206 has a corresponding time-frame 402-B in the second cycle 208 of the cycle pair 206. As shown, each pair of corresponding time-frames 402-A, 402-B, includes a modulation signal that has been applied to the first cycle 204 and the second cycle 208 respectively, to form a pair of modulation signals representing a symbol-type of a symbol in the sequence.

WO 2006/069420 PCT/AU2005/001978 -23-

O

O As is depicted in Fig.7A and Fig.7B, relative to a reference common to each pair O of corresponding time frames 402-A, 402-B, paired modulation signals of those time- Sframes 402-A, 402-B have a phase-difference of 180 degrees so that the modulation O signals of a pair of modulation signals coincide time-wise over at least an extent of each modulation signal of that pair. In the present case, the pair of modulation signals representing "symbol 0" coincide time-wise in "time-slot In addition, the pair of modulation signals representing "symbol 1" also coincide time-wise in "time-slot 2".

As shown in Fig.8, the source impedance of the distribution network 102 will vary depending on the distance of the receivers 108 from the distribution transformer O 10 106 (ref. Fig.l). For example, for distances close to the distribution transformer 106 the Cl network impedance will be low and almost entirely reactive. On the other hand, at the end of a long network (for example, 4km) the resistive component is more significant but still well within the capability of the transmitter.

As the ratio of reactance to resistance varies, the phase of the generated signal voltage (that is, the phase of the modulation signals) resulting from Im will also vary over a small range. In this respect, Fig.8 depicts waveform diagrams illustrating the effect of a variation in the ratio of reactance to resistance.

Using a modulation scheme in accordance with the present invention, a suitable receiver arrangement is able to demodulate data, modulated onto a pair of consecutive cycles of the power signal 110, irrespective of the phase variation caused by network variations in the ratio of reactance to resistance.

One suitable receiver arrangement will now be described in more detail with reference to Fig.9.

Fig.9 depicts a simplified block diagram of a receiver 108 according to an embodiment of the present invention. As shown, the receiver 108 includes a cycle-pair detector 900 and a signal processor 902.

The cycle-pair detector 900 detects pair of cycles of the power signal that include a modulation signal in at least one time frame of corresponding time-frames of a first cycle and a second cycle of the pair of cycles. The signal processor 902 senses, for each time-frame of a pair of corresponding time-frames of the first cycle and the second cycle, a set of signal level values, and processes the sensed level values for WO 2006/069420 PCT/AU2005/001978 -24-

O

O corresponding time-frames of the pair of cycles to generate a difference signal. The (Nl o signal processor 902 then decodes the symbol type associated with the difference signal.

6) Fig.9A depicts an embodiment of a receiver 108 in more detail. As shown, the O signal processor 902 includes a zero-crossing detector 904, an analog-to-digital e¢ n 5 converter (ADC) 906, a phase locked loop (PLL) 908, a controller 910, a clock 912 and a decoder 914. The zero-crossing detector 904, the PLL 908, the controller 910, the clock 912 and the decoder 914 may be implemented in software, hardware or firmware.

0 In one embodiment, the zero-crossing detector 904, the ADC 906, the PLL 908, the controller 910, the clock 912 and the decoder 914 are implemented using a MSP430 O 10 processor including program memory containing executable instructions, in the form of a software program. The configuration of the receiver 108 illustrated in Fig.9A also permits the receiver 108 to detect and decode other modulating schemes, including conventional ripple control data communication. Thus, in the present case the receiver 106 is downwardly compatible with other types of "ripple" modulation schemes.

In the illustrated embodiment, the zero-crossing detector 904 generates an output signal 916 that is synchronised with positive zero-crossing events of the power signal 110. Thus, for a 240VAC 50Hz power signal, a zero-crossing event is detected every The zero-crossing detector 904 is enabled by the controller 910 about 300gs before an estimated location of a positive zero-crossing event to reduce the likelihood of false zero crossings from voltage disturbances on the power signal 110.

The PLL 908 is configured to generate an output signal 917 that is synchronised with the detection of positive zero-crossing events of the power signal 110. In the present case, the PLL 908 provides an output signal 917 having the same frequency as, and a fixed phase relationship with the power signal 110. That is to say, the output signal 917 has a precise timing relationship with the power signal 110 so that output signal 917 of the PLL 908 is phase aligned with the power signal 110. In the present case, the output signal 916 is a OV to 3.3V 50Hz signal that is phased aligned with the power signal 110.

The controller 910 senses the PLL output signal 917 and monitors that signal to control the timing of the sensing of the power signal level values by the ADC 906 so that the controller 910 is able to construct a set of level values for each time-frame of corresponding time-frames of a pair of cycles of the power signal.

WO 2006/069420 PCT/AU2005/001978

O

O The processing of a pair 206 of power signals 110 to decode data encoded O thereon is based on generating a difference signal for sets of signal values for Scorresponding time-frames 402-A, 402-B (ref. Fig.5) of the pair of cycles 206 of the O power signal 110.

In this respect, and as is shown in Fig.10, the generating of the difference signal cancels the fundamental frequency component, and harmonic components, of the power signal. The resultant difference signal 1000 is indicative of the symbol-type represented Sby a pair of modulation signals.

The difference signal 1000 is obtained as a result of the modulation signals of O 10 corresponding time-frames having a phase-difference with respect to one-another, relative to a reference common to each time-frame. A simplified flow diagram for a method of receiving data according to an embodiment of the invention is illustrated at Fig. 1 OA.

Sets of signal level values, for each time-frame of corresponding time-frames, may be sampled using any suitable technique. One suitable technique is depicted in Fig. 1 OB.

Here, the ADC 906 (ref. Fig.9A) samples each cycle of the power signal 110 with a 12 bit ADC sampling signal 1002 having a. sampling frequency of 115200Hz.

Thus, for a 50Hz power signal, the ADC 906 samples two-thousand three hundred and four samples for each cycle of the power signal. Groups of sixteen samples are then summed to provide one-hundred and forty-four summed values for each 20ms cycle of the power signal.

In order to subtract identical points on the power signal, all sampling is synchronised to positive zero-crossings of the power signal. However, the period of the power signal varies slowly over a small range and there is also normally jitter in the zero crossing due to load induced noise. Therefore the PLL 908 output is generated in software to give a jitter free closely tracking 50Hz zero crossing.

The sampling times of the ADC 906 (ref. Fig.9A) are then locked, by the controller 910 (ref. Fig.9A), to the zero crossing of the signal 916 (ref. Fig.9A).

In each single cycle of the power signal, eight time frames are defined and each is aligned with the one-hundred and forty four summed samples, which in turn are locked to the zero-crossing of the signal 916.

WO 2006/069420 PCT/AU2005/001978 -26-

O

O Signal processing is then carried out in each time-frame.

Cl O Fig.1OC depicts an example of the signal processing of a pair of corresponding time-frames 402-A, 402-B. For clarity, the time base of the representation of O modulation signal 508 has been expanded. As shown, for each time-frame 402-A, 402- B, six of the one-hundred and forty-four summed samples for each cycle are processed.

As shown, the decoding of a symbol entails obtaining summed signal level Svalues (OM, M) for each cycle of the pair of consecutive cycles, processing the sets of

O

Slevel values to obtain a difference signal and correlating the set of difference 0 values (Dm) with square wave correlation signals (Kp, Kq) having a phase difference of O 10 900 to provide two sets of correlated values Q).

O

0 The square wave correlation signals (Kp, Kq) have the same frequency as the modulating signal, that is 1800Hz. By using two correlation signals in this way, slight phase variations in the modulation signal, of the type described with reference to Fig.8, will not prevent demodulation of a cycle of the power signal 110 including modulation signals.

The sets of correlated values Q) are summed to provide a summed value.

The summed value is used by the decoder 914 (ref. Fig. 9A) to identify the symbol-type associated with the difference value.

As depicted in Fig.lOC and Fig.lOD, in a base-2 system, the magnitude of the difference signals, and thus the respective summed values, will be different for different symbols. Thus, the magnitude of the summed value is used by the decoder 914 to decode different symbols represented by pairs of modulation signals.

In view of the above, the processing of a pair of cycles 206 of the power signal 110 to extract data contained in modulation signals applied thereto and representing symbols of a base-2 symbol set, may be summarised as follows: For each pair of corresponding time-frames, do the following: Calculate input M Calculate input OM Calculate Dm M Om Correlate Dm with Kp to give P Correlate Dm with Kq to give Q WO 2006/069420 PCT/AU2005/001978 -27-

O

O Calculate S P Q 0 Then: If S is positive then symbol= 0 0 Else If S is negative then symbol 1 End if Again, in the above sequence, Kp and Kq are square waves of frequency 1800Hz Sand magnitude 1 or Kp and Kq are shifted 900 from each other. So to correlate Dm O 10 with Kp, Dm is multiplied by either 1 or -1 according to Kp.

0 With reference to Fig. 11, in one embodiment, decoding is started one cycle after detecting the first modulation signal of the first cycle of a pair of cycles including modulation signals. The detection of the first modulation signal of the first cycle may be accomplished by way of any suitable means.

In embodiments that include a "start pulse" of the type described previously, the first modulation signal of the first cycle of a pair of cycles will have a higher magnitude.

Thus, the sum of the six summed values for the first time-frame of the first cycle of a pair of cycles of the power signal will be significant even though, at that stage, it will not be the difference of two modulation signals.

Thus, in the present case the first "symbol" of the first cycle of a pair of cycles of the modulated power signal 110 is used for synchronising the decoder 914 to a pair of cycles including modulation signals.

In the embodiment illustrated in Fig.9A, synchronisation of the decoder 914 is controlled by control signals 920 provided to the controller 910 by the cycle-pair detector 900. To generate the control signals 920, the cycle-pair detector 900 sums the set of sensed values 918 for the first time-frame of each cycle of the power signal and calculates a respective summed value as ISx\, where: x is a cycle identifier of cycles of a pair of cycles (for example, x=l, or and identifies the first time-frame of the cycle x.

In the present case are each 16 bit values obtained by summing sixteen 12 bit values from the ADC 906 under the control of the controller 910.

As depicted in Fig. 1, if ISI is the greater of IS 1 1 1 and IS211 and if ISI Sthresh then a start flag (Fstart) is set to identify the first cycle of a pair of cycles including WO 2006/069420 PCT/AU2005/001978 -28-

O

0 modulation signals. Then at the first time-frame in the next cycle of the power signal 0 (that is, the next 20ms cycle) a second flag (Fvalid) is set to indicate that decoding can Sstart.

O Until a valid start symbol is received, the only processing performed by the cycle-pair detector 900 is for the first symbol. In the example, this processing is conducted every 20ms because no synchronisation to a 40ms group (that is, two cycles) can be made until this valid symbol is received.

O

In summary then, and with reference to Fig. 11:

O

Before a valid start symbol is received, flag F 40 is not used and flags Fstart O 10 and Fvalid 0. Dm is only processed for the first symbol in every

O

SWhen Sthresh set Fstart 1 If Fstart 1 and ISI Sth for first symbol position then set Fvalid 1 and

F

40 1. If IS Sthresh then Fstart 0.

F

40 is toggled between 0 and 1 at every positive zero crossing while Fvalid =1.

While Fvalid 1, only process Dm for symbols when F 40 =1.

S IS must be greater than Sthresh for a symbol to be received. Sthresh is a threshold magnitude value.

While Fvalid 1, if a symbol is not received then the received data is invalid and flag Fvalid is reset to 0.

A message is received when the correct address and CRC is received.

It will be appreciated that although the foregoing description relates to an embodiment in which a pair of cycles including modulation signals in corresponding time-frames of a first cycle and a second cycle of a cycle pair, in other embodiments, both cycles of a cycle pair need not include modulation signals. For example, Fig.12 and Fig.12A depict an example of the demodulation of a pair of cycles of a power signal in which only one cycle of the pair includes modulation signals.

In terms of the application of a system according to an embodiment of the invention, the data sent over the power distribution network 102 (ref. Fig.l) will vary according to the application of the system.

For example, in an application in which data is communicated to effect supply management, perhaps during times of peak demand, the data may include a command to WO 2006/069420 PCT/AU2005/001978 -29-

O

O isolate particular appliances, or consumer devices, from the power distribution network, C'i to facilitate load shedding.

SIn this respect, Fig. 13 depicts an example system block diagram of a system sO 1300 including different sub-systems for various applications, including a meter reading M 5 subsystem 1302, an intelligent air-conditioning control subsystem 1304, load shedding subsystem 1306, demand side supply management subsystem 1308, and inter-device data cormmunication subsystem 1310.

SThe illustrated sub-systems are illustrated for purpose of providing examples of 0 different applications. Each sub-system may include a standalone receiver of the type O 10 described earlier, or a transceiver that includes a receiver and a transmitter (again, of the 0, type described previously). In this respect, Fig. 14 depicts a schematic diagram of an embodiment of a transceiver 1400.

It will be appreciated that a system according to present invention need not include all of the illustrated sub-systems, nor need it be limited to the examples illustrated. Indeed, it is envisaged that the present invention will find application in a broad range of different applications in which data communication over a power distribution network may be deployed, either uni-directionally or bi-directionally.

Indeed, as is evident from Fig. 13, a system according to the present invention may support uni-directional, or bi-directional, data communication. For example, subsystem 1302 is an example of an embodiment of the present invention that employs a bidirectional communication, whereas subsystem 1304 is an example of a subsystem that employs uni-directional data communication. In either case, data will be commnunicated in "packets" comprising multiple bytes. In a base-4 system each byte is grouped into words encoded as base-4 symbols. Thus, a gateway may include a receiver 108, a transmitter 105, or a transceiver 1400 (ref. Fig. 14) in the form of a combination of a receiver 108 and a transmitter 105.

In a bidirectional system, the sub-systems typically operate in a distributed configuration whereby a master controller (shown as gateway 1312) controls data communications to the receivers of the different sub-systems. A system that uses a gateway 1312 also permits response signals from those sub-systems that include a transmitter. In such a system, each sub-systemn may only respond to requests originating from the gateway 1312.

WO 2006/069420 PCT/AU2005/001978 o Packets sent from the gateway 1312 to a sub-system will typically include data instructing the sub-system as to what type of operation is required and how to interpret Sany additional data bytes in the packet. On the other hand, packets sent from a sub- O system to the gateway 1312 will typically include data that acknowledges received commands, and/or sends requested data to the gateway 1312.

Although a response will often be required from a sub-system to verify that the 0" data was received, a gateway 1312 can also operate in broadcast, or retransmit mode in o which case no reply is required from a sub-system.

SWhere a sub-system does provide a response packet to the gateway, the reply O 10 packet will typically be used to acknowledge the receipt of a gateway packet; provide response data to the gateway; and poll customer inputs and other events detected from devices In an embodiment, each packet includes an even number of bytes coupled into words. An example packet structure is as follows: a one byte sequence number for transaction processing purposes; a one byte command supporting predefined command codes identifying the type of command to be carried out; data bytes: even number of data bytes associated with the command; a two byte customer address interpreted at the gateway which translates the address from open standards supporting AMI, AMR, substation and demand response international protocols; including embedded command, location and addresses within an Internet Protocol Version 6 framework allowing for 128bit addressing; a one, or two, byte cyclic redundancy check (CRC8).

In a base-4 system, all of the above data will be encoded as base-4 symbols or Data words are converted to base-4 by taking two bits at a time starting from the highest bit.

In a system that includes plural sub-systems, each of which may be associated with a different customer, the gateway 1312 may use a customer device address to communicate with specific sub-systems. However, a sub-system will also typically echo its own address to the gateway 1312.

WO 2006/069420 PCT/AU2005/001978 -31 Table 5 includes example of commands that may sent to a sub-system that includes a "power-on-line relay". Such a relay is a single-channel, single phase receiver that receives power signals including modulation signals and decodes the instructions for controlling a device connected to the relay. Each command includes an associated command number.

TABLE FUNCTION COMMAND NUMBER COMMAND (DECIMAL) NUMBER (BASE-4) CLOSE RELAY 0 0 OPEN RELAY 1 1 CLOSE RELAY 2 2 OPEN RELAY 3 3 READ METER 4 READ METER 5 11 Table 6 includes an example structure of a data message for communication to sub-system at address "12" instructing that sub-system to "Close relay 1 at address 12".

TABLE 6 Instruction: "Close relay 1 at address 12" FUNCTION PACKET DATA PACKET DATA (Decimal) (BASE-4) SEQUENCE 43 223

NUMBER

COMMAND 0 0000

NUMBER

ADDRESS 12 0030 DATA BYTES 00 0000 CRC16 12740 03013010 As is evident from Table 6, the resultant message is:"0223 0000 0030 0000 0301 3010" (that is, 3 words, duration 120mS).

WO 2006/069420 PCT/AU2005/001978 -32- Table 7 includes an example structure of a reply message from the receiver at address "12" in acknowledging reception of the message of Table TABLE 7 Reply Message from device at address 12 FUNCTION PACKET DATA PACKET DATA (Decimal) (BASE-4) SEQUENCE 43 223

NUMBER

ADDRESS 12 0030 Thus, the reply Message 0223 00304 (1 word, duration Table 8 includes an example structure of a data message for communication to receiver at address "234" instructing that receiver to "Read meter 1 from address 234" TABLE 8 FUNCTION PACKET DATA (Decimal) PACKET DATA (BASE-4) START NUMBER 0 SEQUENCE 62 332

NUMBER

COMMAND 4 0010

NUMBER

CUSTOMER 234 3222

ADDRESS

DATA BYTES 0 0000 CRC16 0202 2323 Table 9 includes an example structure of a reply from the receiver at address "234" in response to the message at Table 8.

WO 2006/069420 PCT/AU2005/001978 -33

O

O TABLE 9 o Reply Message from device at address 12 FUNCTION PACKET DATA PACKET DATA o (Decimal) (BASE-4) START SYMBOL 0 O SEQUENCE 62 332

NUMBER

COMMAND 4 0010

O

_NUMBER

I

n CUSTOMER 234 3222

O

O

ADDRESS

REPLY DATA 624536 00212013 2120

BYTES

CRC16 25648 1210 0300 If an instruction is sent and a reply not received then the instruction message has been corrupted. Corruption can be due to noise on the power system or to a collision with another message. If a reply is not received then the command needs to be retransmitted. In such a case, the sender needs to wait until the replier has had time to reply. The type of command sent will determine the expected length of reply so that repeated collisions do not occur the wait time before retransmission needs to be randomly variable in each unit, but within limits. The wait time will be typically be in increments of 160ms and will be between 160 and 4000ms.

In one application, a system according to an embodiment of the invention may use an instruction set that conforms to the "Contact ID" security standard. In such an embodiment, codes are translated by the gateway 1312 and either sent, or received, as a three-digit number command which may be transmitted as a local one byte command.

Examples of suitable three-digit codes are provided in Fig.14. The gateway acts as a filter of local commands by decoding addresses sent via radio or internet. These are typically by transformer address or network location. Each gateway may have multiple system addresses depending upon which database is active.

In such an embodiment, sub-systems respond to commands for on/off and the data (for example, meter data) is attached to command responses. The gateway 1312 WO 2006/069420 PCT/AU2005/001978 -34-

O

can also support open protocols and vendor protocols for automation and metering by O translating to a simple one-byte contactID code for use, for example, with security Ssystems.

O Again, it is expected that the present invention will be applicable to a broad range of applications. Examples of services which may be utilise this unique remote ripple control system including, demand-side management, energy efficient equipment, electricity load management, electricity gas, and water metering, internet remote control services, energy automation services, telecomnunnications, broadband over power line control, security products and services including homeland security, maintenance and O 10 installation services, and electricity and emissions trading.

0 Cl For example, in one application, the gateway 1312 may be is used to monitor energy usage in real time to give both an energy supplier and a customer far greater control over energy use. In such an application, sub-system appliances may communicate with the gateway 1312 wirelessly or via the power lines.

In another application, a customer may be able to access the gateway 1312, using a computer terminal 1314 communicatively coupled to the gateway 1312 via a communications network 1316, to operate, for example, an air conditioner thermostat remotely via the gateway. Such an application may also enable remote control of air conditioning loads during periods of peak energy usage by responding to modulated power signals from the substation 104.

A gateway 1312 may also allow the monitoring of electricity used during peak periods and provide the ability to achieve dynamic metering from existing meters. Other examples of services which may utilise the present invention include: Demand-side Management; Energy efficient equipment; Electricity Load Management; Electricity Gas, and Water metering; Internet remote control services; Energy automation services; Telecommunications; Broadband over Powerline control; Security products and services including homeland security; WO 2006/069420 PCT/AU2005/001978

O

O Maintenance and installation services; and O Electricity and Emissions Trading.

U, A gateway will typically translate open standards to bridge devices, appliances, O and meters. Typically messages may be translated into IPV6 the internet version 6 address structure in order to handle mass applications. Each gateway has range of IPV6 equivalent to each state of each device and meter. As will be appreciated, IPV6 has 128 bit addressing instead of the 32 bits used in IPV4 which is currently limited by standard 0 internet. IPV6 is also. more secure and the lower order bits are used to address the subsystems downstream of the gateway 1312 while the higher order bits are used to O 10 identify a specific gateway 1312.

A gateway may also be used as a protocol bridge between ranges of automation devices. For example, in one application, the gateway polls meter information and presents the data in modbus format for interfacing into building management systems.

Finally, it will be understood that there may be other variations and modifications to the configurations described herein that are also within the scope of the present invention.

Claims (41)

1. A method of sending data over a power distribution network carrying an o alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the method including: defining one or more time-frames in each cycle of a pair of cycles of the power 0- signal, each time-frame of the first cycle of the pair of cycles having a corresponding time-frame in the second cycle to provide a pair of corresponding time-frames; and applying a modulation signal to at least one time-frame of each pair of O 10 corresponding time-frames to provide, over a continuum of time values of each time- 0, frame of a pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.

2. A method according to claim 1 wherein a modulation signal is applied to each time-frame of a pair of corresponding time-frames to provide, relative to a reference common to each time-frame of a pair of corresponding time-frames, a phase difference between the respective modulation signals.

3. A method according to claim 2 wherein the phase difference is about 180 degrees.

4. A method according to claim 3 wherein the phase difference is such that the modulation signals of a pair coincide time-wise over at least an extent relative to the common reference. A method according to claim 1 wherein each symbol-type is represented by a pair of modulation signals of a respective pair of corresponding time-frames, and wherein, for each symbol-type, the modulation signal of the first cycle has a different time-wise location with respect to a respective time-frame.

6. A method according to claim 1 wherein the pair of cycles are consecutive cycles. WO 2006/069420 PCT/AU2005/001978 -37- 0 O

7. A method according to claim 1 where the pair of cycles are separated by one or O more other cycles. O

8. A method according to claim 1 wherein each modulation signal is a single cycle of a periodic signal. 0

9. A method according to claim 8 wherein the frequency of the modulation signal 0 is in the range of four to eighty times greater than the frequency of the power signal. O 10 10. A method according to claim 2 wherein the modulation signals of a pair of 3l corresponding time-frames are spaced apart time-wise relative to a reference common to each time-frame of the pair of corresponding time-frames.

11. A method according to claim 8 wherein a time-frame has a width that is an integer multiple of the duration of a half-cycle of the modulation signal, the integer multiple being the same as, or greater than, the number of symbol-types in the symbol set, and wherein the modulation signals for different symbol-types are located in a different position within a time-frame.

12. A method according to claim 2 wherein each time-frame is divided into plural time-slots, each time-slot having a width corresponding to the duration of a half-cycle of the modulation signal, and wherein for each symbol-type the modulation signals are located in a different pair of time-slots.

13. A method according to claim 2 wherein the symbol-set is a binary symbol-set and wherein each symbol-type is represented using a pair of modulation signals, each modulation signal being located in a respective time-frame of a pair of corresponding time-frames.

14. A method according to claim 1 wherein each pair of cycles of the power signal includes eight pairs of corresponding time-frames, each pair including at least one time- frame having a modulation signal. WO 2006/069420 PCT/AU2005/001978 -38- O O U 15. A method according to claim 1 wherein each time-frame includes plural time- Sslots, and wherein different consecutive time slots of a time frame are associated with a O particular symbol-type so that the application of a modulation signal for a symbol includes applying the modulation signal to the power signal within an associated pair of time slots. 0

16. A method according to claim 1 wherein the data is received by a receiver which 0 has an ability to determine dynamically whether a received communication has been O 10 modulated by the, or other, modulating scheme, and to process the communication 0, accordingly.

17. A method according to claim 16 wherein the other modulating scheme includes conventional ripple control data communication.

18. A transmitter for sending data over a power distribution network carrying an alternating current periodic power signal, the data including a sequence of symbols from a predefined symbol-set, the transmitter including: timing means for defining one or more time-frames in each cycle of a pair of cycles of the power signal, each time-frame of the first cycle of the pair of cycles having a corresponding time-frame in the second cycle so as to provide a pair of corresponding time-frames; and signal injector means for applying a modulation signal to at least one time-frame of each pair of corresponding time-frames to provide, over a continuum of time values of each time-frame of a pair of corresponding time-frames, a signal difference therebetween that is indicative of a symbol-type of the symbol sequence.

19. A transmitter according to claim 1 wherein the signal injector is controlled by the timing means to apply a modulation signal each time-frame of a pair of corresponding time-frames to thereby provide, relative to a reference common to each time-frame of a pair of corresponding time-frames, a phase difference between the modulation signals of that pair. WO 2006/069420 PCT/AU2005/001978 -39- O O kN 0 20. A transmitter according to claim 18 wherein the phase difference is about 180 Sdegrees. O n 5 21. A transmitter according to claim 20 wherein the phase difference is such that the modulation signals of that pair coincide time-wise over at least an extent relative to the common reference. O O

22. A transmitter according to claim 18 wherein for each symbol-type represented O 10 by a pair of modulation signals, the modulation signal of the first cycle has a different C, time-wise location with respect to a respective time-frame.

23. A transmitter according to claim 18 wherein the pair of cycles are consecutive cycles.

24. A transmitter according to claim 18 where the pair of cycles are separated by one or more other cycles. A transmitter according to claim 18 wherein each modulation signal is a single cycle of a periodic signal.

26. A transmitter according to claim 25 wherein the frequency of the modulation signal is in the range of four to eighty times greater than the frequency of the power signal.

27. A transmitter according to claim 19 wherein the modulation signals of a pair of corresponding time-frames are spaced apart time-wise relative to a reference common to each time-frame of the pair of corresponding time-frames.

28. A transmitter according to claim 25 wherein a time-frame has a width that is an integer multiple of the duration of a half-cycle of the modulation signal, the integer multiple being the same as, or greater than, the number of symbol-types in the symbol WO 2006/069420 PCT/AU2005/001978 40 o set, and wherein the modulation signals for different symbol-types are located in a O different position within a time-frame. O 29. A transmitter according to claim 18 wherein each time-frame is divided into plural time-slots, each time-slot having a width corresponding to the duration of a half- cycle of the modulation signal, and wherein the modulation signals for different 0 symbol-types are located in a different pair of time-slots. 0 A transmitter according to claim 19 wherein the symbol-set is a binary symbol- O 10 set and wherein each symbol-type is represented using a pair of modulation signals, each modulation signal being located in a respective time-frame of a pair of corresponding time-frames.

31. A transmitter according to claim 18 wherein each pair of cycles of the power signal includes eight pairs of corresponding time-frames, each pair including at least one time-frame having a modulation signal.

32. A transmitter according to claim 18 wherein each time-frame includes plural time-slots, and wherein different consecutive time slots of a time frame are associated with a particular symbol so that the application of a modulation signal for a symbol includes applying the modulation signal to the power signal within an associated pair of time slot.

33. A method of receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the method including: detecting a pair of cycles of the power signal including a modulation signal in at least one time frame of corresponding time-frames of a first cycle and a second cycle of the pair of cycles; sensing, for each time-frame of a pair of corresponding time-frames of the first cycle and the second cycle, a set of signal level values; WO 2006/069420 PCT/AU2005/001978 -41- 0 O processing the sensed level values for corresponding time-frames of the pair of cycles to generate a difference signal; and decoding the symbol type associated with the difference signal. 0

34. A method according to claim 33 wherein the detecting of a pair of cycles of the power signal including one or more modulation signals includes detecting the first cycle of a pair of cycles of the power signal including modulation signals. 0 A method according to claim 33 wherein each time-frame has a predefined O 10 positional relationship with a respective cycle of the power signal so that each time- 0 frame of a pair of corresponding time-frame may be identified by the receiver based on the predefined relationship.

36. A method according to claim 35 wherein the identifying of one or more corresponding time-frames in each cycle of a pair of cycles includes detecting a zero crossing event of the first cycle of a pair of cycles; resetting a clock counter on detection of the zero crossing event; and for predetermined counts of the clock counter, identifying the one or more corresponding time-frames of each cycle of the pair.

37. A method according to claim 33 wherein the processing of the difference signal to identify a symbol type associated with the difference signal includes: correlating the difference signal with an in-phase signal and a quadrature signal having substantially the same fri-equency as the modulation signal Lo provide, for each pair of corresponding time-frames, a first and second set of correlated values; summing the first set and the second set of correlated values to provide a summed value; and decoding the symbol type associated with the summed value.

38. A receiver for receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the receiver including: WO 2006/069420 PCT/AU2005/001978 -42- O O a detector detecting a pair of cycles of the power signal including a modulation Cl signal in at least one time frame of corresponding time-frames of a first cycle and a U second cycle of the pair of cycles; and a signal processor sensing, for each time-frame of a pair of corresponding time- M 5 frames of the first cycle and the second cycle, a set of signal level values, processing the sensed level values for corresponding time-frames of the pair of cycles to generate a difference signal and decoding the symbol type associated with the difference signal. 0 S39. A receiver according to claim 38 wherein the detector includes a means for detecting the first cycle of a pair of cycles of the power signal including modulation O signals. A receiver according to claim 38 wherein the signal processor includes timing means for identifying the time-frames in each cycle of the pair of cycles of the power signal based on a predefined positional relationship existing between the time-frames and a respective cycle of the power signal.

41. A receiver according to claim 39 wherein the timing means for identifying the time-frames in each cycle of a pair of cycles includes: a zero-crossing detector for detecting zero crossing events of one, or each, cycle of the pair of cycles; and a clock counter, responsive to the detection of zero-crossing events to generate counts that identify the time-frames of a cycle of the pair of cycles.

42. A receiver according to claim 41 wherein the timing means further includes a means for reducing jitter in the zero crossing detection.

43. A receiver according to claim 42 wherein the means for reducing jitter includes a phase locked loop. WO 2006/069420 PCT/AU2005/001978 -43 O O 44. A receiver according to claim 37 wherein the signal processor includes a decoder for decoding a symbol type associated with the difference signal, the decoder Sincluding: dual correlators for respectively correlating the difference signal with an in- 5 phase signal and a quadrature signal having substantially the same frequency as the modulation signal to provide, for each pair of corresponding time-frames, a first and second set of correlated values; a summer for summing the first set and the second set of correlated values to Sprovide a summed value; and O 10 an analyser for analysing characteristics of the summed value to identify the 0 symbol type associated with the summed value. A transceiver for sending and receiving data over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined set of symbol-types, the transceiver including: a transmitter according to claim 1; and a receiver according to claim 37.

46. A transceiver according to claim 45, further including an interface for interfacing with a communications network external to the power distribution network.

47. A transceiver according to claim 46 wherein the communication network includes one or more of: a network for packet based data communication; a public switched telephone network; or a public land mobile network;

48. A transmitter for sending data over a power distribution network carrying an alternating current periodic power signal, the data including a sequence of symbols from a predefined symbol-set, the transmitter including: WO 2006/069420 PCT/AU2005/001978 -44- O O timing means for defining one or more time-frames in each cycle of a pair of o cycles of the power signal so that each time-frame of a first cycle of the pair of cycles Shas a corresponding time-frame in a second cycle of the cycle pair; and O a signal injector means for applying, in a pair of corresponding time-frames, to the first cycle and the second cycle, a modulation signal to form a pair of modulation signals representing a symbol-type of a symbol in the sequence; 7- wherein relative to a reference common to each pair of corresponding time frames, paired modulation signals of those time-frames have a phase-difference so that the modulation signals of a pair of modulation signals coincide time-wise over at least O 10 an extent of each modulation signal of that pair.

49. A transmitter according to claim 48 wherein the phase difference is about 180 degrees.

50. A receiver for receiving data sent over a power distribution network carrying an alternating current power signal, the data including a sequence of symbols from a predefined symbol-set, the receiver including: a detector detecting a pair of cycles of the power signal, each cycle of the pair including modulation signals located in corresponding time-frames to provide a pair of modulation signals which, relative to a reference common to each of the corresponding time-frames, have a phase-difference so that each modulation signal pair coincide time- wise over at least an extent; and a processor processing each detected pair of cycles of the power signal to provide a difference value for each modulation signal pair and using each difference value to identify the symbol-type represented by each pair of modulation signals.

51. A receiver according to claim 50 wherein the phase difference is about 180 degrees.

52. A method of sending data communication over a power distribution network carrying an alternating current power signal, the method substantially as hereinbefore described with reference to the accompanying figures. WO 2006/069420 PCT/AU2005/001978 O O

53. A transmitter for sending data communication over a power distribution network Scarrying an alternating current power signal, the transmitter substantially as o hereinbefore described with reference to the accompanying figures.

54. A receiver for receiving data communication sent over a power distribution network carrying an alternating current power signal, the receiver substantially as O Shereinbefore described with reference to the accompanying figures. 0 (N