WO2006069356A2 - A method, apparatus, and system for partial memory refresh - Google Patents

A method, apparatus, and system for partial memory refresh Download PDF

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Publication number
WO2006069356A2
WO2006069356A2 PCT/US2005/046943 US2005046943W WO2006069356A2 WO 2006069356 A2 WO2006069356 A2 WO 2006069356A2 US 2005046943 W US2005046943 W US 2005046943W WO 2006069356 A2 WO2006069356 A2 WO 2006069356A2
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WIPO (PCT)
Prior art keywords
refresh
value
memory
register
memory device
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Ceased
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PCT/US2005/046943
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French (fr)
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WO2006069356A3 (en
Inventor
Sandeep Jain
Animesh Mishra
John Halbert
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Intel Corp
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Intel Corp
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Priority to JP2007547059A priority Critical patent/JP2008524774A/en
Publication of WO2006069356A2 publication Critical patent/WO2006069356A2/en
Publication of WO2006069356A3 publication Critical patent/WO2006069356A3/en
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622—Partial refresh of memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Definitions

  • the present invention relates to Dynamic Random Access Memory (DRAM), and more specifically to DRAM refresh schemes.
  • DRAM Dynamic Data Rate
  • a memory controller queues auto-refreshes to the memory device. During normal operation mode, the controller schedules refreshes in bursts to maximize performance.
  • the DRAM maintains an internal refresh counter that tracks bank rows that get refreshed.
  • the DRAM When each auto-refresh command is received, the DRAM will either increment or decrement the refresh counter.
  • Partial array self refresh (PASR) DRAM is capable of refreshing 1 A, Vi, or 3 A of a bank of memory. This allows for some reduction in refresh power by reducing the number of memory locations to be refreshed during each refresh cycle. However, PASR DRAM does not allow a refresh start or end location to be specified.
  • Figure 1 is an illustration of a block diagram of a memory device according to one embodiment.
  • Figure 2 is a flow diagram illustrating a method according to one embodiment.
  • Figure 3 is a flow diagram illustrating a method according to one embodiment.
  • Figure 4 is a flow diagram illustrating a method according to one embodiment.
  • Figure 5 is an illustration of a block diagram of a memory device coupled to a memory controller device according to one embodiment.
  • Figure 6 is a timing diagram according to one embodiment.
  • Figure 7 is a timing diagram according to one embodiment.
  • Figure 8 is a system block diagram according to one embodiment.
  • Embodiments of the present invention concern a partial refresh scheme for
  • DRAM which includes specifying at least a refresh start value and a fractional
  • the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns, the memory cells may be organized in any of a number of rows and columns
  • Figure 1 is a simplified block diagram of a memory device according to one
  • the memory device is made up, at least in
  • control unit which may include a refresh control unit (RCU) (105),
  • RCU refresh control unit
  • the memory device also includes
  • interface or command bus (102)
  • interface for reading from or writing to
  • Refresh start/end registers (106) may store refresh values, including
  • start/end register indicate a contiguous block of memory in a memory bank array
  • a refresh start value may indicate an address in memory where a refresh operation will begin.
  • refresh end value may indicate an address in memory where a refresh operation
  • a refresh end value may indicate a number of rows in memory that are to be refreshed during a refresh cycle.
  • Each refresh start/end register (106) may correspond to one memory bank
  • partial array self refresh (PASR) DRAM may include
  • end location for the refresh may be determined based on the fractional portion of memory that is to be refreshed during a partial refresh. For example, when a
  • the refresh cycle will begin at the specified location and continue until 1 A
  • the refresh start/end registers (106) are readable and writable data storage
  • the refresh start/end registers may be implemented as mode registers
  • DRAM dynamic random access memory
  • refresh volatile or non-volatile memory
  • RCM counter memory
  • the refresh start/ end registers may be written to by an external device (not shown) or by control unit (104).
  • Refresh values may be programmed by an external device (not shown) or by control unit (104).
  • the refresh values are received at I/O buffers
  • the latches are coupled to the refresh start/end registers (106).
  • the values in the refresh start/end registers (106) are set based upon the data received at the I/O
  • refresh values may be written to the refresh start /end
  • the refresh values may
  • both a refresh may be stored on a per-bank basis over the address bus. For example, both a refresh
  • refresh values for all banks may be programmed
  • the refresh values to be stored in each of the refresh start /end registers may be sent
  • the data write path may be
  • the refresh start value from the refresh start/end register may be
  • the refresh counter indicates the address of the next row that is to be refreshed during a refresh cycle. Thus, the next row to be
  • the refresh counter may be incremented or
  • predetermined location may be refreshed in one or more banks of memory.
  • the refresh start/end registers (106) are readable as well. In one
  • no new value is placed in the refresh start/end register, and the initial refresh value that was written to the refresh start /end register may be
  • the refresh values may be read from the refresh start/end register over a
  • Bus (142) may be an address bus or a data bus. In the case where bus
  • (142) is an address bus, the address bus must be a bi-directional bus. Where bus
  • the refresh values may be multiplexed on the read data path to
  • FIGS. 2 through 4 are flowcharts illustrating methods according embodiments of the present invention. Although the following operations may be performed.
  • FIG. 2 is a flowchart which illustrates one embodiment of a method by
  • a refresh start value is specified.
  • a refresh start value is specified.
  • refresh end value may optionally be specified.
  • the refresh start and end values may be stored in mode registers inside
  • Refresh start and end values may be
  • FIG. 3 is a flowchart which illustrates one embodiment of a method by
  • a refresh write command is received by a
  • the refresh write command may be
  • the refresh value may include only a refresh start value, only a refresh end
  • the refresh value may be sent to the memory device by a controller or by another device.
  • the refresh value may be sent to the memory device by a controller or by another device.
  • refresh values may be programmed over an address bus. In this embodiment, it is
  • the refresh values may be sent over a data bus.
  • values for all banks may be sent in one burst write operation.
  • the received refresh value is stored in a register, as illustrated in block 306.
  • the register may be a mode register, or another register in the memory device.
  • the received refresh value may alternately be stored in a
  • the refresh value may then be read from the register and stored in a
  • the refresh counter contains the location
  • the refresh control unit the first row to be refreshed is indicated by the value in the refresh counter, which is the refresh start value.
  • the refresh cycle continues until the refresh end value is
  • Figure 4 is a flowchart which illustrates one embodiment of a method by
  • an external device such as a memory controller device
  • a refresh read command is received by a memory device, as shown by
  • the refresh read command may be issued to the memory device by a
  • a value is read from the refresh counter, as shown by block 404.
  • the value read from the refresh counter indicates the next location in memory that is
  • the counter may be stored in a register.
  • the value from the refresh counter may be stored in the refresh start/end register.
  • the value may be
  • the value may be sent to an external device, as illustrated by block 408.
  • an external device as illustrated by block 408.
  • the value may be sent to a memory controller device over a data bus
  • Figure 5 is a block diagram which illustrates the interconnection between a
  • Memory controller device (502) is coupled to memory device (504).
  • the memory controller device (502) may issue refresh write and /or refresh
  • refresh values may be sent
  • refresh values may be sent from the memory device (504) to the memory
  • controller device (502) in a burst data transfer over a data bus (508).
  • Figure 6 is a timing diagram illustrating a refresh write command
  • the memory device receives a refresh write
  • DQS strobe
  • Figure 7 is a timing diagram illustrating a refresh read command according
  • the memory device receives a refresh read command (702).
  • refresh values (D0:7) may be sent on the data
  • Figure 8 illustrates one embodiment of a system according to the present
  • the system (800) includes at least a processor or CPU (802), memory
  • the system may also include a network port or interface (820), and may be
  • I/O controller hub (818) may be coupled to the memory controller device (806) by
  • the I/O controller hub (818) may be coupled to a network port (820),
  • the I/O controller hub (818) may also
  • the CPU (802) may execute instructions causing refresh
  • the refresh cycle may begin at the location in memory specified by the refresh
  • start value and may end at the location specified by the refresh end value
  • the CPU (802) may also execute instructions causing the refresh start values
  • the system (800) may vary.
  • the CPU (802) may be any one of a
  • CPU central processing unit
  • memory devices (810) could be any of a variety of types of memory, including DRAM or another type of memory that requires refresh,
  • memory controller device (806) may be any device with an appropriate
  • Embodiments of the system may also

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

Description

A METHOD, APPARATUS, AND SYSTEM FOR ACTIVE REFRESH MANAGEMENT
BACKGROUND OF THE INVENTION [0001] The present invention relates to Dynamic Random Access Memory (DRAM), and more specifically to DRAM refresh schemes. [0002] In Dynamic Data Rate (DDR) memory systems, a memory controller queues auto-refreshes to the memory device. During normal operation mode, the controller schedules refreshes in bursts to maximize performance. The DRAM maintains an internal refresh counter that tracks bank rows that get refreshed.
When each auto-refresh command is received, the DRAM will either increment or decrement the refresh counter.
[0003] In an auto-refresh scheme, the memory controller does not know the exact addresses of the memory locations that are being refreshed. Thus, it is difficult to implement a sophisticated refresh management scheme to optimize power vs. performance.
[0004] With increased DRAM densities, the number of total pages to be refreshed increases substantially and, as a result, the overall refresh operation consumes an increasing amount of power. Because the controller must refresh all memory locations, whether or not the location is used for data, much power is wasted on unnecessary refresh cycles.
[0005] Partial array self refresh (PASR) DRAM is capable of refreshing 1A, Vi, or 3A of a bank of memory. This allows for some reduction in refresh power by reducing the number of memory locations to be refreshed during each refresh cycle. However, PASR DRAM does not allow a refresh start or end location to be specified.
[0006] As DRAM densities continue to increase, additional power can be saved by implementing more sophisticated refresh schemes BRIEF DESCRIPTION OF THE DRAWINGS
[0007] A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which: [0008] Figure 1 is an illustration of a block diagram of a memory device according to one embodiment.
[0009] Figure 2 is a flow diagram illustrating a method according to one embodiment.
[0010] Figure 3 is a flow diagram illustrating a method according to one embodiment.
[0011] Figure 4 is a flow diagram illustrating a method according to one embodiment.
[0012] Figure 5 is an illustration of a block diagram of a memory device coupled to a memory controller device according to one embodiment. [0013] Figure 6 is a timing diagram according to one embodiment.
[0014] Figure 7 is a timing diagram according to one embodiment.
[0015] Figure 8 is a system block diagram according to one embodiment.
DETAILED DESCRIPTION
[0016] In the following description, for purposes of explanation, numerous details
are set forth in order to provide a thorough understanding of embodiments of the
present invention. However, it will be apparent to one skilled in the art that these
specific details are not required in order to practice the present invention.
[0017] Embodiments of the present invention concern a partial refresh scheme for
DRAM which includes specifying at least a refresh start value and a fractional
portion of memory, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the
amount of power consumed during refresh. Although the following discussion
centers on DRAM devices, it will be understood by those skilled in the art that the
present invention as hereinafter claimed may be practiced in support of any type
of memory device having cells in need of being refreshed or otherwise maintained
at regular intervals in order to preserve their contents. It will also be understood
by those skilled in the art that although the following discussion centers on
memory devices in which memory cells are organized in two dimensional arrays
of rows and columns, the memory cells may be organized in any of a number of
ways, including into banks and with or without interleaving, arrays of more than two dimensions, content-addressable memories, etc. In addition, although at least
part of the following discussion centers on memory within computer systems, it
will be understood by those skilled in the art that the present invention as hereinafter claimed may be practiced in connection with other electronic devices
or systems having memory devices.
[0018] Figure 1 is a simplified block diagram of a memory device according to one
embodiment of the present invention. The memory device is made up, at least in
part, of control unit (104), which may include a refresh control unit (RCU) (105),
one or more refresh start/end registers (106), one or more refresh counters (108),
one or more row address control and decoder logic units (110), bank control logic
(118), one or more arrays of memory cells arranged in one or more banks of
memory (114), which may include an area of memory to store refresh start/end
registers (112), sense amplifiers (116), read latches (120), multiplexers (122, 128), I/O buffers (124, 130), and write latches (126). The memory device also includes
several external interfaces, including but not limited to an external control
interface, or command bus (102), and an interface for reading from or writing to
the refresh start/end registers (142, 144). The exact arrangement and
configuration of components within the memory device may be reduced,
augmented, or otherwise altered without departing from the spirit and scope of
the present invention.
[0019] Refresh start/end registers (106) may store refresh values, including
refresh start and /or refresh end values. The refresh values stored in each refresh
start/end register indicate a contiguous block of memory in a memory bank array
(114) that is to be refreshed during a refresh cycle. For example, a refresh start value may indicate an address in memory where a refresh operation will begin. A
refresh end value may indicate an address in memory where a refresh operation
will end. Alternately, a refresh end value may indicate a number of rows in memory that are to be refreshed during a refresh cycle.
[0020] Each refresh start/end register (106) may correspond to one memory bank
array (114). For example, in an eight bank memory system, there may be eight
refresh start/end registers, or one refresh start/end register per bank.
[0021] In one embodiment, partial array self refresh (PASR) DRAM may include
readable and writable data storage elements, such as refresh start/end registers
(106) which store only refresh start values. In this embodiment, the refresh start
value indicates the address in memory where a refresh operation will begin. The
end location for the refresh may be determined based on the fractional portion of memory that is to be refreshed during a partial refresh. For example, when a
refresh start location is specified and 1A bank refresh is selected in the PASR
DRAM, the refresh cycle will begin at the specified location and continue until 1A
of the bank of memory has been refreshed.
[0022] The refresh start/end registers (106) are readable and writable data storage
elements. The refresh start/end registers may be implemented as mode registers
in a DRAM, or may be stored in volatile or non-volatile memory, such as refresh
counter memory (RCM) (112), protected memory, or other non-accessible
memory.
[0023] The refresh start/ end registers may be written to by an external device (not shown) or by control unit (104). Refresh values may be programmed by an
external device over a bus (144). The refresh values are received at I/O buffers
(130), which are coupled to multiplexers (128) and write latches (126). The write
latches are coupled to the refresh start/end registers (106). The values in the refresh start/end registers (106) are set based upon the data received at the I/O
buffers (130).
[0024] In one embodiment, refresh values may be written to the refresh start /end
registers (106) over an address bus. In this embodiment, the refresh values may
be stored on a per-bank basis over the address bus. For example, both a refresh
value and a bank may be specified when programming the refresh start/end
registers.
[0025] In another embodiment, refresh values for all banks may be programmed
in the refresh start/end registers (106) over a data bus. In this embodiment, the refresh values to be stored in each of the refresh start /end registers may be sent
over the data bus in one burst write operation. The data write path may be
optimized for timing.
[0026] After the refresh values have been programmed into the refresh start /end
registers (106), the refresh start value from the refresh start/end register may be
placed in a refresh counter (108). The refresh counter indicates the address of the next row that is to be refreshed during a refresh cycle. Thus, the next row to be
refreshed will be the row having the address indicated by the start refresh value.
Furthermore, when the next refresh cycled is initiated by the refresh control unit
(105), the refresh will begin at the memory location indicated by the refresh start
value.
[0027] After each row is refreshed, the refresh counter may be incremented or
decremented, until the refresh end value is reached. When the refresh end value
is reached, or, for PASR DRAM, when a predetermined fractional amount of the memory block (e.g. 1A, Vi, 3A, etc.) has been refreshed, the refresh cycle is complete.
In this manner, a contiguous block of memory beginning and ending at a
predetermined location may be refreshed in one or more banks of memory.
[0028] The refresh start/end registers (106) are readable as well. In one
embodiment, when a command to read a refresh start /end register is issued, the
current refresh counter value is placed in the refresh start/end register before it is
read. This allows access to the address of the next row that is to be refreshed. In
another embodiment, no new value is placed in the refresh start/end register, and the initial refresh value that was written to the refresh start /end register may be
read from the refresh start/end register.
[0029] The refresh values may be read from the refresh start/end register over a
bus (142). Bus (142) may be an address bus or a data bus. In the case where bus
(142) is an address bus, the address bus must be a bi-directional bus. Where bus
(142) is a data bus, the refresh values may be multiplexed on the read data path to
optimize the read timing path.
[0030] Figures 2 through 4 are flowcharts illustrating methods according embodiments of the present invention. Although the following operations may
be described as a sequential process, some of the operations may be performed in
parallel or concurrently. In addition, the order of the operations may be re¬
arranged without departing from the spirit of embodiments of the invention.
[0031] Figure 2 is a flowchart which illustrates one embodiment of a method by
which a specified portion of memory may be refreshed. First, as illustrated in block 202, a refresh start value is specified. Next, as illustrated in block 204, a
refresh end value may optionally be specified. In embodiments of the present
invention, the refresh start and end values may be stored in mode registers inside
a DRAM, or may be stored in memory. Refresh start and end values may be
specified for each memory bank within the DRAM. Finally, as illustrated in block
206, a contiguous block in memory is refreshed, beginning at the location
specified by the refresh start value, and optionally ending at the location specified
by the refresh end value. [0032] Figure 3 is a flowchart which illustrates one embodiment of a method by
which a refresh start value and /or a refresh end value may be written to a
memory device by an external device. A refresh write command is received by a
memory device, as shown by block 302. The refresh write command may be
issued to the memory device by a memory controller or by another device, and
may be sent over a command bus.
[0033] Next, a refresh value is received by the memory device, as shown by block
304. The refresh value may include only a refresh start value, only a refresh end
value, or both refresh start and end values. The refresh value may be sent to the memory device by a controller or by another device. In one embodiment, the
refresh values may be programmed over an address bus. In this embodiment, it
may be possible to specify a bank which corresponds to the refresh value. In another embodiment, the refresh values may be sent over a data bus. The refresh
values for all banks may be sent in one burst write operation.
[0034] The received refresh value is stored in a register, as illustrated in block 306. The register may be a mode register, or another register in the memory device. In
one embodiment, the received refresh value may alternately be stored in a
reserved memory location.
[0035] The refresh value may then be read from the register and stored in a
refresh counter, as shown by block 308. The refresh counter contains the location
of the next row in memory to be refreshed.
[0036] Finally, a refresh cycle is initiated as shown in block 310. When a refresh
cycle is initiated by the refresh control unit, the first row to be refreshed is indicated by the value in the refresh counter, which is the refresh start value. In
one embodiment, the refresh cycle continues until the refresh end value is
reached, or until a predetermined portion of memory, e.g. 1A or 1A, has been
refreshed.
[0037] Figure 4 is a flowchart which illustrates one embodiment of a method by
which an external device, such as a memory controller device, may read the
values of the refresh start value and/or the refresh end value from a memory device. A refresh read command is received by a memory device, as shown by
block 402. The refresh read command may be issued to the memory device by a
memory controller or by another device, and may be sent over a command bus.
[0038] Next, a value is read from the refresh counter, as shown by block 404. The value read from the refresh counter indicates the next location in memory that is
to be refreshed during a memory refresh cycle. The value from the refresh
counter may be stored in a register. In one embodiment, the value from the refresh counter may be stored in the refresh start/end register. The value may be
stored in another register as well, or may be stored in a location in memory.
[0039] The value is then read from the register as illustrated by block 406. Finally,
the value may be sent to an external device, as illustrated by block 408. In one
embodiment, the value may be sent to a memory controller device over a data bus
or over an address bus.
[0040] Figure 5 is a block diagram which illustrates the interconnection between a
memory device and a controller device according to one embodiment of the
present invention. Memory controller device (502) is coupled to memory device (504). The memory controller device (502) may issue refresh write and /or refresh
read commands, as described above in conjunction with Figs. 3-4. The refresh
read and refresh write commands are issued by the memory controller device
(502) and sent to the memory device (504) on a command bus (506).
[0041] Upon issuance of a refresh write command, refresh values may be sent
from the memory controller device (502) to the memory device (504) in a burst
data transfer over a data bus (508). Upon issuance of a refresh read command,
refresh values may be sent from the memory device (504) to the memory
controller device (502) in a burst data transfer over a data bus (508).
[0042] Figure 6 is a timing diagram illustrating a refresh write command
according to one embodiment. The memory device receives a refresh write
command (602), followed by a burst data transfer (604) of the refresh values (DO: 7). The refresh values are latched on the rising and falling edges of the data
strobe (DQS).
[0043] Figure 7 is a timing diagram illustrating a refresh read command according
to one embodiment. The memory device receives a refresh read command (702).
After a refresh latency period (703), refresh values (D0:7) may be sent on the data
bus.
[0044] Figure 8 illustrates one embodiment of a system according to the present
invention. The system (800) includes at least a processor or CPU (802), memory
controller device (806), I/O controller device (818), and one or more memory
devices (810). A block diagram of memory device (810) is illustrated in Figure 1. [0045] The system may also include a network port or interface (820), and may be
coupled to a wired or wireless network (830). The memory controller device (806)
is coupled to the CPU (802) by a bus (804). The memory controller device (806)
provides the CPU (802) with access to one or more memory devices (810), to
which the memory controller device (806) is coupled by a memory bus (808). An
I/O controller hub (818) may be coupled to the memory controller device (806) by
a bus (816). The I/O controller hub (818) may be coupled to a network port (820),
capable of connecting to a network (830). The I/O controller hub (818) may also
be coupled to a mass storage device (822) and non-volatile memory (824).
[0046] Together, these components form a system (800) that is capable of
supporting the execution of machine readable instructions by CPU (802), and the
storage of data, including instructions, within memory devices (810). During operation of the system, the CPU (802) may execute instructions causing refresh
start values and /or refresh end values to be written to one or more memory
devices (810). As a result, when a refresh cycle for a memory device is initiated, the refresh cycle may begin at the location in memory specified by the refresh
start value, and may end at the location specified by the refresh end value,
thereby refreshing only a predetermined portion of rows in the memory device.
The CPU (802) may also execute instructions causing the refresh start values
and /or the refresh end values to be read from one or more memory devices.
[0047] In embodiments of the present invention, the specific components within
the system (800) may vary. For example, the CPU (802) may be any one of a
variety of types of CPU, memory devices (810) could be any of a variety of types of memory, including DRAM or another type of memory that requires refresh,
and memory controller device (806) may be any device with an appropriate
interface for the memory devices (810). Embodiments of the system may also
include additional devices which are not illustrated in Figure 8, including but not
limited a graphics controller device and I/O devices.
[0048] Thus, a method, apparatus, and system for active refresh management are
disclosed. In the above description, numerous specific details are set forth.
However, it is understood that embodiments may be practiced without these
specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this
description. Embodiments have been described with reference to specific exemplary embodiments thereof. It will, however, be evident to persons having
the benefit of this disclosure that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the
embodiments described herein. The specification and drawings are, accordingly,
to be regarded in an illustrative rather than a restrictive sense.

Claims

IN THE CLAIMSWe claim:
1. A memory device comprising:
an array of memory cells; and
at least one readable and writable refresh start/end data storage element to
store a refresh start value indicating a specific point within the array of memory
cells for starting a refresh operation.
2. The memory device of claim 1, wherein the at least one readable and
writable refresh start/end data storage element is further to store a refresh end value indicating a specific point within the array of memory cells for ending a
refresh operation.
3. The memory device of claim 1, wherein the array of memory cells is
arranged in one or more banks.
4. The memory device of claim 3, wherein each bank corresponds to one
refresh start /end data storage element.
5. The memory device of claim 2, wherein the refresh start value is an address
corresponding to a location in memory where a refresh cycle begins.
6. The memory device of claim 5, wherein the refresh end value is an address
corresponding to a location in memory where the refresh cycle ends.
7. The memory device of claim 5, wherein the refresh end value is a number
corresponding to a number of locations in memory that are to be refreshed during
a refresh cycle.
8. A method comprising:
specifying a refresh start value;
specifying a refresh end value; and
refreshing a contiguous block in memory defined by the refresh start value
and the refresh end value.
9. The method of claim 8, wherein specifying a refresh start value comprises
writing to a refresh start register over an address bus.
10. The method of claim 9, wherein specifying a refresh end value comprises
writing to a refresh start/end register over an address bus.
11. The method of claim 8, wherein specifying a refresh start value comprises
writing to a refresh start /end register over a data bus.
12. The method of claim 11, wherein specifying a refresh end value comprises
writing to a refresh start/end register over a data bus.
13. The method of claim 10, where the refresh start/end register is a mode
register.
14. The method of claim 8, further comprising specifying a bank of memory.
15. The method of claim 14, wherein the contiguous block in memory defined by
the refresh start value and the refresh end value is located within the specified
bank of memory.
16. A method comprising:
receiving a refresh write command; and
receiving a refresh value.
17. The method of claim 16, wherein the refresh write command is received from
a memory controller device.
18. The method of claim 17, wherein the refresh value comprises a refresh start
value and a refresh end value.
19. The method of claim 17, wherein the refresh value comprises a refresh start
value.
20. The method of claim 17, wherein receiving a refresh value comprises
receiving the refresh value on a data bus.
21. The method of claim 17, wherein receiving a refresh value comprises
receiving the refresh value device on an address bus.
22. The method of claim 21, further comprising storing the refresh value in a
first register.
23. The method of claim 22, wherein the first register is a mode register.
24. The method of claim 22, wherein the first register resides in memory.
25. The method of claim 21, further comprising reading the refresh value from
the first register and storing the refresh value in a refresh counter.
26. The method of claim 25, further comprising initiating a refresh cycle.
27. A method comprising:
receiving a refresh read command; reading a value from a refresh counter and storing it in a register;
reading the value from the register; and
sending the value to a memory controller device.
28. The method of claim 27, wherein the refresh read command is received from
the memory controller device.
29. The method of claim 28, wherein the value indicates the next memory
location to be refreshed.
30. The method of claim 29, wherein sending the value comprises sending the
value on a data bus.
31. The method of claim 30, wherein sending the value comprises sending the
value on an address bus.
32. An apparatus comprising:
a control unit; a refresh start/end register coupled to the control unit to store a refresh start
value; and a refresh counter coupled to the refresh start/end register to increment or
decrement a row address during a refresh cycle.
33. The apparatus of claim 32, wherein the refresh start /end register is further to
store a refresh end value.
34. The apparatus of claim 32, further comprising bank control logic coupled to
the control unit.
35. The apparatus of claim 34, further comprising row address control and
decode logic coupled to the refresh counter, the bank control logic, and an array
of memory cells.
36. The apparatus of claim 35, wherein the array of memory cells comprises an
array of DRAM memory cells.
37. The apparatus of claim 34, wherein the refresh start/end register resides in
the array of memory cells.
38. An article of manufacture comprising a machine-accessible medium having
stored thereon instructions which, when executed by a machine, cause the
machine to:
specify a refresh start value;
specify a refresh end value; and
refresh a contiguous block in memory defined by the refresh start value and
the refresh end value.
39. The article according to claim 37 wherein the instructions, when executed by
the machine, further cause the machine to specify a bank of memory.
40. An article of manufacture comprising a machine-accessible medium having
stored thereon instructions which, when executed by a machine, cause the
machine to:
specify a refresh start value; specify a fractional portion of memory; and refresh a contiguous block in memory defined by the refresh start value and
the fractional portion of memory.
41. The article according to claim 40 wherein the instructions, when executed by
the machine, further cause the machine to specify a bank of memory.
42. The article according to claim 41 wherein the fractional portion of memory is
equal to 1A.
43. The article according to claim 41, wherein the fractional portion of memory
is equal to 1A.
44. A system comprising:
a processor; a memory controller device coupled to the processor, the memory controller
device capable of sending a refresh start value and a refresh end value; and
a memory device coupled to the memory controller device, the memory
device capable of receiving and storing the refresh start value and the refresh end
value.
45. The system of claim 44, wherein the memory device is further capable of
refreshing memory locations between the refresh start value and the refresh end
value.
46. The system of claim 45, wherein the memory device is a DRAM memory
device.
47. The system of claim 45, wherein the memory device is a Dynamic Data Rate
(DDR) memory device.
48. The system of claim 45, wherein the memory controller device is an Intel®
Graphics and Memory Controller Hub (GMCH).
49. The system of claim 44, wherein the memory device is capable of receiving
the refresh start value and the refresh end value over a data bus.
50. The system of claim 44, wherein the memory device is capable of receiving
the refresh start value and the refresh end value over an address bus.
51. A memory device comprising:
an array of memory cells;
at least one readable and writable data storage element to store a refresh start value indicating a specific point within the array of memory cells for starting
a refresh operation; and
at least one readable and writable data storage element to store a refresh end
value indicating a specific point within the array of memory cells for ending a
refresh operation.
52. The memory device of claim 51, wherein the array of memory cells is
arranged in one or more banks.
53. The memory device of claim 52, wherein each bank corresponds to a
readable and writable data storage element to store a start refresh value and a
readable and writable data storage element to store an end refresh value.
PCT/US2005/046943 2004-12-21 2005-12-21 A method, apparatus, and system for partial memory refresh Ceased WO2006069356A2 (en)

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US20060133173A1 (en) 2006-06-22
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US7342841B2 (en) 2008-03-11

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