WO2006067784A1

WO2006067784A1 - Chip packaging

Info

Publication number: WO2006067784A1
Application number: PCT/IL2005/001310
Authority: WO
Inventors: Haim Shalev
Original assignee: Rafael Armament Development Authority Ltd.
Priority date: 2004-12-23
Filing date: 2005-12-06
Publication date: 2006-06-29
Also published as: IL165948A0

Abstract

A chip or the like is vacuum packaged by accommodating the chip in the first chamber of a pre final assembly module, which cooperates with a lower cover having a getter, to provide a second chamber. The module has one or more passages for enabling fluid communication between the first chamber and the second chamber. Prior to joining and sealing the lower cover to the module at vacuum conditions, the getter is activated also under substantially vacuum conditions and while said module is spaced with respect to the lower cover.

Description

CHIP PACKAGING

FIELD OF THE INVENTION

The present invention relates to vacuum packaging of micro-electronic systems, in particular of many different types of chips including for example

Micro Electro Mechanical Systems (MEMS) and Micro Opto Electro Mechanical

Systems (MOEMS)₅ and both types of systems will be referred to hereinafter as

MEMS.

BACKGROUND OF THE INVENTION

Micro Electro-Mechanical Systems (hereinafter referred to also as "MEMS"), are integrated micro devices or systems combining electronic, optical and mechanical components. MEMS devices are fabricated using integrated circuit batch processing techniques, and are used in many areas including sensing, controlling, and actuating on the micro scale. These devices may function either individually, or in arrays to generate effects on a macro scale. Various types of micro electronic systems, and in particular MEMS, require vacuum working conditions, e.g. when micro sensor readings may be undesirably influenced by the presence of gas molecules, or e.g. when the operation of the micro device is based on under-pressure, as may be the situation with some types of pressure detectors.

Efforts at developing improved methods for providing vacuum operating conditions for MEMS or other micro-electronic devices may be regarded as falling into two generalized categories: vacuum packaging at the wafer level; and, vacuum packaging at the chip level. More particularly, the first approach is directed at micromachined devices having cavities at vacuum conditions between the internal layers of the wafer from which a microelectronic chip is to be diced, manufactured, and packaged. According to this approach, vacuum conditions are to be maintained with respect to the cavities between the wafer layers of the chip itself, and does not deal with the external packaging of the chip. This approach addresses the problems of gas generation during the bonding process between the wafer substrates, and gas desorption into the cavity from at least one of the substrates. In contrast, the second approach is directed to chips which are to be sealed in an external package under vacuum conditions. The external package is typically a robust structure that protects the chip from environmental effects such as mechanical damage, and comprises suitable electrical micro-terminals for electrically connecting the chip to other electrical or electronic components. This approach does not deal with providing vacuum conditions within the chip itself, i.e., between the wafer layers of the chip.

For example, US 6,499,354 discloses a method directed at dealing with trapped gases in micromachined devices, according to the aforementioned first approach. Such devices comprise a substrate, typically glass, onto which a silicon rim wafer is bonded to form a pressure sensor, comprising a vacuum cavity between the silicon wafer and the glass substrate. US 6,499,354 relates to the construction of vacuum cavities between the internal layers of a wafer, at the wafer production stage, after which the wafer may be diced, interconnected to external micro-components and/or terminals, and finally packaged in an external protective covering. This patent is not involved with providing a vacuum package for the chip itself, e.g., when a MEMS residing on a prepared wafer requires vacuum packaging at the micro-component level, i.e. at the level after the basic wafer has been diced and served as a basis for implanting on it external components, or for connecting to it external electrical or optical connections.

The first approach, as exemplified in US 6,499,354, and also in US 6,391,673 and in "Chip-Level Vacuum Packaging of Micromachines Using NanoGetters", by D. Sparks et al (IEEE Transactions on Advanced Packaging, VoI. 26, No. 3, August 2003), is often useful when dealing with some types of electronic or mechanic sensors or systems that may be fully fabricated at the wafer production level. However, for other types of micro-electronic systems, in which at least a part of the fabrication process utilizes techniques and methods that are not possible to implement at the wafer processing stage, the first approach is inadequate. Such techniques and methods may require components to be integrated into the prepared wafer at a later production stage, and may still require vacuum conditions for their proper operation, although the wafer processing level has already been completed. Thus, even if wafer-level vacuum cavities are present, these components cannot benefit from such a vacuum, and an external vacuum package is still required for such chips.

Regarding the second approach, it is often problematic to provide the ultra high vacuum levels required for such MEMS in their final package, and a getter external to the chip structure is commonly used to eliminate the gas and vapor residues. A getter, typically in the form of a metallic foil, irreversibly captures gas and vapor molecules such as oxygen, nitrogen, hydrogen, methane, carbon dioxide, carbon monoxide and H₂O, which are the main contributors to vacuum deterioration in a sealed vacuum control volume. Getters can therefore act as an inner vacuum pump for maintaining a high vacuum level within such a volume.

Typically, a getter is activated by exposing it to relatively high temperatures (i.e. between about 300⁰C and 500⁰C) for time periods that may vary between ten minutes and 18 hours. However, MEMS typically comprise delicate electronic components that are normally incapable of withstanding such high temperatures, and methods have been developed for protecting the MEMS from exposure to high temperatures during packaging and getter initialization.

In one known method for vacuum-enclosing an MEMS, where size constraints are substantially absent, the MEMS is accommodated in an over-sized package which is wide enough for positioning the getter sufficiently spaced from - A - any heat-sensitive component. Thus, these electronic components remain substantially unaffected by the heating process, which is applied directly to the getter that is already accommodated within the package. According to this method a vacuum is created in the package by suctioning its gaseous content during heating the getter, via an opening which is then permanently sealed.

In US 6,040,625, an apparatus developed by Scientific Sealing Technology, Inc. of Downey Calif, of the United States (hereinafter referred to as "SST"), is used for vacuum packaging electronic components. This apparatus enables minimizing the package size by eliminating the need for spacing the getter from the heat sensitive components as a function of the package dimensions. Essentially, the main body of the electronic package, typically in the form of an open box comprising the chip, is held at a spacing of several centimeters with respect to a cover under vacuum conditions in an oven. A getter is comprised on the inner facing surface of the cover, and heat is applied directly thereto such as to provide getter initialization. Although the main body of the MEMS is also in the oven, it is sufficiently spaced from the cover such that it is exposed to lower temperatures than the cover, arising indirectly from heat radiated from the cover. After getter initialization, the cover is brought into proximity and sealed with respect to the main body under vacuum conditions. The disclosed process is thus suitable only for cases where it is possible to subject the cover to high temperatures, and where the presence of the getter on the underside of the cover does not affect the operation of the chip.

Some types of micro-electronic systems, however, also require unobstructed optical communication with an outside environment for proper operation. By optical communication is meant the transmission and/or receipt of electromagnetic radiation of any wavelength, including but not restricted to γ- rays, X-rays, UV, visible light, IR, radio waves, and so on, between the system and the aforesaid external environment. Typically, vacuum packages used for such systems also require an optical window which is transparent to the aforesaid optical communication. The presence of such windows, prevents the getter from being positioned on the underside of a lid having such a window, since in a miniaturized application at least part of the getter would then block and interfere with optical communication via the window. Furthermore, subjecting a cover having such a window to high temperatures is problematic, and may result in damage to the cover-window interface. Covers that are fully or partially transparent (for example, by means of a window) for providing optical communication therethrough, and that are further capable of withstanding temperatures between 400⁰C and 500°C tend to be relatively high-value items economically, and thus dramatically increase the production costs for MEMS that require to be vacuum packed with such a cover, for example using the process described in the aforesaid US 6,040,625.

Of general background interest, the following patents disclose a variety of vacuum packages for MEMS or wafers: US 6,479,320, US 5,929,497, US 6,062,461, US 6,167,757 and US 6,718,605.

SUMMARY OF THE INVENTION

The present invention is directed along the aforesaid second approach, and relates to the establishment of vacuum conditions at the chip packaging stage, i.e. once the chip has been fully fabricated. While this is of particular utility for chips that include components integrated at the post-wafer production stage, this approach can also be used for chips which are fully fabricated at the wafer stage (with or without integral vacuum cavities according to the first approach).

The establishment of the vacuum conditions according to the present invention is by a method that will be described hereinafter, in which a pre-final assembly module is used for accommodating a chip prior to its vacuum sealing. Also will be described and claimed a kit for packaging a chip, comprising the components to be used for constructing the pre-final module and the complete packaging according to said method. Finally, the product of the method namely the complete packaging arrangement for a chip will be detailed and claimed. The establishment of the vacuum conditions according to the present invention is by a method that will be described hereinafter, which requires the use of a pre-final assembly module for accommodating a chip prior to its vacuum sealing, its details will also be described hereinafter. Also will be described a kit for packaging a chip, comprising the components to be used for constructing the pre- final module and the complete packaging according to said method. Finally, the product of the method namely the complete packaging arrangement for a chip will be detailed and claimed.

Herein, "vacuum conditions" refers to an environment (that is the environment in which it is desired to package the chip) that is at a low, typically at a highly reduced pressure with respect to an ambient (typically atmospheric) pressure (that is, outside of the package). Thus vacuum conditions may include a perfect vacuum as well as imperfect vacuums. In some applications of the present invention vacuum conditions may include environment pressures in the range of between about 1 and about 100 milli torr. In other applications the aforesaid vacuum conditions relate to environment pressures less than 1 milli torr including pressures in the order of micro torrs or less. In yet other applications the vacuum conditions may relate to environment pressures which may be greater than a 100 milli tor, and thus may include pressures up to any suitable sub ambient pressures. The method for vacuum packaging a chip according to the present invention comprises:

(i) providing a lower cover comprising a suitable getter on a portion thereof;

(ii) providing a pre final assembly module comprising a first chamber accoinmodating a said chip, and capable of cooperating with said lower cover to provide a second chamber, wherein said module comprises at least one passage for enabling fluid communication (in the context of the present invention when referring to fluid communication the term "fluid" includes matter in a fluid state e.g. gaseous, liquid, vapor and so on, and thus includes atoms, ions, molecules and particles of any material which may be captured by the getter) between said first chamber and said second chamber;

(iii) activating said getter under substantially vacuum conditions while said module is spaced with respect to said lower cover;

(iv) sealing said module by sealingly joining said lower cover with respect to said module under said substantially vacuum conditions to provide said second chamber accommodating said getter.

Said steps (iii) and (iv) of the method are performed in a suitable vacuum chamber.

One of the ways by which the lower cover may be provided with the getter comprises (in the above step (i)) fixing said getter to said lower cover, wherein the fixing is by at least one of clamping, welding, or soldering.

Another way by which the lower cover may be provided with the getter is by using a nanogetter, wherein in the above step (i) said nanogetter is deposited on said portion by means of an evaporation process.

The method of the present invention may further comprise prior to step (ii) the any of the following steps for the preparation of the pre-fmal module:

(a) removing organic materials from said chip;

(b) removing fluid residues from a base plate and an upper cover comprised in said module; (c) installing said chip on said base plate;

(d) establishing electrical connections between said chip and external terminals comprised on said module;

(e) sealingly connecting said upper cover to said base plate (this is preferably performed by soldering said upper cover to said base plate).

According to one option, step (iii) of the method is performed while maintaining said module and said lower cover in alignment.

The getter activation according to step (iii) of the method comprises the step of heating said getter to a predetermined temperature for a predetermined time period, wherein normally the predetermined temperature is in the range of between 300⁰C and about 500⁰C, and the predetermined time period may vary between about 10 minutes and about 18 hours.

The getter is preferably chosen from the group comprising NEG type getters and directly evaporated getters. For example, getter may be a thin film PaGe 787 getter or a high porosity thick film ST-122 getter.

After the sealing step (iv) the method will normally comprise the step of allowing said sealed module to cool, and it may also comprise the step of removing vacuum conditions external to said sealed module.

The pre final assembly module normally comprises external terminals operatively connected to said chip. According to various embodiments of the module these external terminals are located on a lower part of said module. According to other embodiments embodiment these external terminals are located on an upper part of said module. According to yet further embodiments the external terminals are laterally located with respect to said module.

According to various embodiments of the pre final assembly module of the present invention, the chip comprises a micro-electronic mechanical system. According to various embodiments of the pre final assembly module of the present invention the chip comprises optically sensitive components. The method according of the present invention may further comprise providing optical communication between said chip and an outside of said module. Such optical communication may be provided by means of a suitable window comprised in said module.

The method of the present invention may further comprise prior to its step (iii), the step of purging the said lower cover and said module with nitrogen gas.

According to the method of the present invention the pre final assembly module may be functionally tested prior to step (iii). Such test may be useful for clearing away defective modules early during the process, avoiding redundant expenses that might be involved in continuing their preparation.

The pre-fmal assembly module for accommodating a chip prior to vacuum sealing according to the present invention comprises a base plate having opposed upper and lower surfaces, said upper surface installing a said chip thereon, and said base plate adapted for providing external terminal electrical communication for said chip with respect to said module; and an upper cover sealingly fixed (preferably by soldering) with respect to the base plate defining a first chamber therebetween accommodating said chip; wherein said lower surface is adapted for cooperating with a lower cover to provide a second chamber, wherein said module comprises at least one passage for exclusively enabling fluid communication between said first chamber and said lower surface. Preferably, the at least one passage comprises at least one through hole through a thickness of said base plate.

According to various embodiments the base plate comprises a frame having an upper edge adapted for sealing connection with said upper cover, and a lower edge adapted for cooperation with said lower cover. According to various embodiments of the module, said external terminals are on a lower part of said module. According to other variations of the module said external terminals are on an upper part of said module. According to yet additional embodiments the terminals are laterally located with respect to said module.

According to various embodiments the base plate of the module is made from an insulating material, e.g. from the group of thick film ceramic, LTCC ceramic, HTCC ceramic.

According to other embodiments the base plate is made of metal, and the chip is isolated electrically from the base plate. Such metal base plate may further comprise circumscribing metal frame having apertures through which pass metallic terminals in electrical communication with the chip, and said terminals are isolated from the metal frame e.g. by sleeves or casting of isolated material sealingly filling the aperture portions between the frame and the corresponding terminal.

The kit for packaging a chip according to the present invention comprises: a base plate having opposed upper and lower surfaces, said upper surface adapted for installing a said chip thereon, said base plate adapted for providing external terminal electrical communication for said chip (wherein the external terminals could be located on a lower part of the base plate according to one embodiment type, on an upper part of the base plate according to other, or laterally with respect to the base plate according to yet another embodiment type), said base plate comprising at least one passage (e.g. a through hole through a thickness of said base plate) for exclusively enabling fluid communication between said upper surface and said lower surface; an upper cover adapted to be sealingly fixed (by soldering, preferably) with respect to the upper surface of said base plate such as to define a first chamber therebetween for accommodating said chip; and a lower cover comprising a getter and adapted to be sealingly fixed with respect to the lower surface of said base plate such as to define a second chamber therebetween for accommodating said getter.

According to various embodiments the base plate of the kit is made from an insulating material, e.g. from the group of thick film ceramic, LTCC ceramic, HTCC ceramic. According to other embodiments the base plate is made of metal. The kit may further comprise an isolating coating or a piece of insulating material for isolating the chip (and any of its electrical connections) electrically from the base plate.

Typically, said upper surface is adapted for installation of a chip that comprises a micro-electronic mechanical system and/or of a chip that comprises optically sensitive components.

According to several embodiments said upper cover comprises a suitable optical window for enabling optical communication between a said chip that may be accommodated in said first chamber when said upper cover is sealingly fixed to said base plate and an outside of said upper cover.

According to various embodiments the base plate comprises a frame having an upper edge adapted for sealing connection with said upper cover, and a lower edge adapted for cooperation with said lower cover.

The getter of the kit is preferably chosen from the group comprising NEG type getters and directly evaporated getters. For example, getter may be a thin film PaGe 787 getter or a high porosity thick film ST- 122 getter.

The chip packaging arrangement according to the present invention comprises a base plate having opposed upper and lower surfaces, said upper surface comprising a said chip installed thereon, said base plate adapted for providing external terminal electrical communication for said chip with respect to said arrangement (wherein the external terminals could be located on a lower part of the base plate according to one embodiment type, on an upper part of the base plate according to other, or laterally with respect to the base plate according to yet another embodiment type), said base plate comprising at least one passage (e.g. a through hole through a thickness of said base plate) for exclusively enabling fluid communication between said upper surface and said lower surface; an upper cover sealingly fixed (by soldering, preferably) with respect to the upper surface of said base plate defining a first chamber therebetween accommodating said chip; and a lower cover comprising a getter and sealingly fixed with respect to the lower surface of said base plate defining a second chamber therebetween accommodating said getter.

The chip in the packaging arrangement may comprise a micro-electronic mechanical system as well as optically sensitive components.

The upper cover may comprise a suitable optical window for enabling optical communication between a said chip and an outside of said upper cover.

The getter of the packaging arrangement is preferably chosen from the group comprising NEG type getters and directly evaporated getters. For example, getter may be a thin film PaGe 787 getter or a high porosity thick film ST- 122 getter. BRIEF DESCRIPTION OF THE DRAWINGS

In order to understand the invention and to see how it may be carried out in practice, a embodiment will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

Fig. 1 illustrates a cross sectional view of a chip sensor packaging arrangement according to a first embodiment of the present invention.

Fig. 2 illustrates an apparatus useful for batch processing a plurality of chip packaging arrangements, particularly for initializing getter activation and final vacuum sealing of the chip packaging arrangement.

Fig. 3 illustrates a cross sectional view of a chip sensor packaging arrangement according to a second embodiment of the present invention.

Fig. 4 illustrates a cross sectional view of a chip sensor packaging arrangement according to a third embodiment of the present invention.

Fig. 5 illustrates a cross sectional view of a chip sensor packaging arrangement according to a variation of the embodiment of Fig. 4.

Fig. 6 schematically illustrates a procedure for providing a pre final assembly module for use in the apparatus of Fig. 2.

Fig. 7 schematically illustrates a procedure for providing a lower cover with getter for use in the apparatus of Fig. 2.

Fig. 8 schematically illustrates a procedure for processing chip packaging arrangements, particularly for initializing getter activation and final vacuum sealing of the chip packaging arrangement. DETAILED DESCRIPTION OF THE INVENTION

Referring to Fig. 1, a first embodiment of the present invention comprises a chip packaging arrangement, generally designated with the numeral 100, adapted for providing electrical connection between an internal chip and external components via a lower part thereof. Thus, the chip packing arrangement 100 comprises a micro-electronic device, typically a MEMS chip 130, accommodated in a compartment A formed between carrier or base plate 120 and top cover 160 when these two components are joined together, as will be described in more detail hereinbelow.

The base plate 120 is typically thicker than the chip 130, though this may not be the case in some applications of arrangement 100. The base plate 120 is made from an insulating material, such as e.g. a suitable ceramic (LTCC - Low Temp. Co fire Ceramic, or HTCC- High Temp Co fire Ceramic for example), and is adapted for mounting the chip 130 onto one surface 122 thereof by any suitable means, e.g. by means of glass soldering, sol-gel, adhesive bonding or brazing. Alternatively, the base plate 120 may be made from silicon or the like, and built in layers with printed conducting paths to facilitate electrical connections therethrough, as will be described further herein.

The base plate 120 further comprises a plurality of internal contact terminals 128 within compartment A surrounding the chip 130 or are arranged under the chip for flip-chip connection. The terminals 128 are bonded, for example wire bonded or flip-chip bonded, to suitable connection points in the chip 130, and also electrically connected to UBM (Under Bump Metalization) bonding contacts or terminals 129 on the opposed surface 124 of the base 120 via conducting paths 127 fabricated in the base plate 120. This may be done in any suitable manner, e.g. according to Du-pont LTCC process disclosed in "A new approach for opto-electronic/MEMS packaging" by S. Horowitz and al. in 2002 Electronic Components And Technology Conference, pp. 259-262, the contents of which are incorporated herein in their entirety. The UBM terminals 129 are provided (at the end of the packaging process) with solder balls 195 for flip-chip assembly.

The top cover 160 is adapted for mounting over the surface 122 to form compartment A. Thus, in this embodiment, the top cover 160 is in the form of an open box, having a top panel 162 and sides 165, which are of the appropriate depth correlated, together with a suitable clearance, to the height or projection of the chip 130 from the surface 122. The top cover 160 is typically formed from a metallic material, for example kovar, and further comprises a flange-type rim 166 at the free edges of the sides 165, having at least a portion of the rim 166 gold- plated on its bottom surface 167. The gold plated portion of surface 167 overlies a solder preform 126 in the form of a ring formed on the surface 122 surrounding the chip 130 and terminals 128. The solder preform 126 may be applied to the surface 122 by spot resistance welding, for example, directed at a corresponding metallization ring prepared in advance on the surface 122. The solder preform 126 typically comprises a high temperature solder (which in general is a solder having melting temperature higher than that used for the solder preform 176), such as for example Au/Sn solder. After the chip is mounted onto the base 120 and electrically connected to the terminals 128, the top cover 160 is aligned and brought into contact with the base 120 such that the solder preform 126 is in contact with the gold-plated portion of surface 167. (In other variations of this embodiment, there is no rim 166, and in such embodiments surface 167 is restricted to the free edges of the sides 165.) Preferably, the cover 160 and the base plate 120 are placed in a vacuum oven for a fluxless void free soldering process. During this process the solder perform 126 melts and flows, and after a period of cooling the solder solidifies, thereby sealing the top cover 160 to the base 120.

Alternatively, the top cover 160/base 120 combination (including the chip 130), herein referred to as the pre-fmal assembly module 190, is moderately heated, for example to a temperature of 300⁰C in a case where a Au/Sn 20:80 solder is used (i.e. 20 parts Au per 80 parts Sn), until the solder perform 126 melts and flows. After a period of cooling the solder solidifies, thereby sealing the top cover 160 to the base 120. Alternatively, it is also possible to provide the solder preform on the rim 167, and the gold-plated surface on the surface 122.

In the illustrated embodiment the top cover 160 is substantially the same size and shape, in plan view, as the top surface 122 of the base 120. The dimensions of the base plate 120 are typically such that the chip 130 is tightly accommodated therein, and with as little clearance between the chip 130 and the sides 165 of the cover 160 as possible, with the ensuing miniaturization advantages. In other applications, the relative sizes and shapes of the top cover 160, base plate 120 and chip 130 may be different to the arrangement described above, mutatis mutandis.

Fig. 6 schematically illustrates various steps of a procedure 400 for providing the said pre final assembly module 190. Prior to the mounting step (Step 450) between the top cover 160 and the base 120, these components are typically cleaned and dried, as in known in the art. For example, in Step 410, the chip 130 itself may be subjected to plasma and UV ozone cleaning to remove possible organic matter that is attached thereto. In Step 420, the base 120 and the top cover 160 may be cleaned with a suitable alcohol or the like, and baked to a temperature of up to about 300⁰C (assuming a situation where step 420 is taken when the base 120 has not yet been provided with the solder preform 126) or of up to about 200⁰C (in case the step 420 is taken when base 120 contains already the solder preform 126), to remove moisture and trapped gasses therefrom

In Step 430 the chip 130 is installed on the base plate 120, and in Step 440, electrical connections are established between the chip 130 and the external terminals 129. Finally, the base 120 and top cover 160 can then be joined as described above in step 450, under clean conditions as in known in the art.

Referring again to Fig. 1, the chip 130 typically requires optical communication with the external environment E, and thus the top cover 160 is provided with aperture 163 with respect to which an optical window 161 is typically sealingly mounted by a solder glass or by vacuum brazing. The optical window 161 can be provided with AR (And Reflective) coating as desired. The material, dimensions and shape of the window 161 are such as permit at least the degree and quality of optical communication required for proper operation of the chip 130. Typically, the window 161 is of a shape and size that is similar to that of, and is in overlying registry with, the chip 130. In other embodiments, the whole panel 162 comprises the optical window. In yet other embodiments, the top cover 160 does not comprise a window, where the chip 130 does not require optical communication.

The chip packaging arrangement 100 further comprises a getter 180 accommodated in a second compartment B formed between base plate 120 and a bottom cover 150. Compartment B comprises a recess 123 on surface 124 of the base 120, the recess 123 being inboard of the UBM terminals 129. A second stepped recess 121 is provided between the periphery of recess 123 and the exposed part of surface 124, and comprises a solder preform 176 in the form of a ring formed on the surface of the stepped recess 121 surrounding the recess 123.

The solder preform 176 may be applied to the surface of recess 121 by spot resistance welding, for example, directed at a corresponding metallization ring prepared in advance on the surface of the recess 121. The solder perform 176 typically comprises a solder having melting temperature lower than that of the solder being used for the solder preform 126., For example in case that a Au/Sn solder of a ratio 20:80 is used for the solder preform 126, solder preform 176 may comprise e.g. Au/Sn 10:90 solder or e.g. In/Pb 60:40 solder. Thus, the solder perform 176 is typically applied after the module 190 is assembled. The bottom cover 150 is typically formed from a metallic material, such as kovar for example, and further comprises a rim 156 on a surface 152 of the bottom cover facing the recess 123, the rim 156 ending at the free edges thereof. The rim 156 comprises a gold-plated contact surface 157 that overlies the solder preform 176. The getter 180 is secured to a surface 152 of bottom cover 150, typically by welding, inboard of the rim 156. As will be described in greater detail hereinbelow, the bottom cover 150 may be sealingly secured with respect to the recess 123 of the pre-fmal assembly module 190 under vacuum conditions by means of the solder preform 176, and thus the getter 180 faces the recess 123. The thickness of the lower cover 150 is correlated to the depth of stepped recess 121, and these dimensions are typically substantially similar. In any case the said thickness may be such that when the lower cover 150 is sealingly secured with respect to the recess 123, the solder balls 195 that are attached to terminals 129 protrude beyond the exposed surface 152 of the lower cover 150, which may facilitate the flip-chip electrical connection to flat printed circuit boards or to other components. The recess 123 and the stepped recess 121 are typically formed as a part of the process of manufacturing the base plate 120 (e.g. as a part of an LTCC or of an HTCC ceramic substrate production process).

As illustrated in Fig. 7, the procedure 500 for the preparation of the lower cover 150 comprises, prior to Step 520 of affixing the getter 180 to the inside facing surface of the bottom cover 150, the Step 510 of removing moisture and gasses from the lower cover 150. In a similar manner to that described for the top cover 160, the bottom cover 150 may be cleaned with a suitable alcohol or the like, and baked to a temperature of about 400⁰C to remove moisture and trapped gasses therefrom.

One or a plurality of passages are formed in the base 120, enabling fluid communication between compartment A and compartment B for enabling gasses, vapors such as moisture, and the like, to flow between the two compartments. Typically, such passages are in the form of through holes 185 through the thickness of the base 120 into recess 123. The getter 180 material may comprise Zr-Al-Fe or Zr-V-Fe or other suitable materials, for example. The getter 180 may be a non-evaporable getter (known as NEG), such as for example thin film PaGe 787 or high porosity thick film, ST- 122, supplied by SAES GETTERS GROUP. In any case, the getter 180 is capable of removing via holes 185 any gases or vapors in chamber A after the chip packaging arrangement 100 has been vacuum-sealed by top cover 160 and bottom cover 150, thereby maintaining a high quality vacuum for operation of said chip 130. The holes 185 are typically of a diameter of between 0.1mm to lmm, and similarly to the recess 123 and the stepped recess 121 are formed in the base plate 120 during its buildup process e.g. through HTCC or LTCC manufacturing processes.

The bottom cover 150 may be sealingly secured with respect to the recess 123 of the pre-final assembly module 190 under vacuum conditions as follows, using, for example, the apparatus SST High Vacuum Furnace Model 3150 provided by Scientific Sealing Technology Inc., of Downey, California. In this or similar apparatus, and referring to Fig. 2, a vacuum chamber 10 is adapted for simultaneously processing a plurality of chip packaging arrangements 100. A pump and a suitable gas source 46 (comprising for example nitrogen, argon, helium and/or any other desired gases) are connected to the chamber to enable the same to be filled with a selected gas at a required pressure before the final sealing or to be flushed with the gas, thereby purging the said packaging arrangements 100, during its cooling period at the end part of the packaging process.

A pair of overlying graphite platens, 20, 30 are comprised in the chamber 10, and are adapted for relative movement with the aim of controlling the spacing between the two platens. Thus, at least one platen 20 may be moved towards and away from the second platen 30 by means of a suitable mechanism 40, maintaining alignment by means of parallel rails 45. The upper platen 30 comprises a plurality of vertically extending apertures 32, each of which is adapted for accommodating and holding a pre final assembly module 190, such that the recess 123 thereof is facing the opposed platen 20, and such that the stepped recess 121 sits exposed near the bottom end of aperture 32.

Thus, referring also to Fig. 8, in the Step 610 of the packaging process 600, the modules 190 are loaded into the apertures 32.

In the next Step 620, the bottom covers 150 are placed in seats in the form of cavities 25 formed in respective projections of the lower platen 20, such that the getters 180 of each lower cover 150 are each facing upwardly towards the corresponding recess 123 of an aligned module 190 held by the upper platen 30. In other embodiments, different means (i.e. other than said seats in the form of cavities 25) may be employed for accommodating or for holding the lower cover 150 appropriately to face upwardly towards the corresponding recess 123 of an aligned module 190 held by the upper platen 30.

The modules 190 are positioned in vertically extending apertures 32 and are prevented from falling downwards by means of rims or seats 33 formed near the lower ends of the vertically extending apertures 32. Weights 38 or other resistance-inducing means, such as for example suitable springs, are placed on top of the modules 190 in order to increase their resistance against a push from their bottom side, as will be further explained in step 630.

In Step 630, a vacuum pump 60 connected to the chamber 10 evacuates the same (at this stage of getter activation it is normally aimed to reach the max possible vacuum degree in the chamber, normally in the range of 1 micro torr). The lower platen 20, having been distanced in Step 640 as much as possible with respect to the upper platen 30 to minimize temperature effects to the chip 130, is heated in step 650 by means of electrical heating coil 90 up to the getter activation temperature for getter 180. (The electronic and optical components of the chip 130 are typically incapable of withstanding high temperatures at levels comparable to those required for getter activation.) The temperature of the lower platen 20 is monitored with temperature sensor 47. Getter activation typically takes 30-120 minutes depending on the getter type and the selected activation temperature. (For example, a ST122 getter may be activated at a temperature of 500C°, and only about only 10 minutes are required; if it is activated at 300C°, more than 18 hours are typically required. A PaGe787 getter typically requires about 45 minutes when activated in temperature of between 35O-45OC⁰.) After activation, the heating is then discontinued, and optionally the lower platen 20 may be allowed to partially cool. The gas type (e.g. He, Ar, or nitrogen) and the gas pressure in the chamber 10 are adjusted to the requirements (that is, normally between 1 and 100 milli torr, at this stage of sealing the packaging arrangement), and the lower platen 20 is moved towards the upper platen 30, until the rims 156 of the lower covers 150 make contact with the solder preforms 176 of the modules 190. The modules 190 are prevented from moving upwardly during the upwards movement and the contact of the lower covers by means of weights 38 placed on the top covers 160. Heat from the lower platen 20 is transferred to the upper platen 30, and thence to the modules 190, causing the low temperature solder of the preforms 176 to melt and flow while in contact with the surface 157 (Step 660). At the same time, the temperature reached at the seal between the base 120 and the upper cover 160 is insufficient to affect the solder thereat, and thus the seal between the base 120 and cover 160 is not compromised.

Thereafter, in Step 670, the platens 20, 30 are cooled (e.g. by first turning the heating coil off then, after solder solidification, directing a flow of N2 into the chamber through pump and gas source 46, sealing the lower cover 150 to the base 120, and thereby sealing off the chamber B from the environment E to complete the vacuum sealing of the packaging arrangement 100.

Typically, a vacuum of between 1 to 100 millitorr. with a deterioration not greater than 10^"14 to 10^"12 cubic-cm gas per sec, may thus be obtained for chambers A and B, and thus for operation of the chip 130 under appropriate conditions. The procedure 400 of providing a pre-fϊnal assembly module 190 has certain advantages in that, except for the holes 185, the chip 130 is encapsulated in a robust casing-like structure, and thus protected from the environment - that is, from mechanical damage, contamination by particulate matter, and so on. The module 190 thus provides a more convenient temporary receptacle for the chip 130 than an open box type of structure would, and enables the chip to be fully tested via terminals 129, before proceeding with the sealing process 600, thereby saving costs by not subjecting dud chips 130 or modules 190 to the sealing process, which would also result in the wastage of the lower cover 150 and getter 180. Accordingly, the procedure 400 and module 190 are also useful for chips 130 which do not require a window for operation of the chip.

A second embodiment of the present invention, illustrated in Fig. 3, comprises all the elements, components and features of the first embodiment as described above, mutatis mutandis with the differences described hereinbelow.

According to the second embodiment, the chip package arrangement, generally designated 200, is adapted for providing electrical connection between an internal chip and external components via an upper part thereof. Thus the chip packing arrangement 200 comprises a micro-electronic device, typically a MEMS chip 130, accommodated in a compartment A' formed between carrier or base plate 220 and top cover 260.

The base plate 220 comprises a plurality of internal contact terminals 128 within compartment A' surrounding the chip 130, and the terminals 128 are wire bonded to suitable connection points on the chip 130. However, the terminals 128 are also electrically connected to suitable bonding contacts or terminals 229 on the same surface 222 of the base 220 via conducting paths 227 fabricated in the base plate 220 (e.g. by using thick film technology of printing and firing conductors and insulators on ceramic substrates which is familiar to the skilled in the art). The upper cover 260 comprises an optical window 261, and is sealingly affixed to the base 220 by means of solder preform 226 that is brought into contact with gold plated rim 266 of the top cover 260 in a similar manner to that described for the first embodiment, mutatis mutandis. (In other variations of this embodiments, the rim 266 is eliminated, i.e. it is not a flange-type, and in such embodiments the solder perform 226 is brought into contact with the free edges of the vertically oriented sides of cover 260.) However, in this embodiment, the size of the base 220 in plan view exceeds that of the top cover 260 in order that the external terminals 229 remain outside of the cover 260 or compartment A' when the cover 260 is sealed with respect to the base 220. In this embodiment, compartment B' is formed between the relatively flat surface 224 of the base 220 opposed to the surface 222 comprising the chip 130, and a bottom cover 250 that is in the form of a narrow open box, comprising a panel 252 and sides 253. Fluid communication between chambers A' and B^f is possible via openings 285 through the base 220.

Typically, the lower cover 250 comprises a smaller width compared with the width of the base 220. Thus, when seats 33 are provided in each vertically extending aperture 32 in the upper platen 30 (Fig. 2) as a means for supporting the pre final assembly module 290, the smaller sized cover 250 can pass from the bottom side of aperture 32 and between the seats 33 to be joined to the underside of the base 220. Nevertheless, in other embodiments, different means other than said seats 33 may be employed for holding the pre final assembly module 290 in a vacuum chamber, and wherein the underside of base 220 remains fully exposed, so that cover 250 in such embodiments may be similarly sized to or of a larger size than the said base 220.

The getter 280 is fixed to the inside of the box, and the bottom cover 250 is vacuum sealed with respect to the pre final assembly module 290 (comprising cover 260 and base 220 including chip 130), after getter activation, by means of contacting and heating solder preform ring 276 against the gold-plated free edge of sides 253, in a similar manner to that described for the first embodiment, mutatis mutandis.

A third embodiment of the present invention, illustrated in Fig. 4, comprises all the elements, components and features of the first and second embodiments as described above, mutatis mutandis, with the differences described hereinbelow.

According to the third embodiment, the chip package arrangement, designated herein as 300, is adapted for providing lateral electrical connection between an internal chip and external components. The chip packing arrangement 300 comprises a micro-electronic device, typically a MEMS chip 130, accommodated in a compartment A" formed between carrier or base plate 320 and top cover 360.

In this embodiment, the base 320 comprises a frame 399 circumscribing the free edges thereof, so as to form an upper cavity 392 and a lower cavity 394. Typically, the base 320 and frame 399 are formed as an integral unit. When this integral unit is made from a metal, a layer of insulating material (not shown) is provided between the chip 130 and the upper surface of the base 320, and similarly, a plurality of input/output pins 329 are extending through apertures made in the metal frame 399 with a sleeve (not shown) of insulating material parting between the pins and the metal surface of the apertures.

The base plate 320 comprises a plurality of internal contact terminals 128 within compartment A" surrounding the chip 130, and the terminals 128 are wire bonded to suitable connection points on the chip 130. However, the terminals 128 are also electrically connected to the input/output pins 329 on the frame 399 via conducting paths 327 (typically made of wire-bonded gold or aluminium wires) fabricated in the chamber A". The upper cover 360 is substantially planar, comprising an optical window 361, and is sealingly affixed to the frame 399 by means of solder preform 326 that is comprised on the lower surface of the upper cover 360 (or on the free edge 366 of the frame 399, according to other variations of this embodiment) and brought into contact with gold plated upper free edge 366 (and according to said other embodiments - with appropriate metallization of the periphery of the bottom of cover 360) of the frame 399, in a similar manner to that described for the first and second embodiments, mutatis mutandis.

Alternatively, the top cover 360 may be fully transparent optically (except a metal rim matching the upper end of the frame 399, to allow for joining it to that surface by soldering), and is thus joined directly to the upper end of the frame 399 in an accordingly appropriate manner.

Similarly to the first embodiment, the size of the base 320 together with the frame 390 in plan view is similar to that of the top cover 360. The lower cover 350 is also substantially planar, comprising getter 380, and is sealingly affixed to the frame 399 by means of solder preform 376 that is comprised on the lower free edge 356 of the frame 399 and brought into contact with gold plated rim facing it on the upper surface of the cover 350, in a similar manner to that described for the first and second embodiments, mutatis mutandis. Alternatively, the lower cover may comprise an open-box type arrangement, as illustrated in Fig. 5

Fluid communication between chambers A" and B" is possible via openings 385 through the base 320.

The getter 380 is fixed to the inside of the cover 350, and the bottom cover 350 is vacuum sealed with respect to the pre final assembly module 390 (comprising cover 360 and base 320 with frame 399, including the chip 130), after getter activation, by means of contacting and heating solder preform ring 376 against the gold-plated free edge 356, in a similar manner to that described for the first and second embodiments, mutatis mutandis. In the method claims that follow, alphanumeric characters and Roman numerals used to designate claim steps are provided for convenience only and do not imply any particular order of performing the steps.

Finally, it should be noted that the word "comprising" as used throughout the appended claims is to be interpreted to mean "including but not limited to".

While there has been shown and disclosed exemplary embodiments in accordance with the invention, it will be appreciated that many changes may be made therein without departing from the spirit of the invention.

Claims

1. A method for vacuum packaging a chip, comprising: (i) providing a lower cover comprising a suitable getter on a portion thereof;

(ii) providing a pre final assembly module comprising a first chamber accommodating a said chip, and capable of cooperating with said lower cover to provide a second chamber, wherein said module comprises at least one passage for enabling fluid communication between said first chamber and said second chamber; (iii) activating said getter under substantially vacuum conditions while said module is spaced with respect to said lower cover;

2. Method according to claim 1, wherein step (i) comprises fixing said getter to said lower cover.

3. Method according to claim 2, wherein said fixing is by at least one of clamping, welding, or soldering.

4. Method according to claim 1, wherein said getter comprises a nanogetter, and said nanogetter is deposited on said portion by means of an evaporation process.

5. Method according to claim 1, further comprising prior to step (ii) the steps:

(a) removing organic materials from said chip; (b) removing fluid residues from a base plate and an upper cover comprised in said module;

(c) installing said chip on said base plate;

(d) establishing electrical connections between said chip and external terminals comprised on said module; (e) sealingly connecting said upper cover to said base plate.

6. Method according to claim 5, wherein step (e) is performed by soldering said upper cover to said base plate.

7. Method according to claim 1, wherein step (iii) is performed while maintaining said module and said lower cover in alignment.

8. Method according to claim I₅ wherein step (iv) comprises the step of heating said getter to a predetermined temperature for a predetermined time period.

9. Method according to claim 8, wherein said predetermined temperature is in the range of between 300⁰C and about 500⁰C

10. Method according to claim 8, wherein said predetermined time period is between about 10 minutes and about 18 hours.

11. Method according to claim 1, wherein said getter is chosen from the group comprising NEG type getters and directly evaporated getters.

12. Method according to claim 11, wherein said getter is a thin film PaGe 787 getter or a high porosity thick film ST- 122 getter.

13. Method according to claim 9 comprising the step of allowing said sealed module to cool.

14. Method according to claim 10, further comprising the step of removing vacuum conditions external to said sealed module.

15. Method according to claim 1, wherein said module comprises external terminals operatively connected to said chip.

16. Method according to claim 15, wherein said external terminals are located on a lower part of said module.

17. Method according to claim 15, wherein said external terminals are located on an upper part of said module.

18. Method according to claim 15, wherein in said external terminals are laterally located with respect to said module.

19. Method according to claim 1, wherein steps (iii) to (iv) are performed in a suitable vacuum chamber.

20. Method according to claim I₅ wherein said chip comprises a microelectronic mechanical system.

21. Method according to claim I₅ wherein said chip comprises optically sensitive components.

22. Method according to claim 21, comprising providing optical communication between said chip and an outside of said module.

23. Method according to claim 22, wherein said optical communication is provided by means of a suitable window comprised in said module.

24. Method according to claim 1, comprising, prior to step (iii), the step of purging the said lower cover and said module with nitrogen gas.

25. Method according to claim I₅ wherein said module is functionally tested prior to step (iii).

26. A pre-fmal assembly module for accommodating a chip prior to vacuum sealing comprising: a base plate having opposed upper and lower surfaces, said upper surface installing a said chip thereon, and said base plate adapted for providing external terminal electrical communication for said chip with respect to said module; an upper cover sealingly fixed with respect to the base plate defining a first chamber therebetween accommodating said chip; wherein said lower surface is adapted for cooperating with a lower cover to provide a second chamber, wherein said module comprises at least one passage for exclusively enabling fluid communication between said first chamber and said lower surface.

27. A module according to claim 26, wherein said external terminals are on a lower part of said module.

28. A module according to claim 26, wherein said external terminals are on an upper part of said module.

29. A module according to claim 26, wherein said external terminals are laterally located with respect to said module.

30. A module according to claim 26, wherein said base plate is made from an insulating material.

31. A module according to claim 30, wherein said insulating material is included in the group: thick film ceramic, LTCC ceramic, HTCC ceramic.

32. A module according to claim 26, wherein said chip comprises a microelectronic mechanical system.

33. A module according to claim 32, wherein said chip comprises optically sensitive components.

34. A module according to claim 33, wherein said upper cover comprises a suitable optical window for providing optical communication between said chip and an outside of said module.

35. A module according to claim 26, wherein said at least one passage comprises at least one through hole through a thickness of said base plate.

36. A module according to claim 26, wherein said upper cover is sealingly fixed with respect to the base plate by soldering.

37. A module according to claim 26, wherein said base plate comprises a frame having an upper edge adapted for sealing connection with said upper cover, and a lower edge adapted for cooperation with said lower cover.

38. A kit for packaging a chip, comprising: a base plate having opposed upper and lower surfaces, said upper surface adapted for installing a said chip thereon, said base plate adapted for providing external terminal electrical communication for said chip, said base plate comprising at least one passage for exclusively enabling fluid communication between said upper surface and said lower surface; an upper cover adapted to be sealingly fixed with respect to the upper surface of said base plate such as to define a first chamber therebetween for accommodating said chip; a lower cover comprising a getter and adapted to be sealingly fixed with respect to the lower surface of said base plate such as to define a second chamber therebetween for accommodating said getter.

39. A kit according to claim 38, wherein said external terminals are on a lower part of said base plate.

40. A kit according to claim 38, wherein said external terminals are on an upper 5 part of said base plate.

41. A kit according to claim 38, wherein said external terminals are laterally located with respect to said base plate.

42. A kit according to claim 38, wherein said base plate is made from an insulating material.

10 43. A kit according to claim 42, wherein said insulating material is included in the group: thick film ceramic, LTCC ceramic, HTCC ceramic.

44. A kit according to claim 38, wherein said upper surface is adapted for installation of a chip that comprises a micro-electronic mechanical system.

45. A kit according to claim 44, wherein said upper surface is adapted for 15 installation of a chip that comprises optically sensitive components.

46. A kit according to claim 45, wherein said upper cover comprises a suitable optical window for enabling optical communication between a said chip that may be accommodated in said first chamber when said upper cover is sealing fixed to said base plate and an outside of said upper cover.

20 47. A kit according to claim 38, wherein said at least one passage comprises at least one through hole through a thickness of said base plate.

48. A kit according to claim 38, wherein said upper cover is adapted to be sealingly fixed with respect to the base plate by soldering.

49. A kit according to claim 38, wherein said base plate comprises a frame 25 having an upper edge adapted for sealing connection with said upper cover, and a lower edge adapted for cooperation with said lower cover.

50. A kit according to claim 38, wherein said getter comprises any one of NEG type getters and directly evaporated getters.

51. A kit according to claim 50, wherein said getter is a thin film PaGe 787 30 getter or a high porosity thick film ST-122 getter.

52. A chip packaging arrangement comprising : a base plate having opposed upper and lower surfaces, said upper surface comprising a said chip installed thereon, said base plate adapted for providing external terminal electrical communication for said chip with respect to said arrangement, said base plate comprising at least one passage for exclusively enabling fluid communication between said upper surface and said lower surface; an upper cover sealingly fixed with respect to the upper surface of said base plate defining a first chamber therebetween accommodating said chip; a lower cover comprising a getter and sealingly fixed with respect to the lower surface of said base plate defining a second chamber therebetween accommodating said getter.

53. A chip packaging arrangement according to claim 52, wherein said external terminals are on a lower part of said base plate.

54. A chip packaging arrangement according to claim 52, wherein said external terminals are on an upper part of said base plate.

55. A chip packaging arrangement according to claim 52, wherein said external terminals are laterally located with respect to said base plate.

56. A chip packaging arrangement according to claim 52, wherein said base plate is made from an insulating material.

57. A chip packaging arrangement according to claim 56, wherein said insulating material is included in the group: thick film ceramic, LTCC ceramic, HTCC ceramic.

58. A chip packaging arrangement according to claim 52, wherein said chip comprises a micro-electronic mechanical system.

59. A chip packaging arrangement according to claim 58, wherein said chip comprises optically sensitive components.

60. A chip packaging arrangement according to claim 59, wherein said upper cover comprises a suitable optical window for enabling optical communication between a said chip and an outside of said upper cover.

61. A chip packaging arrangement according to claim 52, wherein said at least one passage comprises at least one through hole through a thickness of said base plate.

62. A chip packaging arrangement according to claim 52, wherein said upper cover is sealingly fixed with respect to the base plate by soldering.

63. A chip packaging arrangement according to claim 52, wherein said base plate comprises a frame having an upper edge sealingly connected with said upper cover, and a lower edge sealingly connected with said lower cover.

64. A chip packaging arrangement according to claim 52, wherein said getter comprises any one of NEG type getters and directly evaporated getters.

65. A chip packaging arrangement according to claim 64, wherein said getter is a thin film PaGe 787 getter or a high porosity thick film ST- 122 getter. .