WO2006064394A1 - Empilement de couche sans bord (a gravure) pour applications a memoire non volatile - Google Patents

Empilement de couche sans bord (a gravure) pour applications a memoire non volatile Download PDF

Info

Publication number
WO2006064394A1
WO2006064394A1 PCT/IB2005/054055 IB2005054055W WO2006064394A1 WO 2006064394 A1 WO2006064394 A1 WO 2006064394A1 IB 2005054055 W IB2005054055 W IB 2005054055W WO 2006064394 A1 WO2006064394 A1 WO 2006064394A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
floating gate
gate stack
volatile memory
capping layer
Prior art date
Application number
PCT/IB2005/054055
Other languages
English (en)
Inventor
Guoqiao Tao
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2006064394A1 publication Critical patent/WO2006064394A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a method of manufacturing non- volatile memory devices. Moreover, the present invention relates to a non-volatile memory device. Also, the present invention relates to a semiconductor device comprising at least one nonvolatile memory device as mentioned above.
  • an (etching-) stop layer is provided on a silicon dioxide layer to enhance the contact etch step, in which a contact hole is to be etched in the silicon dioxide layer for providing an opening to an active area below the silicon dioxide layer.
  • the stop layer masks the silicon dioxide layer during the etching process and renders it possible to create a contact without the need to provide a border between the contact and edges of active areas, such as gate electrodes and source/drain regions.
  • a silicon nitride layer is used (or sometimes, a silicon oxi- nitride layer SiO x N y ) as a stop layer for this technology. Any misalignment of the contact or LIL (local interconnect layer) to active layers can be minimized in that a border is absent here.
  • a non-volatile memory device is known from US 6,696,724 which discloses a two-transistor flash memory cell which is manufactured by a so-called borderless technology.
  • Such a non- volatile memory device comprises a floating gate stack which consists of a charge trapping region and a control gate region, in which the charge trapping region is arranged for holding charge (electrons) and the control gate region is arranged for having a certain electrical potential which can affect the charge in the charge region.
  • source/drain regions are provided which in combination with the control gate region can be electrically biased to manipulate the charge in the charge region.
  • Each source/drain region is provided with a (metal) source/drain contact.
  • the control gate is provided with a (metal) gate contact.
  • the charge trapping region can be manipulated by a read operation, a write operation, and an erasure operation by applying appropriate electrical potentials to each of the source region, drain region, and control gate region, as applicable.
  • this object is achieved by a method of manufacturing a non-volatile memory device on a semiconductor substrate; the non-volatile memory device comprising a floating gate stack and a contact, the contact being adjacent to the floating gate stack with an interposed separation; the floating gate stack being covered by a borderless capping layer, the method comprising the actions of: depositing a charge trapping layer as a first layer of the floating gate stack; depositing an intermediate dielectric layer as a second layer of the floating gate stack; depositing a control gate layer as a third layer of the floating gate stack, and - depositing the borderless capping layer, wherein the deposition of the borderless capping layer comprises the actions of depositing an intermediate silicon dioxide layer, and depositing a second silicon nitride capping layer; said intermediate silicon dioxide layer being located between the floating gate stack and the second silicon nitride capping layer.
  • this object is achieved by a method of manufacturing a non-volatile memory device on a semiconductor substrate; the non-volatile memory device comprising a floating gate stack and a contact, the contact being adjacent to the floating gate stack with an interposed separation; the floating gate stack being covered by a borderless capping layer, the method comprising the actions of: depositing a charge trapping layer as a first layer of the floating gate stack; depositing an intermediate dielectric layer as a second layer of the floating gate stack; - depositing a control gate layer as a third layer of the floating gate stack, and depositing the borderless capping layer, wherein the deposition of the borderless capping layer comprises the actions of depositing an intermediate silicon dioxide layer, and depositing a silicon oxynitride capping layer; said intermediate silicon dioxide layer being located between the floating gate stack and the silicon oxy-nitride capping layer.
  • an intermediate silicon dioxide layer and either a silicon nitride capping layer or a silicon oxynitride capping layer as a borderless capping layer on top of the control gate strongly reduces the current leakage and breakdown probability between the gate and the contact (and the source/drain regions connected to the contact).
  • the electronic properties of the borderless layer stack in accordance with the present invention are greatly improved.
  • the resistivity of silicon dioxide is higher than the resistivity of silicon nitride.
  • the resistance to tunneling (i.e., charge transfer through the material) of silicon dioxide and that of silicon nitride are governed by different mechanisms (Fowler- Nordheim and Pool-Frenkel, respectively).
  • the probability of current leakage and/or voltage breakdown at a given voltage is smaller for a silicon dioxide layer than for a silicon nitride layer (of comparable thickness).
  • the present invention also relates to a non-volatile memory device on a semiconductor substrate; the non-volatile memory device comprising a floating gate stack and a contact, the contact being adjacent to the floating gate stack with an interposed separation; the floating gate stack being covered by a borderless capping layer, wherein the borderless capping layer comprises an intermediate silicon dioxide layer and a second silicon nitride capping layer; said intermediate silicon dioxide layer being located between the floating gate stack and the second silicon nitride capping layer
  • the present invention relates to a non- volatile memory device on a semiconductor substrate; the non-volatile memory device comprising a floating gate stack and a contact, the contact being adjacent to the floating gate stack with an interposed separation; the floating gate stack being covered by a borderless capping layer, wherein the borderless capping layer comprises an intermediate silicon dioxide layer and a silicon oxy- nitride capping layer; said intermediate silicon dioxide layer being located between the floating gate stack and the silicon oxy-nitride capping layer.
  • the present invention relates to a semiconductor device comprising at least one memory device as described above.
  • Figure 1 is a cross-sectional view of a prior art non- volatile memory cell in an X-Z plane
  • Figure 2 is a cross-sectional view of a non- volatile memory cell according to the present invention in the X-Z plane;
  • Figure 3 shows a cross-section through the stack of layers produced by the first plurality of actions as described above in the Y-Z plane;
  • Figure 4 is a plan view of the stack of layers in the X-Y plane at a first processing moment
  • Figure 5 is a plan view of the stack of layers as obtained at a second processing moment.
  • Figure 1 is a cross-sectional view of a prior art non- volatile memory cell in a
  • a first, horizontal direction X is indicated by arrow X.
  • a second direction Z perpendicular to X is indicated by arrow Z.
  • a third direction Y perpendicular to X and Z is perpendicular to the plane of the drawing.
  • the non- volatile memory cell MC is located on a semiconductor substrate 1, which may be a lightly p- or n-doped Si wafer.
  • the non- volatile memory cell MC comprises a floating gate stack including a floating gate FG, an intermediate (or interpoly) dielectric layer 20, a control gate CG, side- wall spacers 40, and a contact layer 30.
  • the floating gate FG is located on the surface of the semiconductor substrate 1 and separated from it by a tunnel oxide 10.
  • the intermediate dielectric 20 is present on the floating gate FG.
  • the intermediate dielectric 20 insulates the floating gate FG from the control gate CG, which is located on top of the intermediate dielectric 20.
  • Floating gate FG may consist of poly-Si or another charge trapping material.
  • the control gate CG may consist of poly-Si or Si-Ge, or even a metal.
  • the poly-Si may be doped, possibly in-situ or later by implant.
  • the poly-Si may be suicided (for example tungsten disilicide WSi 2 , titanium disilicide TiSi 2 , or cobalt disilicide CoSi 2 ).
  • the intermediate dielectric 20 may be a stack of a thin layer of silicon dioxide, a thin layer of silicon nitride, and a second thin layer of silicon dioxide (or ONO stack). Each of the thin layers has a thickness of about 5 - 10 nm.
  • the intermediate dielectric 20 may be a silicon oxynitride layer or a silicon dioxide layer.
  • the contact layer 30 is located on top of the control gate CG. This contact layer 30 provides a well-defined electrical contact between the poly-Si control gate CG and a (metal) control contact (not shown) for controlling the gate voltage of the control gate CG during operation.
  • the contact layer is a thin layer of titanium disilicide or cobalt disilicide, which is preferably self-aligned.
  • the sidewalls of the floating gate stack CG, FG, 20 are covered by a sidewall oxide layer 40.
  • a sidewall spacer 50 is present next to the sidewall oxide layer 40.
  • Such a sidewall spacer 50 typically consists of silicon nitride.
  • Source/drain regions S/D with relatively high doping levels are defined in the semiconductor substrate 1, which S/D regions extend below the tunnel oxide 10 and below a portion of the floating gate stack CG, FG, 20, as indicated by arrow DX.
  • the non- volatile memory cell MC is covered by a silicon nitride capping layer
  • the silicon nitride capping layer may have a thickness of about 50 - 100 nm.
  • the contact 60 is provided to the source/drain region S/D for conducting electrical signals to/from the S/D region.
  • the contact 60 (or local interconnect layer LIL) comprises a conducting material, e.g. a metal such as Al or W.
  • a suicide protective layer 80 may be present for preventing suicide formation on silicon.
  • the suicide protective layer 80 is a remnant from a processing step for manufacturing the non-volatile memory cell as shown.
  • a self-aligned suicide layer 90 is formed on the source/drain region S/D for improving the contact resistance of the junction between contact 60 and source/drain region S/D.
  • the suicide protective layer 80 may also be omitted.
  • Figure 1 indicates a critical distance XO between the contact 60 and the floating and control gates FG, CG.
  • the critical distance XO is typically about 100 nm in non- volatile memory devices MC of the 0.18 generation (i.e. using design rules for 0.18 ⁇ m). However, this critical distance XOmay become as small as 50 nm as a result of misalignment and variations in critical dimensions.
  • the critical distance will tend to be smaller and will impose a more stringent reliability requirement. It is noted that the application of both low and high voltages is required for non- volatile memory devices as illustrated in Figure 1.
  • the source/drain voltage will typically be about 2 V or less, whereas the operation of the floating gate stack may require voltages of about 15 - 30 V.
  • a problem of non- volatile memory cells from the prior art is related to the application of high voltages to the floating gate stack CG, FG, 20.
  • a current leakage and/or voltage breakdown may occur in a top corner of the floating gate stack CG, FG, 20 between the top of the control gate CG in the silicon nitride capping layer 70 and the adjacent contact 60.
  • Silicon nitride has a relatively high susceptibility to leakage and/or breakdown due to the relatively low tunneling resistance.
  • the tunneling resistance relates to a flow of charged particles, i.e., electrons, tunneling through the layer.
  • the tunneling resistance of silicon nitride is essentially governed by the Pool-Frenkel tunneling mechanism.
  • FIG. 1 is a cross-sectional view of a non- volatile memory cell according to the present invention in the X-Z plane.
  • the current leakage and/or voltage breakdown at the top corner of the control gate CG can be prevented by replacement of the silicon nitride capping layer 70 with a layer of a material different from that of the intermediate dielectric layer 20 and having a better resistance to current leakage and/or voltage breakdown.
  • a material replacing silicon nitride must also be compatible with the processing technology for manufacturing a non- volatile memory device.
  • a practical solution is to use a compound material which combines the properties of the silicon nitride layer as a borderless layer with improved electronic properties for reducing current leakage and/or voltage breakdown.
  • such a compound material may be a stack of a silicon dioxide layer and a second silicon nitride layer.
  • an intermediate silicon dioxide layer 100 is located between the contact layer 30 and the second silicon nitride capping layer 75.
  • the stack of the intermediate silicon dioxide layer 100 and the second silicon nitride capping layer 75 as shown in Figure 2 may have the same thickness as the individual silicon nitride layer 70 in Figure 1, about 50 - 100 nm. Both the intermediate silicon dioxide layer 100 and the second silicon nitride layer 75 may have a thickness of 25 - 50 nm.
  • the use of a stack of an intermediate silicon dioxide layer 100 and a second silicon nitride capping layer 75 provides an improvement of current leakage and/or voltage breakdown at the top corner of the control gate CG because of the properties of silicon dioxide: a relatively high electronic barrier height higher than that of silicon nitride and a different tunneling mechanism (i.e. Fowler-Nordheim). A better resistance against current leakage and/or voltage breakdown is obtained thereby.
  • the critical distance for current leakage and/or voltage breakdown can now be symbolically subdivided into the critical distance XO relating to the second silicon nitride layer 75 and a second critical distance Xl relating to the intermediate silicon dioxide layer 100.
  • the overall critical distance (XO + Xl) can be less than the critical distance observed in the non-volatile memory cell MC from the prior art.
  • the present invention renders it possible to use a non- volatile memory cell in device generations with smaller critical feature sizes.
  • the self-aligned suicide layer 90 may be omitted.
  • the compound material may be formed by a silicon dioxide layer and a silicon oxynitride layer (SiO x N y ). In that case, the silicon oxynitride layer 75a of Figure 2 replaces the second silicon nitride capping layer 75.
  • the method of manufacturing a non- volatile memory cell MC comprises a first plurality of actions: providing a semiconductor substrate 1 ; providing a shallow trench isolation STI; forming well regions (e.g., logic N-well, logic P-well, Flash well, High Voltage N-well, High Voltage P-well, depending on the design of the memory cell MC; well regions are not shown); growing a CMOS logic gate oxide (not shown) on the semiconductor substrate 1, followed by CMOS logic gate poly-Si deposition (not shown); removing CMOS logic gate oxide and CMOS logic poly-Si in the area designated for the creation of the memory cell MC; growing tunnel oxide 10 and depositing a first poly-Si layer FG; a first patterning of the first poly-Si layer FG to form floating gate lines in the first direction X; depositing an intermediate dielectric layer 20; (- removing the intermediate dielectric layer 20 in areas of the
  • FIG. 3 shows a cross-section through the stack of layers produced in the Y-Z plane by the first plurality of actions as described above.
  • the STI region is located in the semiconductor substrate 1.
  • the tunnel oxide 10 is located on the substrate 1.
  • the floating gate layer FG, the intermediate dielectric layer 20, and the control gate layer CG are stacked in that order on the tunnel oxide 10.
  • the floating gate FG is a rectangular object owing to the sequence of the first and the second patterning action.
  • the sidewalls and top surface of the floating gate FG are covered by the intermediate dielectric layer 20.
  • the control gate layer CG is now linear in shape since the second poly-Si layer was only subjected to the second patterning action.
  • the control gate lines extend in the third direction Y and have a certain width in the first direction X.
  • Figure 4 is a plan view of the stack of layers shown in Figure 3. The depicted area is in the X-Y plane.
  • entities have the same reference numerals as in the preceding Figures.
  • two adjacent control gate lines CG are shown.
  • the control gate CG lines are crossed by STI regions extending in the first direction X.
  • Below the CG lines the STI regions are indicated by dotted boundary lines.
  • the reference STI is placed between parentheses to indicate that the STI regions at these locations are covered by another layer.
  • the rectangular floating gate FG and intermediate dielectric stack 20 are located below the CG lines. To indicate their locations in the vertical Y-direction, the FG regions are demarcated by horizontal dashed lines.
  • the references 20, FG for floating gate FG and intermediate dielectric stack 20 are given between parentheses to indicate when the FG, 20 region at a location is covered by another layer.
  • the method proceeds with a second plurality of actions, comprising: oxidation of sidewalls 40; - implantation of source/drain regions S/D (to obtain a good hot carrier reliability); formation of sidewall spacers 50; formation of hard source/drain implants (to obtain a low resistance in the source/drain region and to achieve good ohmic contacts); - formation of self-aligned suicide 30 on top of the poly-Si control gate lines
  • CG by deposition of metal, annealing for forming a metal disilicide on the interface of the poly-Si of the control gate lines CG, and removing unreacted metal); deposition of the intermediate silicon dioxide layer 100; in the first embodiment: deposition of the second silicon nitride capping layer 75, or in the second embodiment: deposition of the silicon oxynitride capping layer 75a ; deposition of the ILD layer (inter layer dielectric, the layer below the metal layer); planarization of the ILD layer; - masking and etching to form contact holes for the contact 60 to the source/drain region S/D; deposition of contact metal (for example tungsten); planarization.
  • Figure 5 is a plan view of the stack of layers obtained after the second plurality of actions. Again, as in Figure 4 two adjacent CG lines are shown. On top of the CG lines the self-aligned suicide 30 is present. The self-aligned suicide 30 is covered by the intermediate silicon dioxide layer 100 and either the second silicon nitride capping layer 75 or the silicon oxynitride layer 75a. The source/drain regions S/D are located in between the STI regions. The source/drain regions S/D are separated from (OK?) the CG lines by the sidewall oxide 40 and sidewall spacers 50.
  • the source/drain regions S/D are covered by the intermediate silicon dioxide layer 100 and either the second silicon nitride capping layer 75 or the silicon oxynitride layer 75a .
  • a contact 60 is located in each of the areas of the intermediate silicon dioxide layer 100 and either the second silicon nitride capping layer 75 or the silicon oxynitride layer 75a that covers one of the source/drain regions S/D.
  • the contact 60 is shown to have a rectangular shape here. It is noted that the contact may have a different shape, for example circular. Again, entities not visible at the surface are indicated with their references within parentheses.
  • further actions may be carried out as back-end processing: formation of a further intermediate dielectric (not shown), of contacts (not shown), 'metal 1 ' deposition and patterning of 'metal 1', deposition of a further insulating layer, creation of a first via, and so on.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif (MC) à mémoire non volatile comprenant un empilement de grille flottante (FG, 20, CG) et un contact (60) adjacent à l'empilement de grille flottante (FG, 20, CG) et séparé de celui-ci par une séparation interposée (40, 50). L'empilement de grille flottante (FG, 20, CG) est recouvert d'une couche de recouvrement sans bord comprenant une couche intermédiaire (100) de dioxyde de silicium et une seconde couche (75) de recouvrement de nitrure de silicium. Ladite couche intermédiaire de dioxyde de silicium est située entre l'empilement de grille flottante (FG, 20, CG) et la seconde couche (75) de recouvrement de nitrure de silicium. L'invention concerne également un procédé de fabrication dudit dispositif (MC) à mémoire non volatile.
PCT/IB2005/054055 2004-12-13 2005-12-05 Empilement de couche sans bord (a gravure) pour applications a memoire non volatile WO2006064394A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04106498.1 2004-12-13
EP04106498 2004-12-13

Publications (1)

Publication Number Publication Date
WO2006064394A1 true WO2006064394A1 (fr) 2006-06-22

Family

ID=36128403

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/054055 WO2006064394A1 (fr) 2004-12-13 2005-12-05 Empilement de couche sans bord (a gravure) pour applications a memoire non volatile

Country Status (2)

Country Link
TW (1) TW200636928A (fr)
WO (1) WO2006064394A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0409107A2 (fr) * 1989-07-18 1991-01-23 Sony Corporation Dispositif de mémoire non volatile à semi-conducteur et son procédé de fabrication
US6194784B1 (en) * 1993-10-15 2001-02-27 Intel Corporation Self-aligned contact process in semiconductor fabrication and device therefrom
US20020003253A1 (en) * 1998-09-09 2002-01-10 Shota Kitamura Nonvolatile semiconductor memory device and its manufacturing method
US6486506B1 (en) * 1999-11-01 2002-11-26 Advanced Micro Devices, Inc. Flash memory with less susceptibility to charge gain and charge loss
US20030011017A1 (en) * 2001-07-10 2003-01-16 Samsung Electronics Co., Ltd. Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same
US20040079985A1 (en) * 2002-10-29 2004-04-29 Kabushiki Kaisha Toshiba Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0409107A2 (fr) * 1989-07-18 1991-01-23 Sony Corporation Dispositif de mémoire non volatile à semi-conducteur et son procédé de fabrication
US6194784B1 (en) * 1993-10-15 2001-02-27 Intel Corporation Self-aligned contact process in semiconductor fabrication and device therefrom
US20020003253A1 (en) * 1998-09-09 2002-01-10 Shota Kitamura Nonvolatile semiconductor memory device and its manufacturing method
US6486506B1 (en) * 1999-11-01 2002-11-26 Advanced Micro Devices, Inc. Flash memory with less susceptibility to charge gain and charge loss
US20030011017A1 (en) * 2001-07-10 2003-01-16 Samsung Electronics Co., Ltd. Nonvolatile semiconductor memory device with a multi-layer sidewall spacer structure and method for manufacturing the same
US20040079985A1 (en) * 2002-10-29 2004-04-29 Kabushiki Kaisha Toshiba Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof

Also Published As

Publication number Publication date
TW200636928A (en) 2006-10-16

Similar Documents

Publication Publication Date Title
US7767522B2 (en) Semiconductor device and a method of manufacturing the same
US8008702B2 (en) Multi-transistor non-volatile memory element
US7208796B2 (en) Split gate flash memory
US8278202B2 (en) Conductive spacers extended floating gates
US7834390B2 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
US7446370B2 (en) Non-volatile memory
US20070102731A1 (en) Semiconductor memory device and method of manufacturing the same
US6770934B1 (en) Flash memory device structure and manufacturing method thereof
US8035155B2 (en) Split-gate nonvolatile semiconductor memory device
US20090200600A1 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
US7479427B2 (en) Semiconductor device and method of fabrication
JP2009088061A (ja) 不揮発性半導体記憶装置及びその製造方法
US6962852B2 (en) Nonvolatile memories and methods of fabrication
JP4266089B2 (ja) 半導体記憶装置の製造方法
US20020137282A1 (en) Manufacturing method for isolation on non-volatile memory
KR100683389B1 (ko) 플래시 메모리의 셀 트랜지스터 및 그 제조 방법
US7348239B2 (en) Semiconductor device and method of manufacturing the same
US20080157163A1 (en) EEPROM device and method of forming the same
KR20040019191A (ko) 플래시 메모리 소자 제조 방법
US7109084B2 (en) Flash memory device and method for fabricating the same
WO2006064394A1 (fr) Empilement de couche sans bord (a gravure) pour applications a memoire non volatile
US20090200594A1 (en) Nonvolatile semiconductor memory device and method of manufacturing the same
JP2007506275A (ja) 不揮発性メモリ装置を製造する方法及びそれによって得られるメモリ装置
US20050116280A1 (en) Flash process for stacking poly etching
US7208801B2 (en) Nonvolatile semiconductor memory device and method of manufacturing the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 05822481

Country of ref document: EP

Kind code of ref document: A1