Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
  • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
  • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
  • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design

Definitions

• the present invention relates generally to the field of designing integrated circuits, and more particularly to hardware technologies for enforcing terms of a licensing agreement between a plurality of parties involved in a particular hardware design.
• the design of complex hardware systems involves a combination of creating new hardware sub-designs (e.g., portions of a proprietary hardware design code and supporting documentation) from scratch and purchasing hardware sub-designs that are prepared by an IP block owner.
• a designer purchases hardware sub-designs from an IP block owner (e.g., organizations/persons which own the intellectual property rights to hardware sub- designs) rather than develop a particular hardware sub-design internally.
• IP block owners face several challenges in licensing and maintaining control of their intellectual property (e.g., hardware sub-designs).
• One of the biggest challenges is the unauthorized use of and lack of effective ways of licensing hardware sub- designs on a per use basis.
• FPGAs field-programmable gate arrays
• ASICs application specific integrated circuits
• IP block owners must often sell global one-time licenses (e.g., a global one-time license to use a particular hardware sub-design on any and all FPGAs at a designer) unless the IP block owner trusts (e.g., through a long standing business relationship) that a designer will properly account for and pay for each use of the hardware sub-design.
• rampant theft pervades the industry because of a lack of ways to track where hardware sub-designs are copied and applied (e.g., once a hardware sub-design is sold, an IP block owner is unable to monitor and determine how many instances of a particular hardware sub-design were made on FPGAs).
• IP block owners are unable to maximize their leverage of intellectual property rights in hardware sub-designs, and are unable to control where their hardware sub-designs are ultimately utilized.
• Figure IA illustrates a FPGA 118 having a plurality of IP blocks 110A-110I.
• the FPGA 118 is coupled to designer 111 through bus 108.
• a designer 111 e.g., a person or company who is creating a hardware system
• transfers hardware sub-designs e.g., the designer 111 may reuse a particular hardware sub-design that was previous created by the designer 111, may develop a custom design, may use a design in the public domain, or may use a design purchased from or created by a third party IP block owner
• the designer 111 may transfer a representation of the design to the FPGA 118 to program one or more IP blocks 1 lOA-1101 and/or the designer's logic 150).
• the FPGA 118 includes a designer's logic 150 and a plurality of IP blocks 110A-110I.
• the designer's logic 150 includes hardware sub-designs that have been created by a designer 111.
• Each IP block 1 lOA-1101 within FPGA 118 includes a hardware sub-design that has been purchased from a third-party, (e.g., the hardware sub-design within a particular IP block HOA may be purchased from a third party IP block owner 100 as illustrated in Figure IB for example).
• Figure IB shows a prior art transaction flow diagram between a designer 111, IP block owner 100, and FPGA provider 120 for the implementation of a design.
• a designer 111 communicates first with the FPGA provider 120 as illustrated in circled 1.
• the communication, circled 1 may be a request to purchase a FPGA device 118 from the FPGA provider 120 (e.g., the FPGA provider may be any commercial supplier of FPGAs such as a distributor, retailer, manufacturer, and/or wholesaler).
• the FPGA provider 120 then ships to the designer Il i a FPGA 118 in circled 2. (e.g., the FPGA provider 120 may perform a credit check, generate an invoice, and accept an offer as part of a business transaction between designer 111 and FPGA provider 120).
• the designer 111 After the designer 111 receives the FPGA 118 from the FPGA provider 120 in circled 2, the designer 111 sends a request to an IP block owner 100 to purchase a proprietary hardware sub-design that the designer 111 requires to complete his hardware system in circled 3. (e.g., an IP block owner 100 may have ownership rights in the proprietary hardware sub-design that the designer 111 needs to complete his hardware system within the time and cost constraints afforded to him).
• an IP block owner 100 may have ownership rights in the proprietary hardware sub-design that the designer 111 needs to complete his hardware system within the time and cost constraints afforded to him).
• the IP block owner 100 After the designer 111 provides a request to the IP block owner 100 in circled 3 (e.g., the designer 111 may electronically send to the IP block owner 100 an offer to purchase the proprietary hardware sub-design in the form of a purchase order or may telephone the IP block owner 100 to purchase the proprietary hardware sub-design), the IP block owner 100 provides the proprietary hardware sub-design to the designer 111 in circled 4 (e.g., the IP block owner 100 may enter into a contract for a global license and provide the HDL and/or RTL implementation design details and corresponding documentation necessary to implement the proprietary hardware sub-design to the designer 111 after accepting the designer Ill's offer to purchase a global intellectual property license for the proprietary hardware sub-design owned by the IP block owner 100).
• the designer 111 then incorporates the proprietary hardware sub- design received from IP block owner 100 into the FPGA 118 (e.g., the designer 111 may program the FPGA 118 which has been purchased by the designer 111 from the FPGA provider 12O through the bus 108 as described previously in Figure IA).
• the IP block owner 100 loses control over his intellectual property after the proprietary hardware sub-design details are sent to the designer 111.
• the designer 111 can freely replicate and utilize it for as many FPGAs 118 as he/she desires (e.g., by replicating the license code in addition to the encrypted circuit).
• the IP block owner 100 is unable to determine whether the designer 111 has misappropriated the proprietary hardware sub-design that the IP block owner 100 has provided and is unable to monitor whether the design&r 111 has resold the proprietary hardware sub-design to others (e.g., the IP block owner 100 may have invested millions of dollars in the original design of his proprietary hardware sub-design, and may have difficulty in recouping his investment but for misappropriation and/or theft of the proprietary hardware sub-design by the designer 111 because the IP block owner 100 is unable to license his intellectual property to others).
• the IP block owner 100 may have invested millions of dollars in the original design of his proprietary hardware sub-design, and may have difficulty in recouping his investment but for misappropriation and/or theft of the proprietary hardware sub-design by the designer 111 because the IP block owner 100 is unable to license his intellectual property to others.
• a hardw are sub-design includes a license verification sub-design that is protected from user modification by encryption.
• connections between the licensing verification sub-design and portions of the logic code within the hardware sub-design for disabling an IP block are also encrypted to prevent modification.
• a license is generated based on a trusted host identifier within an external hardware device.
• a user cannot modify the trusted host identifier.
• each trusted host identifier is unique, and no two integrated circuits share the same trusted host identifier.
• the integrated circuit is a field programmable gate array or an application specific integrated circuit.
• an exemplary method uploads a first hardware sub-design that is designed by a designer onto a programmable gate array having a trusted host identifier, as well as uploads a second hardware sub-design that is provided by a third party and which can only function on the programmable gate array having a particular trusted host identifier.
• a license is generated based on a group of trusted host identifiers.
• the license determines how long the hardware sub-design will operate when the hardware sub-design is implemented within an integrated circuit having a trusted host identifier.
• the present invention also discloses apparatuses, including software media, which may be used to design integrated circuits.
• the present invention includes digital processing systems which are capable of designing integrated circuits according to the present invention, and the invention also provides machine readable media which, when executed on a digital processing system, such as a computer system, causes the digital processing system to execute a method for designing integrated circuits.
• a digital processing system such as a computer system
• Figure IB shows a prior art transaction flow diagram between a designer, an IP block owner, and a FPGA provider for implementation of a hardware design.
• Figure 2A illustrates a FPGA having a trusted host identifier, a plurality of licensing blocks, and a plurality of IP blocks associated with each licensing block, according to one exemplary embodiment of the present invention.
• Figure 2B shows a transaction flow diagram between a designer, an IP block owner, and a trusted host ID provider for the implementation of a hardware design using a trusted host identifier and a license code, according to one exemplary embodiment of the present invention.
• Figure 3 shows a hardware diagram of the use of a trusted host identifier and a license code between a computer, a license generator, and a trusted ID provider for the implementation of a design, according to one exemplary embodiment of the present invention.
• Figure 4A is a block diagram of a computer that may be used to implement embodiments of the present invention.
• Figure 4B is a flow chart illustrating operations within a computer at a designer that are used to implement a hardware sub-design within a FPGA having a trusted host identifier, according to one exemplary embodiment of the present invention.
• Figure 4C is a flow chart illustrating operations within a computer at a designer that are used to implement a hardware sub-design within an ASIC using an external hardware device having a trusted host identifier, according to one exemplary embodiment of the present invention.
• Figure 5 illustrates a FPGA having a trusted host identifier, a plurality of licensing blocks, a plurality of clock memories, and a plurality of IP blocks associated with each licensing block and clock memories according to one exemplary embodiment of the present invention.
• Figure 6 is a flow chart illustrating encryption of a license verification sub-design within a hardware sub-design with a trusted host identifier at an IP block owner to prevent modification, according to one exemplary embodiment of the present invention.
• Figure 7 is a flow chart illustrating the generation of a hardware sub-design license code by a license generator at an IP block owner after receiving a trusted host identifier from a designer, according to one exemplary embodiment of the present invention.
• Figure 8 is a flow chart illustrating the generation of a hardware sub-design license code having a time limit by a license generator at an IP block owner after receiving a trusted host identifier from a designer, according to one exemplary embodiment of the present invention.
• Figure 2A illustrates a FPGA 218 having a trusted host identifier 245, a plurality of licensing blocks 205A-205I, and a plurality of IP blocks 210A- 2101 associated with each licensing block 205A-205I, according to one exemplary embodiment of the present invention.
• a designer 211 communicates with the FPGA 218 through bus 208 (e.g., the designer 211 may compile all parts of a hardware sub-design by synthesizing, placing, routing, and generating a bit stream before downloading to an FPGA through bus 208).
• the designer 211 may be a hardware system designer who uses hardware sub-designs created internally as well as that purchased from third parties, according to one embodiment (e.g., the designer 211 may purchase a particular hardware sub-design from an IP block owner 200 and combine it with the designer's logic 250 to make a complete design within a FPGA 218 through bus 208).
• the bus 208 may be a direct connect local bus (e.g., a computer connected directly to the FPGA through a serial and/or parallel port). Alternatively, the bus 208 may be a local or wide area network from which designer 211 communicates to FPGA 218, according to another embodiment.
• the FPGA 218 includes a designer's logic 250, a trusted host ID 245, and one or more IP locations 240A-240I.
• the designer's logic 250 includes hardware sub-designs that have been solely created by a designer 211. (e.g., the designer's logic 250 might include hardware sub-designs that have been verified and already tested, or may include hardware sub-designs that have been previously used in other designs).
• the designer's logic 250 is separated from the IP locations 240A-240I because IP locations 240A-240I may be used for hardware sub-designs that have been designed by a third party in one embodiment.
• a trusted host ID 245 within the FPGA 218 maintains a unique, trusted host identifier for FPGA 218.
• the trusted host ID 245 may be implemented within a field programmable gate array using a built-in serial number (e.g., an FPGA may be manufactured a built-in serial number or the built- in serial number may be a one time programmable serial number) plus a design component that can be used in a license verification sub-design (e.g., a license verification sub-design within a hardware sub-design) to access that serial number without user visible connections in one embodiment (e.g., to protect the license verification portion of the sub-design from modification by the user).
• a built-in serial number e.g., an FPGA may be manufactured a built-in serial number or the built- in serial number may be a one time programmable serial number
• a design component that can be used in a license verification sub-design (e.g., a license verification sub-design within a hardware sub-design) to
• the trusted host ID 245 may be a unique number that has been permanently associated with FPGA 218 in one embodiment (e.g., the trusted host ID may be a number that was preset by a trusted host ID provider such as an FPGA manufacturer during fabrication). In one embodiment, a portion of the trusted host ID 245 may be common for a group of FPGAs (e.g., a mask having a fixed upper set of bits and the trusted host ID may be combined) that have been sold to a designer 211 by a trusted host ID provider 220 as shown in Figure 2B.
• a portion of the numeric host ID may be associated with a particular batch of FPGAs sold by a trusted host ID provider 220 to designer 211 so as to indicate the manufacturing time and/or location of manufacture of the FPGA 218).
• the identity of the trusted host ED 245 may be retrievable by designer 211 through bus 208 by querying the FPGA 218 in one embodiment, (e.g., a software program owned by designer 211, or a software program may allow designer 211 to read the contents of the trusted host ID 245).
• the trusted host ED 245 is unalterable without completely disabling FPGA 218 (e.g., the trusted host ID 245 may be protected against tampering through a circuit breaker that disables the FPGA 218 if someone attempts to change the identity of trusted host ID 245).
• the trusted host ED 245 is external to a field programmable gate array and various known techniques can be used for secure communication over insecure channels (e.g., virtual private networking protocol).
• a designer 211 may compile all parts of a hardware sub-design by synthesizing, placing, routing, and generating a bit stream before downloading to an FPGA 218.
• each EP block 205A-205I may be downloaded separately to different locations on FPGA 218.
• Each EP location 240A-240I includes a licensing block 205A-205I and an IP hardware design block 210A-210I (e.g., or EP block 210A-210I).
• Each EP location 240A-240I may be connected to designer logic 250. (e.g., to allow a particular EP location 240A to communicate and share hardware sub-design instructions with designer logic 250).
• the IP locations 240A-240I may be enabled and disabled when a new hardware sub-design is added and/or deleted from within an EP block 210A-210I in one embodiment, (e.g., an IP location 240A may be a logical association of a particular licensing block 205A to an EP block 210A that is created when proprietary hardware sub-designs purchased from an IP block owner as shown in Figure 2B are added and/or deleted within the FPGA 218, as opposed to a physical IP location).
• the licensing blocks 205A-205I may be used to enable IP blocks 210A-210I in one embodiment, (e.g., a particular licensing block 205A may unlock the contents of the EP block 210A to reveal a hardware sub-design that is provided by an IP block owner 200 as illustrated in circled 4 of Figure 2B).
• the licensing block 205A may receive a license and analyze a trusted host identifier 245 to decide which features of an IP block to enable.
• the licensing blocks 205A-205I include license verification hardware (e.g., a license verification sub-design within the hardware sub-design that is encrypted while generating the hardware sub-design) that validates consistency of a license code received from an IP block owner 200 (as shown in Figure 2B) with the trusted host identifier 245 to enable operation of the hardware sub-design.
• the licensing blocks 205A-205I may operate as electronic locks which keep out unlicensed designers of intellectual property from accessing hardware sub- designs within the IP blocks 210A-210I by comparing a license code received from an IP block owner (such as an IP block owner 200 as shown in Figure 2B) with an internal encryption scheme within the licensing blocks 205 A-205I that is dependent upon the trusted host ID 245 (e.g., the license code may work only on a FPGA having a particular trusted host ID 245 in one embodiment.
• the licensing block 205A may receive a license code (e.g. a string of binary data) through bus 208 from the designer 211 who received the license code from an IP block owner 200 (as shown in circled 4 on Figure 2B).
• a licensing block 205 A may compare the license code with the trusted host ID 245 and the encryption scheme within the licensing block 205A.
• the license code may be embedded within an IP block 210A-210I and/or may be embedded within the designer's logic 250.
• the IP blocks 210A-210I may be hardware sub-designs that have been provided by a third party IP block owner, according to one embodiment, (e.g., IP block owner 200 as later will be described in Figure 2B). Different IP block owners may have sold or licensed their hardware sub-designs to a designer 211 in another embodiment to form the IP blocks 210A-210I. (e.g., a first IP block owner may provide the hardware sub-design within IP block 210A, whereas a different IP block owner may provide the hardware sub-design within IP block 210B).
• IP blocks 210A-210I may share a common licensing block 205A-205I in another embodiment and/or may allow a common license code to enable their contents, (e.g., the same license code may operate to unlock a licensing block 205A as well as licensing block 205B).
• the licensing block 205A- 2051 may include a license verification sub-design that has been encrypted to prevent modification.
• the IP blocks 210A-210I will only function on the FPGA 218 having a particular host ID 245 value, and will not function on a different FPGA that has a different host ID value.
• the licensing blocks 205A-205I may make a decision to operate based on a combination of a trusted host identifier 245 and a license provided by the IP block owner 200 in one embodiment.
• the operation of the hardware sub-design may be prevented by asserting signals that interfere (e.g., causing state machines to reset and memories to never write) with the logic of the hardware-sub-design in one embodiment.
• the license verification sub-design may be encrypted so that the user is not able to modify any portion of the license verification sub-design (e.g., the design tool flow may prevent editing of this part of the hardware sub-design).
• the hardware sub- design is encrypted only for the purpose of protecting a license verification sub- design within the hardware sub-design from modification.
• connections between the licensing verification sub-design and portions of the logic code within the hardware sub-design for disabling the IP block may be encrypted to prevent modification.
• FIG. 2B shows a transaction flow diagram between a designer 211, an IP block owner 200, and a trusted host ID provider 220 for the implementation of a hardware design using a trusted host ID 245 and a license code, according to one exemplary embodiment of the present invention.
• a designer 211 sends a request to purchase a FPGA with a host ID 218 to a trusted host ID provider 220.
• the trusted host ID provider 220 may be a trusted manufacturer such as a FPGA manufacturer that has developed a trustworthy business reputation sufficient so that the IP block owner 200 believes that each FPGA manufactured by the trusted manufacturer has a unique and uneditable host ID 218.
• the trusted host ID provider 220 may be a company that manufactures an external hardware device (e.g., a dongle and/or microchip), which provides a trusted host identifier when connected to a computer (e.g., such as computer 311 in Figure 3).
• the designer 211 orders a trusted host ID (or FPGA with trusted host identifier 218) from the trusted host ID provider 220. (e.g., the designer 211 may place an order by sending a purchase order to the trusted host ID provider 220 for the purchase of an FPGA 218 with a built in trusted host identifier 245 for use in a design of a customized integrated circuit).
• the designer 211 may also inform the trusted host ID provider 220 which IP block owner 200' s hardware sub-design the designer 211 intends to use in his/her hardware system in circled 1 (e.g., the designer 211 may communicate to the trusted host ID provider that he/she intends to use a hardware sub-design created by IP block owner 200 for example).
• the trusted host ID provider 220 ships a FPGA with a trusted host ID 218 to the designer 211, or alternatively provides an external hardware device having a trusted host identifier (e.g., the trusted host ID provider 220 may enter into a binding contract with designer 211 and produce a unique host- ED for each FPGA 218 ordered by the designer 211 for example).
• the external hardware device may be directly connected to the FPGA and it may not required that the external hardware device be connected to a computer.
• the trusted host ED provider 220 provides an external hardware device
• the designer 211 may need to connect the external hardware device to a computer connected to an ASIC and/or FPGA on which a hardware sub-design owned by an IP block owner 200 is used, (e.g., the designer 211 may connect a peripheral device having a trusted host identifier to a USB port on a computer that the designer 211 may use to write to an ASIC and/or FPGA that uses the hardware sub-design owned by the IP block owner 200).
• the serial number of a computer may be used as the host identifier in one embodiment.
• the IP block owner 200 must trust (e.g., have faith) that the host identifiers generated by the external hardware device are unique and unmodifiable. As such, the IP block owner 200 may need to pre- qualify each trusted host BD provider 220 that wishes to generate trusted host identifiers in one embodiment. In another embodiment, an independent trade organization may provide guidelines and qualification of trusted host ID providers.
• the designer 211 informs the IP block owner 200 that the designer 211 has made a purchase of the FPGA w/host ID 218 (or an external device having a trusted host identifier), and the designer 211 places an order for a hardware sub-design owned by IP block owner 200 (e.g., the designer 211 may purchase part of a complex integrated circuit design from the IP block owner 200 so that the designer 211 can save time rather than designing from scratch for example).
• the designer 211 informs the IP block owner 200 that the designer 211 has made a purchase of the FPGA w/host ID 218 (or an external device having a trusted host identifier), and the designer 211 places an order for a hardware sub-design owned by IP block owner 200 (e.g., the designer 211 may purchase part of a complex integrated circuit design from the IP block owner 200 so that the designer 211 can save time rather than designing from scratch for example).
• the designer 211 may also inform the IP block owner 200 of the identity of the trusted host ID (e.g., the designer 211 may run a software program that determines the identity of the trusted host identifier by reading a fixed register bit within the FPGA with host ED 218 and/or on an external hardware device).
• the EP block owner 200 is able to better regulate the ways the hardware sub-design, owned by the IP block owner 200, is used (e.g., the IP block owner 200 can restrict the use of his/her hardware sub-design only to certain FPGAs by providing a license to the designer 211 that works with only a certain group of trusted host EDs).
• the IP block owner 200 may provide a license code that requires an external hardware device that includes a trusted host identifier be connected to a computer at the designer 211 in one embodiment.
• the IP block owner 200' s hardware sub-design may operate only on an ASIC and/or an FPGA that has the external hardware device connected.
• the IP block owner 200 is able to charge a variable amount for his/her intellectual property (e.g., hardware sub-designs), by charging on a per use basis rather than for a global license, (e.g., the IP block owner 200 can charge for each FPGA on which their hardware sub-design is used because there is an enforcement mechanism in that every instance of the hardware sub-design is known, as opposed to a one-time fee to license a hardware sub-design for all FPGAs).
• the IP block owner 200 is able to prevent unauthorized sublicensing and/or theft of the hardware sub-designs owned by the IP block owner 200.
• Figure 3 shows a hardware diagram of the use of a trusted host identifier and a license code between a computer, a license generator, and a trusted host ID provider for the implementation of a design, according to one exemplary embodiment of the present invention.
• Figure 3 is similar to Figure 2B in that all the processes occurring in Figure 2B occur in Figure 3, except that Figure 3 illustrates the particular hardware used by the parties shown in Figure 2B.
• a computer 311 resides within a designer 211 as previously described in Figure 2B (e.g., the computer 311 may communicate with an FPGA with host ID 218 through bus 208 as described in Figure 2A).
• a supplier of programmable ICs typically determines the target architecture.
• An example of a target architecture is the programmed look-up tables (LUTs) and associated logic of field programmable gate arrays from Xilinx, Inc., of San Jose, California.
• Other examples of target architecture/technology include those well-known architectures in FPGAs and complex programmable logic devices from vendors such as Altera, Lucent Technologies, Advanced Micro Devices, and Lattice Semiconductor.
• the present invention may also be employed with ASICs.
• the method of Figure 4B begins in operation 411 in which a designer (such as a designer 211 as shown in Figure 2B) prepares a design representation (e.g., a behavioral description of a desired circuit) including license validation hardware protected from modification.
• a design representation e.g., a behavioral description of a desired circuit
• the design is displayed with the IP block, which is hidden, and changes are allowed to the design except for the IP block which is not editable (e.g., the designer's logic 250 may be editable whereas the IP locations 240A-240I having hardware sub-designs provided by an IP block owner 200 may be hidden and may be partly or completely uneditable as shown in Figure 2A).
• the design representation is then compiled by an HDL compiler in operation 413 to generate a technology independent RTL netlist.

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