WO2006032298A1 - Planarisation d'heterostructures epitaxiales comprenant un traitement thermique - Google Patents

Planarisation d'heterostructures epitaxiales comprenant un traitement thermique Download PDF

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Publication number
WO2006032298A1
WO2006032298A1 PCT/EP2004/011439 EP2004011439W WO2006032298A1 WO 2006032298 A1 WO2006032298 A1 WO 2006032298A1 EP 2004011439 W EP2004011439 W EP 2004011439W WO 2006032298 A1 WO2006032298 A1 WO 2006032298A1
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WO
WIPO (PCT)
Prior art keywords
polishing
annealing
rpm
strain
epitaxial heterostructure
Prior art date
Application number
PCT/EP2004/011439
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English (en)
Inventor
Muriel Martinez
Nicolas Daval
Olivier Rayssac
Beryl Blondeau
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S.O.I.Tec Silicon On Insulator Technologies
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Publication date
Application filed by S.O.I.Tec Silicon On Insulator Technologies filed Critical S.O.I.Tec Silicon On Insulator Technologies
Priority to PCT/EP2004/011439 priority Critical patent/WO2006032298A1/fr
Publication of WO2006032298A1 publication Critical patent/WO2006032298A1/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/12—Lapping plates for working plane surfaces
    • B24B37/14—Lapping plates for working plane surfaces characterised by the composition or properties of the plate materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/0251—Graded layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Definitions

  • the present invention relates to the field of epitaxial heterostructures including a relaxed buffer layer epitaxially grown on a substrate of a different material, as for instance graded silicon germanium (SiGe) layers deposited on a Si substrate.
  • a relaxed buffer layer epitaxially grown on a substrate of a different material as for instance graded silicon germanium (SiGe) layers deposited on a Si substrate.
  • Relaxed graded SiGe buffers are commonly used notably as substrates for the achievement of high electron mobility structures.
  • the surface of the SiGe buffer is considerably roughened, exhibiting cross- hatch patterns, thus requiring polishing to flatten the surface before subsequent growth or wafer bonding steps can be achieved.
  • the characteristic cross-hatch surface roughness and the underlying strain fields of the misfit array can overlap, blocking threading dislocation glide and leading to dislocation pile-ups.
  • Such a metastable state can produce changes in the surface state when further steps of the process are performed, as induced by thermal activation.
  • many methods have been experimented in order to obtain smooth relaxed SiGe layers epitaxially grown on substrates of a different material such as Si.
  • thermal processes are carried out during the epitaxially growth of relaxed Si(i -X )Ge( X ) buffer layers.
  • RTA rapid thermal annealing
  • the prior art methods cannot provide a solution which ensures to obtain SiGe buffer layers without any surface topology, and this with a high rate of reproducibility. Even in the case of a chemical mechanical polishing (CMP), it can remain residual topology at the surface. Moreover, the cross-hatch may "reemerge" during subsequent thermal treatments.
  • CMP chemical mechanical polishing
  • an object of the present invention is therefore to provide a technique which insures that the surface of an epitaxial heterostructure is planarized with a sufficient quality for subsequent growth or wafer bonding, and this without risks of reemergence of surface topology notably during subsequent heating of the heterostructure.
  • This object is attained with a method of planarization of an epitaxial heterostructure comprising at least a strain-relaxed buffer layer epitaxially grown on a substrate of a different material, the method comprising: a step of thermal annealing the epitaxial heterostructure at a temperature of at least 900 0 C for a period of at least 2 hours, and a step of chemical-mechanical polishing the surface of the strain-relaxed buffer layer.
  • the planarization method of the invention provides a specific thermal treatment which allows, by improving the relaxation of the strain- relaxed buffer layer, to obtain a better quality of the surface planarization and to insure a stable material for further processing.
  • the thermal processing firstly brings an improvement to the polishing step for removing surface topology (e.g. cross-hatch) in that the strained heteroepitaxial buffer layer is completely relaxed before the chemical-mechanical polishing step.
  • the thermal annealing step structurally changes the surface of the layer in increasing the surface topology which, according to the method of the invention, is advantageous since the thermal annealing step is carried out before the polishing step.
  • the step of annealing the epitaxial heterostructure is carried out preferably in an atmosphere mainly composed of argon and that may contain about 2% of oxygen.
  • This slightly oxidizing atmosphere allows an oxide layer of a thickness about 150 A to be formed on the epitaxial heterostructure.
  • the step of annealing the epitaxial heterostructure is carried out at temperatures ranging from 900 0 C to 1000 0 C and for a period lying between about 2 hours to 4 hours.
  • the epitaxial heterostructure may comprise a strain-relaxed buffer graded SiGe layer grown on a silicon substrate, the SiGe layer having cross-hatch patterns and localized irregularities at its surface.
  • the step of annealing the epitaxial heterostructure is carried out ex situ, namely outside the epitaxy reactor after the formation of the epitaxial heterostructure, to insure high production yield since several wafers can be processed together.
  • the step of chemical-mechanical polishing the surface of the strain- relaxed buffer layer is carried out with a polishing pad having a compressibility comprised between 2 and 15% and a slurry containing at least 20% of silica particles having a size comprised between 70 and 100 nm.
  • This polishing step allows to reach high polishing rates (ex. 40 A/sec) appropriated for eliminating surface defects or topology on heteroepitaxial layers, such as cross-hatch patterns, and to achieve, in the same time, a final polish roughness values less than 4 A RMS for a scan area of 40*40 ⁇ m 2 and 2 A RMS for a scan area of 10*10 ⁇ m 2 , while preserving an industrial, cost effective process.
  • the method of the invention brings cost reduction and production yield in comparison with the usual polishing process which calls for important material removal usually takes place in two steps: one step for planarization followed by a finishing step to get a specified roughness level, such as disclosed in the patent EP 1 016 129.
  • This method of planarization further brings industrial advantages such as good reproducibility and is easily transferable for production.
  • the parameters of the polishing tool can be adjusted so as to reach a stabilized polishing rate around 40 A/sec, which permits to carry out the step of chemical mechanical polishing for a period less than 200 seconds.
  • the three above parameters can be adjusted according to the following possibilities:
  • said method may further comprise a step of molecular bonding the epitaxial heterostructure to a receiving substrate such as a silicon substrate.
  • Figure 1 is a curve showing general aspect of a thermal cycle performed during the annealing step of the invention.
  • - Figure 2 illustrates the influence of different annealing conditions on the surface planarity of SiGe buffer layers, either before chemical-mechanical polishing (CMP) or after, as measured with the surface Haze;
  • CMP chemical-mechanical polishing
  • Figure 3 shows the effects of annealing on the surface roughness, as measured by AFM, and the difference between a small surface scan (10*10 ⁇ m 2 ) and a larger surface scan (40*40 ⁇ m 2 );
  • Figure 4 shows pictures which enhance this benefit of annealing on the surface roughness after CMP, as observed with AFM performed on 40*40 ⁇ m 2 surface scans;
  • Figure 5 is a schematic of an apparatus for polishing according to an embodiment of the invention.
  • Figures 6A and 6B are curves showing polishing rate variation according to polishing time which are obtained with the method of the invention and with a conventional method.
  • the invention implements an annealing step in the overall processing of planarization of graded SiGe substrates in order to better eliminate by polishing the cross-hatch pattern and to provide thermally stable substrates for further wafer processing.
  • This annealing process can be carried out with the following values of the parameters: - temperature range: 900 -1000 0 C ; - annealing time: 2-4 hours ;
  • the temperature when the wafers are introduced in the oven (boat-in) at the beginning of the cycle and at the end of a cycle when they are taken out of the oven (boat-out) is between 300-600 0 C and typically about 500 0 C.
  • the ramp rate which is the period of time during the cycle when temperature is rising (i.e. ramp-up) or falling (i.e. ramp-down), is comprised in the range 5°C/min to 30 °C/min, typically of about 10 °C/min as indicated in figure 1.
  • the period of time for the ramp-up or the ramp- down is about 40 min.
  • the wafer temperature is kept constant (i.e. steady-state) at a steady-state temperature ranging from 900 0 C to 1000 0 C and for a steady-state time duration from 2 hours to 4 hours.
  • the annealing process is performed at atmospheric pressure under an argon atmosphere which can include about 2% of oxygen allowing the formation of an oxide layer of a thickness about 150 A.
  • the annealing is performed exsituQ.e, outside the epitaxy reactor) which allows several wafers to be processed at once and to introduce oxidizing compounds if needed.
  • it is believed that it results in more uniform relaxation if the SiGe layer.
  • Such an annealing results in an increase of the cross-hatch pattern before polishing as seen by Haze measurement, but it leads to an improved quality of the surface planarity after polishing, in that it allows to remove entirely the cross-hatch pattern.
  • the chemical-mechanical step is performed on a layer which is completely relaxed thanks to the previous annealing step.
  • the substrates obtained according to this process exhibit a better thermal stability for the further steps of the whole process notably those implementing thermal treatments. More precisely, the annealing step also changes the whole material of the layer, which results in a stable equilibrium for the internal energy of the material and prevents reemergence of surface topology at the time of subsequent heat treatments.
  • Figure 2 illustrates the influence of different annealing conditions on the surface planarity of SiGe buffer layers, either before chemical- mechanical polishing (CMP) corresponding to w Haze after TUT (thermal treatment)" in the figure or after corresponding to "Haze after CMP” in the figure, as measured with the surface Haze.
  • CMP chemical- mechanical polishing
  • FIG. 3 shows the effects of annealing on the surface roughness, as measured by AFM, and the difference between a small surface scan (10*10 ⁇ m 2 ) and a larger surface scan (40*40 ⁇ m 2 ).
  • A designates a starting Si(i- X )Ge x (x «20%) substrate material
  • THT designates annealing according to three different annealing conditions (THTl, THT2 and THT3)
  • CMP designates chemical-mechanical polishing.
  • the former scan (10*10 ⁇ m 2 ) leads to similar values of the roughness before and after CMP, whatever the thermal processing is, while only the latter scan (40*40 ⁇ m 2 ) allows to observe the increase of surface roughness after annealing but before CMP and the decrease of this roughness after CMP for annealed samples.
  • Figure 4 shows pictures which enhance this benefit of annealing on the surface roughness after CMP, as observed with AFM performed on 40*40 ⁇ m 2 surface scans: the first four pictures (pictures 1 to 4) show the cross-hatch patterns before CMP, with (pictures 2 to 4) or without (picture 1) annealing, while the last two pictures (pictures 5 and 6) show the difference in surface roughness after CMP between an annealed sample (picture 5) and a non-annealed sample (picture 6), the latter showing that punctual defects (intense lines) are still present.
  • the annealing process which is one object of the invention allows to eliminate, after CMP, both the cross-hatch pattern and the punctual surface defects.
  • the annealing step does not cause damages to the layer.
  • the annealing step according to the invention does not lead to migration of dislocations to the surface of the layer.
  • the chemical-mechanical polishing step is carried out.
  • FIG. 5 illustrates a system 10 according to an embodiment of the invention which can be used for implementing the method of the present invention.
  • the system 10 comprises a polishing head 11 into which a structure 12 to be polished is inserted and a plate 13 covered with a polishing pad 14.
  • a liquid abrasive or slurry is injected into the head, for example via a side conduit 15.
  • a polishing pressure Fe and a movement represented by an arrow 16 are applied to the head 11 to carry out polishing.
  • the structure 12 is a heterostructure comprising at least a heteroepitaxial layer 121, as for example a SiGe layer, which has grown on a substrate 120 of another material such as silicon.
  • the surface of the heteroepitaxial layer 121 is polished in order to eliminate cross-hatch patterns occurred during growth from the dislocation strain fields and annealing step.
  • the polishing step can also be used for smoothing the final surface disturbed after a transfer process using a substrate fracture method (ex. Smart CutTM) has been performed (after-cleaving residues).
  • a substrate fracture method ex. Smart CutTM
  • polishing pad that is a pad having a compressibility rate less than that of a soft pad and more than a hard pad. More precisely, the polishing pad used in the invention has a compressibility rate included between 2% (hard pad) and 15% (soft pad), preferably around 6%.
  • the CMP is also performed by an "aggressive" slurry containing a colloidal solution, such as a NH 4 OH solution, with high rate of silica, namely more than 20%, and silica particles in 70-100 nm range.
  • a colloidal solution such as a NH 4 OH solution
  • the combined use of the above-mentioned intermediate pad and aggressive slurry allows to perform CMP which are suitable to the polishing of heteroepitaxial layers, such as Si(i- X )Ge( X ) layers, permitting, on the one hand, to eliminate either the surface defects (Crosshatch patterns, after-cleaving residues), and, on the other hand, to achieve a final post bonding polish, while preserving an industrial, cost effective process.
  • a slurry slightly less aggressive e.g. diluted to 1/40 or containing smaller particles
  • the polishing pad used in the invention is primarily intended for smoothing the surface, while the slurry with a high rate of silica enhances the reactive and mechanical activity of the etching and hence allows to increase the polishing rate for Si(i- X )Ge( X ).
  • FIG. 6A shows the polishing rate according to polishing time which is obtained with a typical process (curve B) used for silicon polishing (soft pad of around 10% compressibility, "standard” slurry including a colloidal solution with a low rate of silica (less than 10%) and silica particles of 130-210 nm in diameter), here applied to SiGe polishing, and with the planarization method of the invention (i.e.
  • Figure 6A clearly shows the advantages of the planarization method of the invention for the polishing rate on Si(i- X )Ge( X ) since it permits to reach a polishing rate of around 40 A/sec, versus 2 A/sec with the typical process.
  • the processing duration is very short, less than 200 seconds in order to eliminate a Crosshatch pattern of a thickness around 500 nm and prepare surface for bonding.
  • Figure 6B which is an enlarged view of the curve A of figure 5A, indicates that the polishing rate decreases along with time and stabilizes from around 130 seconds to about 40 A/sec, a value well suitable for large material removal such as required by Crosshatch pattern removal. Such stabilization insures also good process reproducibility.
  • the method of planarization of the present invention allows to obtain a final polish roughness values less than 5 A RMS (4 A RMS for a scan area of 40*40 ⁇ m 2 and 2 A RMS for a scan area of 10*10 ⁇ m 2 ) that corresponds to the typical roughness value from which a molecular bonding can be performed. Therefore, the planarization method of the invention can be used as a surface preparation step for strain-relaxed buffer layers such as SiGe layers that must be molecular bonded on receiving substrates such as Si substrates.
  • the invention allows to get surface roughness values for as good as a usual final polishing processes, but in a much shorter time. A short time then insures to minimize major defects, such as scratches, which often occur for long polishing times. Consequently, the polishing process is better adapted for mass production.
  • polishing is performed in a one-step process on a completely relaxed epitaxial material thanks to the previous annealing step described above.

Abstract

L'invention concerne un procédé de planarisation d'une hétérostructure épitaxiale comprenant au moins une couche tampon à contrainte relâchée à croissance épitaxiale sur un substrat de matière différente, ce procédé consiste: - en une étape d'annelage thermique de l'hétérostrucutre épitaxiale à une température d'au moins 900 °C pour une période d'au moins deux heures, et - en une étape de polissage chimico-mécanique de la surface de la couche tampon à contrainte relâchée. Ce procédé fournit un traitement thermique spécifique qui permet, par amélioration du relâchement de la couche tampon à contrainte relâchée, d'obtenir une meilleure qualité de la planarisation de surface et d'assurer l'obtention d'une matière stable à des traitement ultérieures.
PCT/EP2004/011439 2004-09-22 2004-09-22 Planarisation d'heterostructures epitaxiales comprenant un traitement thermique WO2006032298A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/EP2004/011439 WO2006032298A1 (fr) 2004-09-22 2004-09-22 Planarisation d'heterostructures epitaxiales comprenant un traitement thermique

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Application Number Priority Date Filing Date Title
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008099245A1 (fr) * 2007-02-15 2008-08-21 S.O.I.Tec Silicon On Insulator Technologies Procédé de polissage d'hétérostructures
DE102007019565A1 (de) * 2007-04-25 2008-09-04 Siltronic Ag Verfahren zum einseitigen Polieren von Halbleiterscheiben und Halbleiterscheibe mit einer verspannt-relaxierten Si1-xGex-Schicht
US8304345B2 (en) 2008-06-10 2012-11-06 Soitec Germanium layer polishing
US9064702B2 (en) 2012-07-31 2015-06-23 Imec Method for manufacturing semiconductor devices

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008099245A1 (fr) * 2007-02-15 2008-08-21 S.O.I.Tec Silicon On Insulator Technologies Procédé de polissage d'hétérostructures
FR2912841A1 (fr) * 2007-02-15 2008-08-22 Soitec Silicon On Insulator Procede de polissage d'heterostructures
CN101611477B (zh) * 2007-02-15 2011-01-12 硅绝缘体技术有限公司 用于抛光异质结构的方法
DE102007019565A1 (de) * 2007-04-25 2008-09-04 Siltronic Ag Verfahren zum einseitigen Polieren von Halbleiterscheiben und Halbleiterscheibe mit einer verspannt-relaxierten Si1-xGex-Schicht
US8304345B2 (en) 2008-06-10 2012-11-06 Soitec Germanium layer polishing
US9064702B2 (en) 2012-07-31 2015-06-23 Imec Method for manufacturing semiconductor devices

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