WO2006028238A1

WO2006028238A1 - Test carrier

Info

Publication number: WO2006028238A1
Application number: PCT/JP2005/016691
Authority: WO
Inventors: Michinobu Tanioka; Yukiharu Akiyama
Original assignee: Nec Corporation; Renesas Technology Corp.
Priority date: 2004-09-06
Filing date: 2005-09-06
Publication date: 2006-03-16
Also published as: JPWO2006028238A1; JP4955395B2

Abstract

A test carrier is provided for inspecting a semiconductor device by holding the semiconductor device in a bare chip status and by electrically connecting the semiconductor device to an inspecting apparatus. The test carrier is provided with a probe pin, which is arranged at a position corresponding to an external electrode of the semiconductor device and has elasticity; a first wiring layer which is electrically connected to the probe pin and is formed on a base material; a metal protruding part formed at a part where the probe pin has a contact with the external electrode of the semiconductor device; a metal layer formed on the surface of the metal protruding part; and a second wiring layer formed on the first wiring layer. The metal layer and the second wiring layer are separated.

Description

Description Test carrier Technical field

The present invention relates to a test carrier for inspecting a bare LSI (bare chip), which is a semiconductor device, using the same device as a conventional package product. In particular, the bare carrier has a narrow electrode pitch and requires high-speed transmission. It relates to a test carrier suitable for inspection. Background art

In recent years, the demand for high-density and high-speed transmission of semiconductor devices has increased rapidly, and development of Sip (System ina Package) technology that systematizes certain functions using bare chip mounting has been actively conducted. The technology that directly mounts on the board is one key technology. However, at the present stage, only open / short and simple function tests called wafer inspection are performed at the pre-mounting stage, and high-speed testing at the actual operation level performed in the conventional package is performed. No burn-in test has been conducted.

In order to solve this problem, a method has been developed in which a bare chip is mounted on a test carrier and treated as if it were a packaged product. In this method, a test carrier using a carrier substrate having a metal protrusion (bump) as a contact for obtaining contact with an electrode of a bare chip and having an external terminal for obtaining electrical connection with an inspection apparatus is mainly used. Has been applied.

In addition to this, a structure has been proposed in which bumps are formed on the electrodes of the bare chip, thereby eliminating the metal protrusions (bumps) on the carrier substrate of the test carrier and reducing the cost, or a structure using a mold PKG. . Also, as a probe card for wafer inspection, it is not used as a test carrier, but it is a probe card structure for wafer inspection that uses a tape carrier package (TCP) lead or a stress metal spring as a contact. Is used.

Here, a test carrier using a carrier substrate on which metal protrusions (bumps) are formed is described in Japanese Patent Application Laid-Open No. 2000-0196 035 (Patent Document 1). Also, metal bumps are formed on the bar chip electrode, and a bumpless test carrier is described in Japanese Patent Application Laid-Open No. 11-112. A test carrier using a mold PKG is described in Japanese Patent Application Laid-Open No. 7-29 7 3 26 (Patent Document 3). Further, a wafer inspection probe using a TGP lead as a contact is described in Japanese Patent Application Laid-Open No. 2 03-3-2480 019 (Patent Document 4). Also, a wafer inspection probe using a stress metal spring is described in Japanese Patent No. 2 0 4-5 0 1 5 1 7 (Patent Document 5). Hereinafter, these Patent Documents 1 to 5 will be described in detail.

(1) Patent Document 1

As shown in FIG. 7, this is a test carrier structure using a membrane type film 20 (membrane sheet) having a metal protrusion (bump) 36 at a position facing the external electrode of the semiconductor device.

A metal protrusion 36 is formed on one side of the flexible membrane type film 20 at a position corresponding to the external electrode of the semiconductor device. Pads are formed to obtain electrical contact with the inspection device 30 (socket) by extending the pitch from the metal protrusion with the wiring layer. The semiconductor device is fixed by installing the semiconductor device on a test carrier in which the carrier substrate using the membrane type film 20 having the metal protrusions 36 is incorporated and closing the clamshell lid 16. In this state, an inspection is performed using a conventional device.

In this structure, a spring 31 is incorporated in the carrier lid 16 to obtain a contact pressure. It has dimensions and spring constants so that the desired contact pressure can be obtained when the lid 16 is closed. In addition, the material and thickness of the base 37 are optimized so that the carrier base 37 holding the membrane type film 20 is not bent by contact pressure. Further, an elastomer 17 is provided on the back surface of the membrane type film 20 having the metal projections 36 in order to absorb the height variation and parallelism of the contacts inside the carrier. (2) Patent Document 2

As shown in FIG. 8, the test carrier has a structure in which the metal protrusions 36 formed on the carrier substrate described in Patent Document 1 are omitted by forming the metal protrusions 36 on the external electrodes of the semiconductor device 1. It has a carrier structure that uses TAB (Tape Automated Bonding) tape 38 as the carrier substrate. The alignment of the external electrode of the semiconductor device 1 and the electrode of the T A B tape 3 8 is performed by the guide ring 3 4. The base 37 at the bottom of the carrier board uses rigid material. The structure is aimed at low-cost and stable contact by using a T A B tape and a positioning method that uses the outer shape of the chip. A similar structure is disclosed in Japanese Patent Laid-Open No. 10-2 1 3 6 2 6 (Patent Document 6).

(3) Patent Document 3

Figures 9 (a) and 9 (b) show structural diagrams of test carriers using conventional semiconductor packages.

Semiconductor device 1 is mounted on lead frame 40, and semiconductor device 1 and lead frame 40 are connected by bonding wire 42. Then, mold type semiconductor (PKG) to range mold 43, part of lead frame 40 and semiconductor This is a test carrier formed by removing device 1. The ball portion 4 1 of the bonding wire 4 2 is used as a contact. It is also possible to use a metal mold having a metal film instead of the semiconductor device 1. This structure can realize mass production ease and low-cost sockets by using a conventional package.

(4) Patent Document 4

FIG. 10 shows the contact probe structure, and FIG. 11 shows the manufacturing method. A plurality of wiring layers 46 are formed on the surface of the polyimide resin film layer 44, and the wiring layer 46 has a contact bin 4 at the front end portion, and a metal layer is provided only in a necessary portion on the back surface of the film. It is a contact probe structure of the structure. Conventionally, since the metal layer was provided on the entire back side of the film, each pin had a certain capacity and caused a signal delay. In order to solve this problem, a structure in which the metal film 45 is formed only in the necessary part is adopted, and the structure is made possible to improve the electrical characteristics and the assembly property by improving the flexibility. (5) Patent Document 5

FIGS. 12 (a) and (b) show the linear arrangement of the springs released from the substrate 5. FIG.

A single contact spring probe 54 is formed on the substrate 5 as a continuous layer by vapor deposition and photoengraving. Each continuous layer has a different inherent stress level. Release area 5 5 is undercut and etched, spring contacts are released and bent to form probe pin 4. By utilizing the semiconductor pre-process, a 0.001 inch (25.4 micrometers) spring pitch array 56 is possible.

(6) Other conventional examples

Japanese Patent Application Laid-Open No. 3-27454 (Patent Document 7) is a structure in which a cantilever is formed by wet etching using a silicon substrate and used as a substrate for a test carrier. If the inspection target is a bare chip with solder bumps, a structure is adopted in which pads are formed at the electrical contacts on the leads and pulled out to the external terminals with lead wires. If there is no solder bump, a solder bump is provided at the tip of the lead and the lead wire is used to pull it out.

Japanese Patent Application Laid-Open No. 6-29 5 9 6 4 (Patent Document 8) relates to an inspection socket having a structure in which an O-ring is made of silicon rubber to obtain elastic force for the purpose of inspecting a bare chip having double-sided electrodes.

JP-A-7-1 4 2 5 4 1 (Patent Document 9) is a probe for inspecting a device having a fine electrode of 60 m or less, and is a cantilever having a curved shape using a silicon substrate. The present invention relates to a probe having a structure in which a beam is formed, a conductive metal layer is formed on the surface layer, and an insulating layer is formed on the back surface.

In Patent Document 1, a metal protrusion is used as a contact, and a process is performed in which a via fill is formed on a membrane film by laser and then via filling and metal protrusion are formed by isotropic contact. For this reason, it is difficult to form metal protrusions in a fine region of a pitch of 50 or less mouthpieces with a certain height secured. Because it uses a film-like flexible material as the base material, the positional accuracy in the pitch direction of the metal protrusions is limited to about ± 5 micrometers due to the thermal history of the film substrate manufacturing process (for example, laser processing). It is. Therefore, 40 micrometer pitch or more It is difficult to control to the desired value (± 1.0 micrometer or less) in the lower fine region.

When performing high-temperature inspection at 80 to 125 ° C during burn-in inspection, the thermal expansion coefficient of film material (several tens of ppm) compared to the thermal expansion coefficient of silicon (2 to 3 _PP m) of semiconductor device materials Is big. For this reason, a positional shift occurs between the metal protrusion and the electrode of the semiconductor device. In addition, by repeatedly increasing and decreasing the temperature as in the monitor burn-in test, semiconductor device electrode debris adheres to the tip of the metal protrusion, and the contact characteristics deteriorate. Since the membrane film and the base are fixed by screws, there is a possibility that the screws will loosen due to the thermal history during the burn-in inspection. In addition, the cost of the carrier itself is high due to the large number of parts that make up the test carrier.

In Patent Document 2, since metal protrusions are formed on the bare chip electrode by pole bonding, it is difficult to form metal protrusions in a fine region of 40 micrometers or less. In addition, since the base of the test carrier is rigid, parallelism and variations in metal protrusion height must be absorbed by the amount of deformation of the metal protrusion. For this reason, the deformation of the metal protrusion is large, and wire bonding in the next process adversely affects the connection process such as flip chip. Even if the initial connection is obtained, the connection height is low, so it is difficult to ensure long-term reliability such as temperature cycle testing.

Furthermore, it is thought that the deformation of metal protrusions will increase due to the addition of a temperature cycle such as the monitor burn-in test. As in Patent Document 1, the carrier substrate that obtains contact with the metal protrusions on the bare chip electrode and connects to the inspection device uses a membrane type film using polyimide resin such as TAB tape. It has the same technical problem as the second problem of 1. When viewed from the viewpoint of the number of parts, compared to Patent Document 1, it is reduced in that it does not have a spring for pressurization in the lid, but it is not drastically reduced, so the carrier body price is high.

Further, in the case of the carrier structure described in Patent Document 6, the film member and the base member are only sandwiched and fixed by the fixing means, and neither member has a metal projection shape. For this reason, there is a high possibility of contact failure.

In Patent Document 3, although it can be estimated that the cost is very low, the structure is such that the contact with the external electrode of the semiconductor device is performed at the pole portion of the wire bonding. this For this reason, it is difficult to form contacts in a fine pitch region below 40 micrometer pitch. Since the mold resin is a thermosetting resin and does not have elasticity, all the variation in the height direction is absorbed by the deformation amount of the metal protrusion formed on the semiconductor device electrode, which is the second problem of Patent Document 2. There is a need. As a result, the amount of deformation of the metal protrusion increases, which adversely affects the connection process of the next process.

In Patent Document 4, since a polyimide resin film layer is used as a base material, it has the same technical problem as the second problem of Patent Document 1 and the second problem of Patent Document 2. As a manufacturing method, there is a process of bonding a film having a metal film layer. However, precise control of the amount of adhesive is difficult, and the wiring layer peeling due to insufficient adhesive and bleeding due to excessive adhesive occur, making manufacturing difficult. If a coating device that can be precisely controlled is used, the cost of the device increases. Since this process is followed by a process of separating from the supporting metal plate, it is difficult to ensure the contact bin position accuracy. The contact bin is made of Ni alloy and has an oxide film on the surface. In a fine pitch region of 30 micrometers or less, it is difficult to obtain a large contact pressure because there are restrictions on both the width and thickness of the contact pin. Therefore, it is necessary to obtain contact with a small contact pressure, but it is difficult to completely break through the oxide film, resulting in a contact state in which the oxide film is interposed. For this reason, it is difficult to obtain a stable contact. Assuming that this structure is applied to a test carrier, this structure has a contact bin on one side. For this reason, when the electrodes of the semiconductor device are arranged peripherally, it is necessary to manufacture four contact probes having this structure and assemble them to the carrier. Therefore, there are problems such as difficulty in securing the positional accuracy of the contact pins on the four sides and high carrier costs due to an increase in the number of parts.

In Patent Document 5, the stress metal spring is formed by a plasma deposition method as a manufacturing method. For this reason, it is difficult to increase the thickness of the spring. As a result, in a fine pitch region of 30 micrometer or less, it is difficult to obtain good contact because the contact pressure is insufficient. Even if initial contact is obtained, the stress applied to the base of the metal spring due to repeated contact causes plastic deformation in the metal spring, making it difficult to ensure long-term reliability.

As can be seen from Fig. 12, contact pressure is concentrated as the tip of the metal spring is pointed. The structure is adopted. However, when the electrode of the semiconductor device has a strong oxide film such as copper, it is necessary to precisely control the radius of curvature of the spring tip that contacts the semiconductor electrode, resulting in a significant increase in manufacturing cost. Since silicon, which is a semiconductor, is used as the base material, it is necessary to form an insulating film, a barrier layer, and a seed layer in the through electrode formation process. This leads to a significant increase in manufacturing costs. Disclosure of the invention

Problems to be solved by the invention:

Therefore, the present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to perform an inspection equivalent to that of a normal package product in a bare chip state semiconductor device, and to achieve an equivalent quality. In order to ensure this, it is an object of the present invention to provide a bare-chip test carrier that can handle ultrafine pitches of 40 micrometer pitch or less, is low cost, and is practical.

Means to solve the problem:

In the present invention, the semiconductor device is provided in a position corresponding to the external electrode of the semiconductor device in the test carrier for performing the inspection by holding the semiconductor device in a bare chip state and electrically connecting to the inspection device. A probe pin having elasticity; a first wiring layer electrically connected to the probe pin; and formed on a substrate; a metal protrusion formed on a portion where the probe pin contacts an external electrode of the semiconductor device; A metal layer formed on the surface of the metal protrusion, and a second wiring layer formed on the first wiring layer, wherein the metal layer and the second wiring layer are separated from each other. Yes. Furthermore, fixing means for fixing the semiconductor device to the base material is provided. Here, the metal layer has contact characteristics according to the material of the external electrode of the semiconductor device. Preferably, the substrate includes a through electrode penetrating between the front surface and the back surface of the base material and a third wiring layer formed on the back surface of the base material, and the first wiring layer and the third wiring layer are formed through the through electrode. The wiring layer is electrically connected.

The volume resistivity of the second wiring layer is preferably smaller than the volume resistivity of the first wiring layer.

Further, another metal layer was formed between the first wiring layer and the base material. The other The volume resistivity of the metal layer is preferably smaller than the volume resistivity of the first wiring layer. In addition, the metal protrusion formation region has a width direction equal to or less than the width of the probe pin, and the length direction indicates the amount of movement of the probe pin tip after the probe pin contacts the external electrode of the semiconductor device and the longitudinal direction of the probe pin. The rectangular shape is equal to or greater than the dimension including the position tolerance and the external electrode tolerance of the semiconductor device.The height of the external electrode of the semiconductor device contacts the metal protrusion with respect to the surface of the first wiring layer. More than the dimension including the height considering the amount of indentation and the height tolerance of the metal protrusion and the height tolerance of the external electrode of the semiconductor device.

When the external electrodes of the semiconductor device are arranged other than the single-row peripheral arrangement, it is preferable that the probe pins corresponding to the external electrodes of the semiconductor device have the same length. Further, when the external electrode of the semiconductor device is arranged other than the single row peripheral arrangement, the base material of the base portion of the probe pin corresponding to the external electrode existing on the center side of the semiconductor device has a protruding shape. Is desirable.

When the external electrode of the semiconductor device is arranged other than the single-row peripheral arrangement, the width of the first wiring layer on the substrate and the base portion of the probe pin corresponding to the external electrode existing on the center side of the semiconductor device is It is preferable that the probe pin corresponding to the external electrode existing outside the semiconductor device and the first wiring layer are both wider and projecting. Preferably, the metal layer on the surface of the metal protrusion is made of a gold alloy metal.

Further, it is preferable that the metal layer on the surface of the metal protrusion has a fine uneven shape. In this case, the fine uneven shape may be formed only in the same direction as the movement direction of the probe pin, or may be formed only in the direction perpendicular to the movement direction of the probe pin. The fine concavo-convex shape is formed in, for example, a grid shape, a file shape, or a random shape. The fine uneven shape is preferably an uneven shape having a surface roughness of 1 micrometer or less.

Moreover, it is desirable to have a through-hole in the center part of the said base material. Here, the shape of the through hole is the same as or smaller than the opening diameter of the base portion of the probe pin. As described above, the test carrier according to the present invention is a test carrier that holds the semiconductor device in a bare chip state and is electrically connected to the inspection device. Has elasticity at a position corresponding to the electrode of A probe pin that is independent of each other, and a base material that is electrically connected to the probe pin and on which the first wiring layer of the probe pin is formed, and the probe pin is in contact with the electrode of the semiconductor device Metal protrusions made of one or more metal layers are formed, and one or more metal layers made of a material having good contact characteristics according to the electrode material of the semiconductor device are formed on the surface of the metal protrusions. A second wiring layer that is one or more metal layers formed on the first wiring layer of the material, and the one or more metal layers on the surface of the metal protrusion, the second wiring layer, It is constituted by a carrier substrate characterized by having a separated structure and means for fixing the bare chip to the carrier substrate. In this configuration, a metal layer having good contact characteristics according to the electrode of the semiconductor device is provided at the tip of the contact surface between the independent lead-shaped probe pin and the semiconductor device electrode. This makes it possible to simplify the structure of the fixing means and integrate the base structure parts, dramatically reduce the number of parts, and reduce the carrier cost.

In addition, a material with a small coefficient of thermal expansion was applied to the base material of the carrier substrate to prevent deterioration in accuracy in the thermal history of the manufacturing process. In addition, we applied electrical technology to the manufacture of probe pins to ensure a certain level of thickness with very fine pin widths and to obtain sufficient contact pressure. In addition, probe pins and wiring layers were formed by the additive method using micromachine technology. As a result, it has become possible to deal with semiconductor devices having electrodes in an ultrafine pitch region of 40 micrometer pitch or less.

In addition, by providing a metal protrusion at the contact portion with the electrode of the semiconductor device and separating the second metal layer on the surface of the metal protrusion and the second wiring layer on the surface of the first wiring layer, excellent initial characteristics and probes can be obtained. Long-term reliability of the pin can be ensured. In addition, by providing a third metal layer with a low volume resistivity between the substrate and the first wiring layer, high-speed signal transmission characteristics above the GHz level are possible.

As described above, the test carrier of the present invention has a structure that enables drastically reducing the cost by reducing the number of parts compared to the conventional carrier. Further, by using the test carrier of the present invention, it becomes possible to perform the same selection and burn-in inspection of a semiconductor device having a fine pitch electrode of 40 micrometer pitch or less as a package product in a bare chip state. . Therefore, using a bare chip The production efficiency of the Sip (System ina Package) structure can be improved and the cost of sacrifice can be greatly reduced. In addition, screening inspection can be performed in the high-frequency region above GHz, which was difficult in the past. Brief Description of Drawings

FIG. 1 is a cross-sectional view showing a test carrier structure according to a first embodiment of the present invention.

FIG. 2 is a diagram showing details of the carrier substrate and the probe portion according to the first embodiment of the present invention. (C) is a detailed view of the probe portion within the dotted line of (a), and (d) is a detailed view of the probe portion within the dotted line of (b).

FIG. 3 is a diagram showing another example of the structure of the probe section.

FIG. 4 is a sectional view showing a test carrier structure according to the second embodiment of the present invention.

FIG. 5 is a diagram showing a carrier substrate manufacturing method according to the present invention.

FIG. 6 is a diagram showing a method for manufacturing a carrier substrate according to the present invention.

FIG. 7 is a view showing a conventional structure described in Patent Document 1. In FIG.

FIG. 8 is a view showing a conventional structure described in Patent Document 2.

FIG. 9 is a view showing a conventional structure described in Patent Document 3.

FIG. 10 is a view showing a conventional structure described in Patent Document 4. In FIG.

FIG. 11 is a diagram showing a conventional structure manufacturing method described in Patent Document 4.

FIG. 12 is a diagram showing a conventional structure described in Patent Document 5. BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)

FIG. 1 is a cross-sectional view showing a first embodiment of the test carrier structure of the present invention, and FIGS. 2 (a) to (d) show details of the carrier substrate and probe portion of the present invention. First, the overall structure of the test carrier according to the present invention will be described with reference to FIG.

As shown in FIG. 1, the test carrier structure according to the embodiment of the present invention Each of the independent lead-shaped probe pins 4 having elasticity at positions corresponding to the external terminal electrodes 2 of the semiconductor device 1 is electrically connected to the probe pins 4 and the first wiring layer of the probe pins 4 6 and a base material 5 formed thereon. A metal protrusion 36 is formed at a portion where the probe pin 4 contacts the electrode 2 of the semiconductor device 1. A second metal layer 18, which is one or more metal layers made of a material having good contact characteristics according to the electrode material of the semiconductor device 1, is formed on the surface of the metal protrusion 36.

It has a second wiring layer 18 that is one or more metal layers formed on the first wiring layer 6 of the substrate 5, and the second metal layer 18 on the surface of the metal protrusion 3 6 and the first metal layer 18. It features a structure in which the second wiring layer 18 is separated.

Furthermore, a carrier lid made up of a holding plate 16 that is a fixing means 14 and an elastic material 17 or a leaf spring 15 that fixes the semiconductor device 1 to the carrier substrate 10 and a carrier lid that is the fixing means 14 are used as the carrier substrate. 10 for fixing to the hook 1 3, the semiconductor electrode 1, and the metal projection 3 of the probe pin 4 3 for the purpose of alignment with the carrier substrate 10 through hole 9 formed in the center of the 0 or the carrier substrate 10 It has a positioning frame 58 formed on the surface.

Next, the materials used and the detailed structure of each part will be described with reference to FIGS. 2 (a) to (d).

The first wiring layer 6 formed on the surface of the substrate 5 is extended in a planar manner from the electrode pitch of the semiconductor device 1 to a pitch that can be connected to the inspection device. The base material 5 suppresses deterioration of pin position accuracy due to thermal history during the manufacture of the carrier substrate 10 and a positional shift between the electrode 2 of the semiconductor device 1 and the probe pin 4 due to a temperature difference during the burn-in test. For the purpose of suppressing this, glass ceramics, glass, and silicon, which are materials with a thermal expansion coefficient close to that of silicon that is widely used as a semiconductor material, are used. Among these materials, it is preferable to use glass ceramics from the viewpoints of processability and electrical characteristics.

The first wiring layer 6 is made of Ni or Ni-based alloy, which is the same material as the first metal layer 11 of the base material portion of the probe pin 4 in consideration of manufacturability. The width of the first wiring layer 6 is set to 50% to 60% of the pitch of the electrodes 2 of the semiconductor device 1 at a level in which no short circuit occurs during manufacturing and no leakage occurs. The thickness is set in consideration of manufacturability. 1

It is equivalent to the thickness of the first metal layer 1 1 of the lobe pin 4.

The second wiring layer 12 is formed on the first wiring layer 6 for the purpose of increasing the conductivity of the wiring portion and reducing the conductor loss. The material is first in the N i Oh Rui a wiring layer 6 N ί alloy with reduced volume resistivity in comparison, in the range of 1~4 x 10- ⁸ Q m metal (e.g., gold, gold Z Copper alloy, gold-palladium alloy, copper). The formation area is the width obtained by subtracting the manufacturing tolerance from the width of the first wiring layer 6 from the position entering the base material 5 side from the boundary between the base of the probe pin 4 and the base material 5 at a manufacturing tolerance of about 2 micrometers. It is formed on the entire surface of the first wiring layer 6. When the width of the first wiring layer 6 is 10 micrometers, it is formed on the entire surface with a width of 8 micrometers.

The probe pin 4 can be manufactured by electroplating and uses a metal having a Young's modulus of 100 GPa or more (for example, nickel, nickel iron alloy, nickel Z cobalt alloy, nickel manganese alloy) as a material. . The width is 50 to 60% of the electrode 2 pitch of the semiconductor device 1, and the thickness and the length can obtain a desired contact pressure within the elastic limit region, and a predetermined overdrive amount (of the semiconductor device The amount by which the semiconductor device is pushed in based on the point at which the electrode contacts the probe pin is referred to as the OD amount (hereinafter referred to as “OD amount”).

The material of the metal protrusion 3 6 that is a contact point with the electrode of the semiconductor device 1 is the base material of the probe pin 4 in consideration of the adhesion with the first metal layer 1 1 except for the second metal layer 1 8. Ni or Ni alloy based on the same material as the first metal layer 11 is used. Of course, other materials having a hardness equal to or higher than Ni can be used. The width (W) of the metal protrusions 3 6 should be less than the width of the probe pins 4. The length (L 2) of the metal projection 3 6 is the amount of movement of the tip of the probe pin 4 after the probe pin 4 contacts the electrode 2 of the semiconductor device 1 and the positional tolerance in the moving direction of the probe pin 4. It is formed in a rectangular shape that is longer than the dimension plus the length considering the electrode tolerance. The height (H 2) of the metal protrusion 3 6 is the amount of pressing after the electrode 2 of the semiconductor device 1 contacts the metal protrusion 3 6 with respect to the surface of the first wiring layer 6 and the height of the metal protrusion 3 6. It should be at least the dimension plus the height in consideration of the height tolerance and the height tolerance of the electrode 2 of the semiconductor device 1.

The surface shape of the metal protrusions 36 is processed into an appropriate structure according to the contact target. When the electrode 2 of the semiconductor device 1 is a gold bump, it has a flat shape with no irregularities. If the surface roughness after electric mating is 0.05 micrometer or less, special processing for forming a flat shape is unnecessary. If the surface roughness is 0.05 micrometer or more, perform surface polishing. When the electrode 2 of the semiconductor device 1 is copper, since a natural oxide film exists on the surface, fine irregularities are formed with a surface roughness of 1 micrometer or less in order to break through this. The shape of the fine irregularities is formed only in the same direction as the moving direction of the probe pin 4 as shown in FIG. 2 (c). Various structures such as a grid shape, a file eye shape, and a random shape formed in a direction perpendicular to the moving direction can be adopted.

A second metal layer 18 is formed on the surface of the metal protrusion 36 to prevent oxidation of the metal protrusion. For example, a gold alloy (AuZPd, Au / Co, AuZCu, etc.) is arranged at a thickness of 0.05 to 3 micrometers.

The through electrode 8 and the third wiring layer 7 are formed on the base material 5, and the third wiring layer 7 is connected by the first wiring layer 6 and the through electrode 8. As a result, contact from the back surface becomes possible, and it becomes possible to cope with sorting inspection that requires high-speed inspection. The dimension of the through electrode 8 is determined by the external terminal pitch of the carrier substrate 10. For example, in the case of a 0.5 mm pitch, it is a ø20-300 micrometer and a length (depth) 200-300 micrometer. The third wiring layer 7 is composed of an N film having a thickness of 20 micrometers or less and an Au plating having a thickness of 2 micrometers or less on the upper layer. The wiring width is 20 to 300 micrometers, and the length is 0.5 to 1. O mm.

The counterbore 21 formed on the base material 5 is necessary to make the probe pin 4 independent, and considering the mechanical strength of the base material 5, the depth is 200 micrometers or more. It is formed in the area where the length of the probe pin 4 is added to the external size of 1.

Either one of the penetrator L 9 formed in the central portion of the base material 5 and the positioning frame 5 8 disposed on the upper surface of the base material 5 may be present. Both are used for alignment between the electrode 2 of the semiconductor device 1 and the metal protrusion 36 of the probe pin 4. When alignment is performed using the external shape of the semiconductor device 1, a positioning frame 58 is disposed. When position detection and correction are performed by image processing and the electrode 2 of the semiconductor device 1 is mounted on the metal protrusion 3 6, For temporary fixing until the fixing means 1 4 is attached, negative pressure is sucked from the through hole 9 in the center of the base material 5. Therefore, both are used properly depending on the electrode pitch of the semiconductor device 1. However, in the fine pitch region, it is preferable to apply the latter optical alignment.

As shown in FIG. 1, the carrier lid serving as the fixing means 14 is composed of a pressing plate 16 and an elastomer 17 or a leaf spring 15 which is an elastic material. It is necessary to determine the material and thickness of the retainer plate 16 so that it will not bend when a load is applied. When using stainless steel, it should be 1. O mm or more. When using resin materials such as polyether imide and polyether sulfone, it should be 2. O mm or more. The size is equal to or smaller than that of the carrier substrate 10.

The elastomer 17 that is in contact with the back surface of the semiconductor device 1 uses a silicone rubber having a thickness of 0.5 to 1. O mm or more, and applies a material having resilience even after a thermal history is applied. It is formed in a region where 1 O mm or more is added to the external size of 1. The material of the leaf spring 15 is carbon steel or beryllium copper. The dimensions are determined by the required pressure. For example, when the probe of the present invention is applied to a gold electrode with a pitch of 20 micrometers and a pin of 1000, an OD amount of 50 micrometers and a contact pressure of 2 O mg are required. A contact pressure of 20 g is required. Therefore, when carbon steel is used as the leaf spring material, the spring constant is 0.3 7 8 K g Zm m, the plate thickness is 0.2 mm, the width is 9 mm, and the length is “!

The latch 13 has a function of fitting and fixing the edge of the holding plate 16 6 by dropping the carrier lid as the fixing means 14. As the material, metals such as carbon steel and beryllium copper, polyethersulfane, polyetherimide, and the like can be used, but it is preferable to use the latter resin material in order to suppress generation of dust. Attach at least two places in the center of the two sides of the carrier substrate 10. Of course, it can be arranged on the diagonal part of two sides, and can be arranged on 3-4 sides.

Next, the dimensions of the first embodiment of the present invention will be described by taking as an example the case where the electrode pitch of the semiconductor device 1 is 20 micrometers.

The width W of the probe pin 4 is the maximum 10 micrometer that does not cause a short circuit due to manufacturing. The pin thickness H1 is 10 micrometers, which can be formed with one electrical contact. The probe pin length L 1 is within the elastic limit when an OD amount of 70 μm is applied to the probe pin 4, and is 400 μm because it is as short as possible to minimize conductor loss and crosstalk noise. Use a meter.

The height H2 of the metal protrusion 36 is set to a minimum of 40 micrometers in consideration of the fact that the semiconductor device 1 and the probe pin 4 do not come into contact with each other and the manufacturing accuracy when the semiconductor device 1 is pushed in by 30 micrometers. The second wiring layer 1 2 formed on the first wiring layer 6 has a manufacturing tolerance from the boundary between the base of the probe pin 4 and the base material 5 and a manufacturing tolerance of 2 micrometers. Formed on the entire surface of 1 wiring layer 6 with a width of 8 micrometers. The length L2 of the second metal layer 18 formed on the surface of the protrusion is necessary for the second metal layer 18 to be in contact with the electrode 2 of the semiconductor device 1 when the indentation amount is 50 micrometers. Considering length 7 micrometer and manufacturing accuracy ± 2 micrometer and position accuracy ± 1 micrometer, 10 micrometer or more is required. The thickness is 2 micrometers in consideration of manufacturability.

In the present invention, it is possible to cope with an ultra fine pitch of 40 micrometer pitch or less, to greatly reduce the number of parts of the test carrier, and to ensure long-term reliability of the probe pin and to have sufficient practicality. It has a big advantage. The reason for having these merits will be described sequentially below.

There are mainly three reasons why the test carrier of the present invention can handle electrode pitches of 40 micrometers or less. The first point is that the substrate 5 is made of a material with a smaller thermal expansion coefficient than PI (polyimide film) such as glass ceramics, glass, and silicon, thereby preventing deterioration in accuracy in the thermal history of the manufacturing process. It can be done. The second point is that a sufficient level of contact pressure can be secured because a certain level of thickness can be secured with a very fine pin width by applying electrical technology. For example, a pin thickness of 10 micrometers can be formed with a pin width of 10 micrometers. The third point is that the reprobe pin and the wiring layer on the substrate can be formed by the additive method by applying micromachine technology.

There are two reasons why the number of parts can be reduced. The first point of the present invention is that each of the independent lead-shaped probe pins 4 includes a semi- Since a metal layer with good contact characteristics is formed according to the electrode 2 of the conductor device 1, stable contact characteristics can be secured at low contact pressure. Therefore, since the amount of OD for ensuring contact can be reduced, the carrier lid structure as the fixing means 14 can be greatly simplified. For example, if the probe pin 4 of the 20 micrometer pitch, width 10 micrometer, thickness 10 micrometer is used, and the electrode material of the semiconductor device 1 is gold / compress, the OD amount is 10 micrometer, 3 0 (micro); Good contact can be obtained under the contact condition of a pin. Therefore, the OD amount can be set to 30 micrometers in consideration of the parallelism between the semiconductor device 1 and the test carrier and the height variation of the metal protrusion 36 at the tip of the probe pin. Conventionally, since a high contact pressure is required, a structure has been adopted in which several springs are arranged on the carrier lid as a fixing means. However, the lid structure, which is the fixing means 14 of the present invention, can be composed of two parts: a pressing plate 16 that is a supporting member and an elastomer 17 or a leaf spring 16.

Second, the probe pins 4 of this configuration can be independently deformed. Therefore, the probe pin 4 itself can absorb the height variation of the metal protrusion 36 at the tip of the probe pin 4 and the parallelism variation between the semiconductor device 1 and the test carrier. Therefore, there is no need to place an elastomer on the lower surface of the membrane sheet as in the case of a carrier using a conventional membrane sheet with bumps, and a three-point component consisting of a sheet, elastomer, and base is placed on one point on the carrier substrate 10. Can be configured. As a result, the cost can be reduced by reducing the number of parts.

The reason why the long-term reliability of the probe pin can be secured is that the second wiring layer 1 formed on the second metal layer 18 and the first wiring layer 6 formed on the surface in contact with the electrode 2 of the semiconductor device 1 This is because the probe pin 4 except for the second metal layer 18 is separated into a single elastic material.

Also, by providing the metal protrusion 3 6 at the contact portion of the semiconductor device 1 with the electrode 2, when the semiconductor device 1 is pressurized by the solid means 14, only the electrode 2 portion of the semiconductor device 1 is exposed to the metal protrusion 3 6. Can be contacted with. When the metal protrusion 3 6 is not provided or a metal layer with a small thickness is provided, the contact pressure is reduced because the probe pin 4 is in contact with the portion other than the electrode 2 portion of the semiconductor device 1. For this reason, the amount of OD increases, and even if initial contact can be secured, it will lead to deterioration of long-term reliability. Therefore, metal protrusion 3 6 This is a very effective means that can achieve stable contact with a small amount of OD and maintain long-term reliability.

Next, other structural examples of the probe section will be described with reference to FIG.

The difference from the probe structure of FIG. 2 is that a third metal layer 19 is provided between the first wiring layer 6 and the base material 5. The third metal layer 1 9, first low volume resistivity compared to N i or N i based alloy which is a wiring layer 6, in the range of 1~4 x 10- ⁸ Q m metal (e.g., Gold, gold / copper alloy, gold / palladium alloy, copper) are used as materials. With this structure, higher conductivity can be obtained compared to the probe structure of FIG. For this reason, the conductor loss during high-speed signal transmission can be reduced, and the signal transmission characteristics can be dramatically improved. This structure is effective when signal transmission of 1 GHz or higher is required. In the case of 1 GHz or less, sufficient signal transmission characteristics can be obtained with the probe structure shown in Fig. 2.

(Second embodiment)

FIGS. 4 (a) to (c) are diagrams showing a test carrier structure according to the second embodiment of the present invention.

This embodiment shows a carrier substrate structure when the electrodes of a semiconductor device are in a staggered arrangement. When the arrangement of the external electrodes of the semiconductor device is a staggered arrangement, the length of the probe pin 4 corresponding to the inner peripheral electrode L3 and the length of the probe pin 4 corresponding to the outer peripheral electrode when the carrier substrate structure shown in Fig. 2 is applied. L 4 is different, so the contact pressure of probe pin 4 is different. That is, the probe pin 4 corresponding to the inner peripheral electrode has a longer pin length than the probe pin 4 corresponding to the outer peripheral electrode, and the contact pressure of the probe pin 4 corresponding to the inner peripheral electrode is reduced. Therefore, even if good contact is obtained with respect to the outer peripheral electrode, high resistance due to insufficient contact pressure may occur with respect to the inner peripheral electrode.

On the other hand, when the pressing amount is set so as to obtain good contact with the inner peripheral electrode, the contact pressure with respect to the outer peripheral electrode becomes high. As a result, there is a possibility that the life of the probe pin 4 corresponding to the outer peripheral electrode is shortened by the stress acting on the base of the probe pin 4 due to repeated probing. Therefore, as shown in FIG. 4 (b), the width of the metal layer of the probe pin base portion 22 corresponding to the inner peripheral electrode is increased to have a protruding shape. Alternatively, as shown in FIG. 4 (c), a pro A structure 23 projecting in the direction of sitting on the base material part of the buppin 4 is adopted. As a result, the pin length L 3 of the probe pin 4 corresponding to both the inner peripheral electrode and the outer peripheral electrode is set to the same length, and the contact pressure can be kept uniform. According to the present embodiment, the contact reliability of the probe pins 4 corresponding to both the inner and outer peripheral electrodes can be maintained relatively easily and uniformly.

In the present embodiment, the case where the arrangement of the electrodes of the semiconductor device is a staggered arrangement has been taken up, but the same technique can be adopted in the case of another arrangement of electrodes such as three rows or four rows.

(Carrier substrate manufacturing method)

Next, a manufacturing method of the carrier substrate structure used in the test carrier of the present invention shown in FIGS. 1 and 2 will be described in detail with reference to FIGS.

Prepare an insulating material such as glass ceramics or glass with the desired dimensions as the base material 5, and form a seating part 21 that sits at a depth of 200 micrometers or more in the area of the chip size plus the probe pin length (See Fig. 5 (a) and (b)).

The desired dimensions of the substrate 5 are equivalent to the device package size. For example, in the case of a 64M flash memory (P D 29 F064 1 1 5), the outer size is 1 2 X 2 Omm and the outer peripheral terminal pitch is 0.5 mm. By using an external size equivalent to the package size of existing devices, conventional inspection equipment can be used as is. For this reason, cost reduction can be achieved.

After this, there is a YAG (Yttrium Aluminum Garnet) laser of 355 nm wavelength high-power LD (Laser Diode) excitation type, or RIE (Reactive Ion Etching). It is formed in an area larger than a micrometer (see Fig. 5 (c)).

Next, a copper seed layer 25 is formed on the entire surface with a thickness of 100 to 300 nm by plasma CVD (Chemical Vapor Deposition) or sputtering (see Fig. 5 (d)). After that, the copper layer as the sacrificial layer 26 is completely filled by electrical contact with the countersink part 21 and the through-hole 24 part (see Fig. 5 (e)).

When the hole is completely filled, naturally, a copper layer of several to several tens of meters is deposited on the surface, so CMP (Chemical Mechanical The copper layer deposited on the surface is removed by a polishing method to form a flat state. Subsequently, a copper seed layer 25 having a thickness of about 0.3 μm was formed on the exposed surface of the sacrificial layer 26 and the through electrode 8, and a resistor 28 was added to the thickness of the 20 micrometer on this surface. Glue or apply with. Thereafter, a shape in which the resist 28 in the portion corresponding to the probe pin 4 and the first wiring layer 6 is removed is formed using photolithography of exposure and development (see FIGS. 5 (f) to (h)).

Then, a first metal layer 11 and a first wiring layer 6 having elasticity are grown in this recess by electroplating (see FIG. 5 (ί)).

Subsequently, the resist 28 and the metal surface are polished so that they are flush with each other, and a 20 micrometer-thick resist 28 is applied to the surface, exposed, and developed, so that the metal protrusion 36 is formed. A recess is formed (see Fig. 5 (j) to (k)).

Next, the first metal layer 11 is formed in this recess by staking (see FIG. 5 (I)). Furthermore, by repeating this process twice, a metal protrusion 36 having a height of 40 micrometers or more can be secured. In addition, when the height of the metal protrusion 36 or more of 40 micrometers or more is required, the height can be increased sequentially by repeating the process of embedding by forming the recess and fitting.

Next, the process of polishing the surface of the protruding portion is started. At this stage, the contact method is used, and the processing method is selected according to the electrode material of the semiconductor device 1. When the contact target is a gold electrode or a gold bump, the surface is polished by CMP (Chemical Mechanical Polishing) to ensure that the surface roughness is 0.05 micrometer or less. In the case of copper electrodes or copper bumps, a concavo-convex structure of 0.1 to 0.7 micrometers is provided on the metal protrusion surface layer after the CMP process.

An example of the unevenness forming method will be described. Prepare a # 2000 wrapping sheet (abrasive paper) with fine metal particles, and move it about 50 times in the region between the tip of probe pin 4 and 300 micrometers in the direction of probe pin movement. In this way, an uneven structure of 0.1 to 0.7 micrometers can be provided. As another method for forming irregularities, it is also possible to use a ceramic material having an appropriate porosity or a silicon substrate on which appropriate irregularities are formed in advance.

The uneven shape is not only the direction of movement of the probe pin 4, but also the direction perpendicular to the movement direction. Various formations such as a board shape, an oblique shape, a file eye shape, and a random shape can be adopted. This fine unevenness can break through the natural oxide film on the copper surface and achieve stable contact. ,

Subsequently, a resist 28 is applied, a recess is formed by exposure and development, and a second metal layer 18 is formed to a thickness of 0.01 micrometer or more by plating. As a result, the influence of the oxide film on the Ni or N alloy, which is the first metal layer 11, can be eliminated. For this reason, more stable contact can be realized.

When this step is completed, the back surface of the carrier substrate is processed. First, using a grinder, thin the substrate 5 until the thickness of the substrate 5 reaches about 2500 micrometers. If necessary, dry etching is performed to remove the damaged layer (see FIGS. 5 (m) to (n) and FIGS. 6 (a) to (b)).

Next, a copper seed layer 25 of about 0.3 micrometers is formed on the entire back surface where the through electrode is exposed by sputtering. A resist 28 having a thickness of 20 micrometers is applied to the surface, and a concave shape is formed by removing the resist 28 corresponding to the second wiring layer 7 by exposure and development. A Ni or Ni alloy having a thickness of 5 to 15 micrometers is formed in the recess by electroplating (see Fig. 6 (c) to (d)).

Subsequently, an Au or Au alloy plating is formed on the surface layer by electroless plating with a thickness of not less than 0.01 micrometer. Next, the resist layer and seed layer on the front surface are removed by wet etching and milling, respectively, and the resist layer and seed layer on the back surface are also removed in the same manner. Finally, the sacrificial layer is removed by wet etching, so that the second surface of the surface of the probe pin and the metal protrusion 36 having a metal protrusion shape having a material and a structure having good contact characteristics according to the contact target is provided. A carrier substrate structure in which the metal layer 18 and the second wiring layer 12 formed on the surface layer of the first wiring layer 6 are separated can be obtained (see FIGS. 6 (e) to (m)). . Industrial applicability

The test carrier of the present invention has a structure that enables a dramatic reduction in cost by reducing the number of parts compared to a conventional carrier. In addition, by using the test carrier of the present invention, a semiconductor device having a fine pitch electrode having a pitch of 40 micrometers or less is used. Conductor devices can be sorted and burned-in in the bare chip state equivalent to package products. Therefore, it can be suitably used as a Sip (System ina Package) using a bare chip.

Claims

1. In a test carrier for carrying out an inspection by holding the semiconductor device in a bare chip state and electrically connecting it to the inspection device,

An elastic probe pin provided at a position corresponding to the external electrode of the semiconductor device; and fa.

A first wiring layer electrically connected to the probe pin and formed on a substrate; a metal protrusion formed on a portion where the probe pin contacts an external electrode of the semiconductor device;

A metal layer formed on a surface of the metal protrusion;

A second wiring layer formed on the first wiring layer,

A test carrier characterized in that the metal layer and the second wiring layer are separated.

2. The test bag carrier according to claim 1, further comprising a fixing means for fixing the semiconductor device to the base material.

3. The test carrier according to claim 1, wherein the metal layer has contact characteristics according to a material of an external electrode of the semiconductor device.

4. A through electrode penetrating between the front surface and the back surface of the base material and a third wiring layer formed on the back surface of the base material, and the first wiring layer and the third wiring layer are formed through the through electrode. 2. The test carrier according to claim 1, wherein the wiring layer and the wiring layer are electrically connected.

5. The test carrier according to claim 1, wherein a volume resistivity of the second wiring layer is smaller than a volume resistivity of the first wiring layer.

6. Another metal layer is formed between the first wiring layer and the substrate. The test carrier according to claim 1.

7. The test carrier according to claim 6, wherein the volume resistivity of the other metal layer is smaller than the volume resistivity of the first wiring layer.

8. The metal protrusion formation area has a width direction that is less than or equal to the probe pin width, and the length direction is the amount of movement of the probe pin tip and the probe pin longitudinal direction after the probe pin contacts the external electrode of the semiconductor device. It is a rectangular shape that is more than the dimension plus the length considering the position tolerance and external electrode tolerance of the semiconductor device,

The height is based on the surface of the first wiring layer, and the amount of indentation after the external electrode of the semiconductor device contacts the metal protrusion, the height tolerance of the metal protrusion, and the height tolerance of the external electrode of the semiconductor device are taken into account 2. The test carrier according to claim 1, wherein the test carrier has a dimension equal to or greater than a height obtained by adding the measured height.

9. The length of the probe pin corresponding to each external electrode of the semiconductor device is the same when the external electrode of the semiconductor device is arranged other than the single row peripheral arrangement. The test carrier described.

10. When the external electrode of the semiconductor device is arranged other than the single row peripheral arrangement, the base of the base portion of the probe pin corresponding to the external electrode existing on the center side of the semiconductor device has a protruding shape. The test carrier according to claim 9, wherein:

1 1. When the external electrode of the semiconductor device is arranged other than the single-row peripheral arrangement, the probe pin root portion corresponding to the external electrode existing on the center side of the semiconductor device and the first wiring layer on the substrate 10. The test carrier according to claim 9, wherein the width of the test piece is wider than both the probe pin corresponding to the external electrode existing outside the semiconductor device and the first wiring layer, and has a protruding shape. .

1 2. The metal layer on the surface of the metal protrusion is made of a gold alloy metal. The test carrier according to claim 1.

13. The test carrier according to claim 1, wherein the metal layer on the surface of the metal protrusion has a fine uneven shape.

14. The test carrier according to claim 13, wherein the fine uneven shape is formed only in the same direction as the moving direction of the probe pin.

15. The test carrier according to claim 13, wherein the fine uneven shape is formed only in a direction perpendicular to a moving direction of the probe pin.

16. The test carrier according to claim 13, wherein the fine uneven shape is formed in a grid shape, a file shape, or a random shape.

17. The test carrier according to any one of claims 13 to 16, wherein the fine ω-convex shape is an uneven shape having a surface roughness of 1 micrometer or less.

18. The test carrier according to claim 1, wherein a through hole is provided in a central portion of the base material.

19. The test carrier according to claim 18, wherein a shape of the through hole is the same as or smaller than an opening diameter of a base portion of the probe pin.