KR101638228B1 - Fabrication method of probe pin capable of being used for fine pitch - Google Patents

Abstract

The probe pin of the present invention includes a probe beam region connected to a circuit pattern of a probe substrate and a probe tip region contacted with a contact pad of a semiconductor element, wherein the probe beam region includes a first metal pattern in the form of a strip, A second metal pattern stacked on the first metal pattern and having a length greater than that of the first metal pattern and a third metal pattern stacked on the second metal pattern and having substantially the same length as the first metal pattern And the probe tip region has a two-dimensional structure formed integrally protruding from the front end of the second metal pattern toward the contact pad. According to the structure of the present invention as described above, inspection can be performed in response to the fine pitch of the semiconductor element.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a probe pin,

In order to avoid interference between neighboring probe pins while maintaining the thickness of the probe body in order to maintain a predetermined tension, restoring force, elasticity, mechanical strength, and the like, the probe tip has a thickness corresponding to a fine pitch A plurality of metal patterns having a predetermined thickness are sequentially stacked using a MEMS process, and the length of the metal pattern including the probe probe is made longer than the lengths of the other metal patterns, And more particularly, to a probe manufacturing method for easily adjusting the thickness of a probe body in an interval corresponding to a fine pitch using an electroplating process or a deposition process.

Generally, the process of manufacturing a semiconductor device is composed of several steps. In the final stage of assembling a semiconductor device, a plurality of semiconductor chips fabricated to form an individual integrated circuit (IC) on a wafer, Only the good chip except the chip is selected and assembled.

Therefore, in order to determine whether the semiconductor chips on the wafer are good or defective before assembly, a probe card directly connected to the semiconductor inspection apparatus is directly contacted with each semiconductor chip to check its performance electrically.

Such a semiconductor inspection apparatus includes a tester, a prober, and a prober, which are kind of computer apparatuses for generating inspection signals and detecting and analyzing response signals received as a result to discriminate between the semiconductor chips. And a probe card for electrically connecting the tester and the semiconductor chip to be inspected in the middle.

The probe card transmits electrical signals between the tester and the semiconductor device being inspected. To this end, the probe card includes a plurality of microprobe (probe) spaced at a pitch corresponding to the connection terminals so as to be contactable with a contact pad formed to be exposed to the outside on the semiconductor element during the inspection, And a substrate assembly that physically fixes the microprobe and electrically connects the microprobe and the tester.

A plurality of fine probes are provided on the surface of the substrate assembly corresponding to the contact terminals of the semiconductor element in the vertical direction and contact the contact pad on the semiconductor element during inspection to transmit an electrical signal of the inspection signal and the response signal.

On the other hand, recent semiconductor devices tend to be highly compact and miniaturized at the same time as the design rules are becoming finer. In order to inspect such semiconductor devices, a suitable inspection apparatus is required.

For example, in order to be connected to various patterns of a semiconductor element to be fine, the probe pins of the probe card must be miniaturized and miniaturized to an appropriate size corresponding to the pattern.

Therefore, conventionally, the probe pins of the probe card have been appropriately dealt with the change in the technology of the semiconductor while fabricating the blade type of the wire type having a predetermined diameter and finely processed by etching or the like of the thin plate.

Referring to FIGS. 1A and 1B, the probe card includes a plurality of probe pins 2. In a situation where the semiconductor device is currently being reduced to submicron or smaller, the contact pad 4 of the wafer chip is reduced Research and development for miniaturization of the probe probe 6 contacting the contact pad 4 is actively underway.

On the other hand, if the width of the probe probe 6 is narrowed so as to correspond to a fine pitch, the thickness of the probe body 8 can be reduced corresponding to the fine pitch. That is, as the pitches of the contact pads 4 formed on the semiconductor elements become narrower, the thicknesses of the probe probes 6 and the probe bodies 8 become thinner.

This causes various problems in the process of picking up or handling the probe body 8. For example, if the thickness of the probe body 8, which is provided by transferring the probe body 8 to the probe substrate using a pickup device (not shown), is too thin, the probe body 8 may not be easily picked up, But is bent (deformed). For example, if the thickness of the probe is less than a certain thickness due to the characteristics of the probe material, an unstable state may occur without bending the linear structure.

On the other hand, if the probe body 8 is formed thick so that it can be easily handled, there is no space between adjacent probe bodies 8, which makes it very difficult to use the pickup device.

1A and 1B show the case where interference occurs in a section where the probe body 8 contacts the contact pad 4 when the pitch of the contact pad 4 of the semiconductor element is reduced from "Pa" to "Pb" . At this time, it can be seen that a section in which interference occurs is a section in contact with the contact pad 4.

Referring to FIG. 2, in order to arrange a plurality of vertical probes in array units corresponding to the fine pitch as the contact pads 4 of the wafer chip are reduced to a fine pitch, A technique of processing a probe probe 6 into a pyramid shape using a wet etching method or a mechanical polishing method is disclosed in Japanese Patent Laid-Open No. 10-0670999.

However, there is a problem that the tapping process of the probe probe 6 is very complicated and difficult, requires a long processing time, and is difficult to assemble the probe card. In addition, the above-described probe tip processing and the vertical probe card arrayed in this array are not suitable for testing wafers in which chip pads are arranged in a straight line.

Patent Document 1:

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a probe having a probe pin array structure that secures a necessary minimum gap between adjacent probe pins, And a manufacturing method thereof.

Another object of the present invention is to provide a probe having a thickness corresponding to a fine pitch having a thickness capable of maintaining mutual interference in a section corresponding to a fine pitch in a section where a bar- And a method for producing the same.

It is still another object of the present invention to provide a probe corresponding to a fine pitch for manufacturing a probe pin in a two-dimensional or three-dimensional structure using a MEMS process and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a probe card including a probe card having a plurality of probe pins corresponding to contact pads of fine pitch formed in a semiconductor device, Wherein the probe pin includes a probe block coupled to and supported by the probe card, a probe body resiliently supported on the probe block, and a probe probe in contact with the contact pad, And the probe blocks are arranged alternately in a zigzag shape so as to face each other with respect to the straight line on the basis of the straight line, and the probe probe is installed at the front end of the probe body, The thickness of the section that interferes with the probe tip is defined as the remaining straight line Is smaller than the thickness of the section where the structure is maintained.

According to another aspect of the present invention, a probe pin of the present invention includes a probe beam region connected to a circuit pattern of a probe substrate, and a probe tip region contacted with a contact pad of a semiconductor device, A second metal pattern stacked on the first metal pattern and having a length greater than that of the first metal pattern and a second metal pattern stacked on the second metal pattern and being substantially identical to the first metal pattern And the probe tip region has a two-dimensional structure integrally protruding from the front end of the second metal pattern toward the contact pad.

As described above, according to the configuration of the present invention, the following effects can be expected.

First, even when the pitch of the contact pad of the semiconductor device is reduced, the thickness of the conventional probe pin is maintained and the thickness of the contact pin is only reduced in a part of contact with the contact pad. Therefore, the linear structure of the yield strength, The characteristics of the existing probe material can be preserved.

Secondly, the effect of maximizing the efficiency of the probe pin array structure arranged in a staggered manner so that the probe bodies are opposed to each other in order to secure a space between neighboring probe bodies can be expected by thinning the thickness only in a certain section where interference occurs .

1A and 1B are plan views of a probe pin array structure according to the prior art.
2 is a partial perspective view of a probe pin according to the prior art;
3 is a perspective view of a three-dimensional structure of a probe pin according to the first embodiment of the present invention.
4 is a plan view of a multiple probe pin array structure according to a first embodiment of the present invention;
5 is a perspective view of a two-dimensional structure of a probe pin according to a second embodiment of the present invention.
6A to 6C are perspective views illustrating the manufacturing process of FIG.
7A to 7C are perspective views illustrating the manufacturing process of FIG. 5. FIG.

Brief Description of the Drawings The advantages and features of the present invention, and how to achieve them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

Embodiments described herein will be described with reference to plan views and cross-sectional views, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are produced according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, preferred embodiments of a probe corresponding to a fine pitch according to the present invention having the above-described structure will be described in detail with reference to the accompanying drawings.

3, the probe pin 100 of the present invention includes a probe block 110 coupled to and supported on a probe substrate 10, a probe body 120 resiliently supported on the probe block 110, And a probe probe 130 installed at a front end of the probe.

Referring to FIG. 4, the plurality of probe pins 100 have an array structure alternately arranged in a zigzag shape in order to minimize interference even in a straight section of the probe body 120. For example, the contact pads 4 of the semiconductor devices are arranged in series on a straight line, and the probe probes 130 of each probe pin 100 are aligned on a straight line corresponding to the fine pitch of the contact pads 4 However, the probe blocks 110 may have an array structure in which the probe blocks 110 are alternately arranged in a zigzag shape so as to face each other at both sides with respect to the straight line. As a result, a space can be secured between the adjacent probe pins 100.

3 and 4, the probe body 120 maintains the existing thickness d1 in the section L in which the linear structure is to be maintained, while the section P in which the probe pitches And has a thickness d2 smaller than the existing thickness d1 in order to avoid mutual interference with the neighboring probe probes 130. [ The thickness d2 may be reduced to ½ to ¼ (preferably ⅓) of the thickness d1. It is because interference is generated only in the section P in which the thickness d1 of the existing probe body is reduced to the small thickness d2 only in the section P necessary for real pitch pitch correspondence.

The probe substrate 10 may be a circuit board having a predetermined thickness, as is well known. For example, a ceramic substrate. The probe substrate 10 may also include a substrate assembly. On the other hand, the circuit pattern formed on the probe substrate 10 is not essential for understanding the present invention, so the circuit pattern is omitted from the drawing.

In addition, the probe substrate 10 can constitute a probe card for discriminating and inspecting the electrical characteristics or defects of the semiconductor devices by using electrical contact with the probe pins 100. For example, the probe card may include a probe substrate 10 having a circuit pattern densified and a plurality of probe pins 100 electrically connected to the circuit pattern.

The probe block 110 is a rectangular block, one surface of which is coupled to a circuit pattern of the probe substrate 10, and the other surface thereof is integrally connected to the probe body 120. The probe block 110 may be bonded to the probe substrate 10 through various methods such as solder bonding or intermetallic bonding.

The probe body 120 is made of an electrically conductive metal material, like the probe block 100. The probe body 120 is formed in a bar shape and extends from the probe block 110 in a state of being substantially parallel to the probe substrate 10. The probe body 120 is integrally formed with the probe probe 130 and provides an elastic force to the probe probe 130 when the probe probe 130 contacts the contact pad 4 of the semiconductor element . This elastic force serves to prevent physical damage that may occur in the contact pad 4 of the semiconductor device and to maintain a good contact state.

The probe pin 100 of the present invention can be positively and negatively affixed to the fine pitch of the contact pad 4 of the integrated circuit (IC) chip, because the probe body 120 is formed to a small size of several tens of micrometers using the MEMS process .

However, since the probe pin 100 repeatedly comes into mechanical contact with the wafer, the probe body 120 constituting the body of the probe pin 100 must have high yield strength, high restoring force, and high mechanical elasticity. Therefore, there is a certain limit in reducing the thickness of the probe body 120.

The probe probe 130 extends at the front end of the probe body 120 and protrudes in a direction opposite to the probe block 110. The probe probe 130 is a portion in direct contact with the contact pad 4 of the semiconductor device and the probe tip 130 may be formed to have a smaller cross sectional area than the contact pad 4 of the semiconductor device. Since probe probe 130 is in direct contact with contact pad 4, it must have high wear resistance and low electrical resistance.

Referring to FIG. 5, the probe pin 200 of the present invention may be formed in a two-dimensional structure. The probe pin 200 includes a probe beam region B connected to the circuit pattern of the probe substrate 10 and a probe tip region T electrically contacting the contact pad 4 of the semiconductor device.

The probe beam region B includes a probe block 210 coupled to the circuit pattern and a probe body 220 elastically supported on the probe block 210. The probe tip region T is composed of a probe tip 230 electrically connected to the contact pad 4.

The probe beam region B includes a strip-type first metal pattern B1, a second metal pattern B2 that is longer than the first metal pattern B1, The probe tip region T is integrally protruded from the front end of the second metal pattern B2 in the direction of the contact pad although it includes a third metal pattern B3 having substantially the same length as the first metal pattern B1 . The first metal pattern of the two-dimensional structure to the third metal patterns B1 to B3 are sequentially stacked to form the probe pin 200.

Hereinafter, a method of manufacturing the probe pin 100 of the three-dimensional structure shown in FIG. 3 according to the first embodiment of the present invention will be described with reference to the drawings.

Meanwhile, although the probe pins 100 and 200 having the three-dimensional structure or the two-dimensional structure to be described below are shown as a single unit for the sake of convenience of illustration, they may be manufactured in plural by the MEMS process.

Referring to FIG. 6A, a seed layer (not shown) is formed on a sacrificial substrate 102, and then a first photoresist (not shown) is applied to a predetermined thickness. Then, A conductive metal is filled using a plating or other deposition method to pattern the probe block (bump 110). At this time, the upper surface of the probe block 110 can be planarized by chemical mechanical polishing (CMP) or the like.

6B, a conductive thin film is deposited on the first photoresist and the probe block 110, the second photoresist is applied to a predetermined thickness, and a predetermined region is etched away to expose at least the probe block 110 do. The conductive thin film is plated with the seed layer in the removed region, and the probe body (120) is patterned. The pattern forming process of the probe body 120 may be repeated one or more times as needed.

6C, a third photoresist is coated on the probe body 120 to a predetermined thickness, a photolithography process is performed to expose a part of the front end of the probe body 120, and then a conductive metal And the probe tip 130 is patterned.

Hereinafter, a method of manufacturing the probe pin 200 of the two-dimensional structure shown in FIG. 5 according to the second embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 7A, a trench (not shown) is formed on the sacrificial substrate 202 through anisotropic etching. The sacrificial substrate 202 may be a silicon wafer substrate. Anisotropic etching may be a reactive ion etching process. A first seed layer (not shown) is formed on the sacrificial substrate 202 and a first photoresist pattern (not shown) is formed on the sacrificial substrate 202 except for the trenches. A first metal pattern (B1) is formed on the first seed layer using a plating method using the first photoresist pattern as a mask. The first photoresist pattern may be removed and a planarization process may be performed.

Referring to FIG. 7B, a second photoresist pattern exposing the first metal pattern B1 and having a length longer than the first metal pattern is formed. A second seed layer (not shown) is formed on the first metal pattern B1 and the second photoresist pattern, and the second seed layer (not shown) is formed on the second photoresist pattern using the second photoresist pattern The second metal pattern B2 may be electroplated or physical / chemical vapor deposited on the first metal pattern B1.

Referring to FIG. 7C, a portion of the second metal pattern B2 is exposed. The first metal pattern B1 has substantially the same length as the first metal pattern B1, and protrudes from the front end portion toward the contact pad 4, T) is formed. A third seed layer (not shown) is formed on the second metal pattern B2 and the second metal pattern B2 is formed using a plating method using the third photoresist pattern (not shown) The third metal pattern B3 may be electroplated or physical / chemical vapor deposited. The second and third photoresist patterns are removed. Finally, the first to third metal patterns (B1 to B3) are separated from the sacrificial substrate (202).

The thus manufactured blob pin 200 may be fixed to the circuit pattern of the probe substrate 10 by applying a solder cream, and then soldering or the like.

As described above, according to the present invention, in order to maintain the predetermined tension, the thickness of the probe body is adjusted so as to correspond to the fine pitch in order to avoid interference between neighboring probe pins, As shown in FIG. Many other modifications will be possible to those skilled in the art, within the scope of the basic technical idea of the present invention.

100, 200: probe pin 110, 210: probe block
120, 220: probe body 130, 230: probe probe
B: probe beam area T: probe tip area
B1 to B3: first to third metal patterns

Claims (8)

delete delete delete delete delete delete Forming a seed layer on the sacrificial substrate; applying a first photoresist to the seed layer to a predetermined thickness; etching a predetermined region to expose the sacrificial substrate; filling the conductive metal with a plating process; ; ≪ / RTI >
Depositing a conductive thin film on the first photoresist and the probe block, applying a second photoresist to a predetermined thickness, etching a predetermined region to expose at least the probe block, Patterning the probe body using a plating process using the seed layer as a seed layer; And
A third photoresist is applied on the probe body to a predetermined thickness, a photolithography process is performed to expose a part of the front end of the probe body, a probe tip is patterned using a conductive metal plating process on the etched area, Wherein the step of forming the three-dimensional structure comprises the steps of: Forming a trench through anisotropic etching on the sacrificial substrate and forming a first seed layer on the sacrificial substrate;
Forming a first photoresist pattern on the sacrificial substrate except for the trench and forming a first metal pattern on the first seed layer using a plating process using the first photoresist pattern as a mask;
Removing the first photoresist pattern and performing a planarization process;
Forming a second photoresist pattern exposing the first metal pattern and having a length greater than that of the first metal pattern, and forming a second seed layer on the first metal pattern and the second photoresist pattern;
Forming a second metal pattern on the first metal pattern using a plating process using the second photoresist pattern as a mask;
Forming a third photoresist pattern exposing a portion of the second metal pattern, the third photoresist pattern having the same length as the first metal pattern and having a tip region protruding from the front end to be in contact with the contact pad of the semiconductor element, Forming a third seed layer on the metal pattern;
Forming a third metal pattern on the second metal pattern using a plating process using the third photoresist pattern as a mask; And
And removing the second and third photoresist patterns and separating the first metal pattern to the third metal pattern from the sacrificial substrate.

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