WO2006021907A1 - Semiconductor device and method of manufacturing such a semiconductor device - Google Patents

Semiconductor device and method of manufacturing such a semiconductor device Download PDF

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Publication number
WO2006021907A1
WO2006021907A1 PCT/IB2005/052647 IB2005052647W WO2006021907A1 WO 2006021907 A1 WO2006021907 A1 WO 2006021907A1 IB 2005052647 W IB2005052647 W IB 2005052647W WO 2006021907 A1 WO2006021907 A1 WO 2006021907A1
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Prior art keywords
metal
conducting material
region
channel
semiconductor device
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PCT/IB2005/052647
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French (fr)
Inventor
Jacob C. Hooker
Robert Lander
Robertus A. M. Wolters
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Koninklijke Philips Electronics N.V.
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Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP05773554A priority Critical patent/EP1784856A1/en
Priority to JP2007529060A priority patent/JP2008511149A/en
Publication of WO2006021907A1 publication Critical patent/WO2006021907A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Definitions

  • the invention relates to a semiconductor device with a substrate and a semiconductor body comprising a first field effect transistor with a first source and drain region and a first channel of a first conductivity type and with separated from the first channel by a first dielectric region a first gate region comprising a first conducting material and a second field effect transistor with a second source and drain region and a second channel of a second, opposite to the first, conductivity type and with separated from the second channel by a second dielectric region a second gate region comprising a second conducting material different from the first conducting material, wherein the first and second conducting material comprise a compound containing both a metal and a further element.
  • CMOS Complimentary Metal Oxide Semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • metals or metal alloys that are suitable for the former of which the workfunction is about 4.2 eV are Ru, Zr, Nb, Ta, MoSi and TaSi.
  • Ru, Zr, Nb, Ta, MoSi and TaSi having a workfunction of about 5.2 eV Ni, RuO2, MoN and TaN are suitable material among others.
  • a drawback of the known conducting materials is that they are not always very compatible with existing IC technology. This includes the requirement that the materials should be compatible with the materials of the gate stack comprising the materials of the gate dielectric, the capping layer and the spacers. It is therefore an object of the present invention to avoid the above drawbacks and to provide a device which is very compatible with IC technology and easy to manufacture.
  • a device of the type mentioned in the opening paragraph is characterized in that the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and the second conducting material comprises oxygen as the further element and the first conducting material comprises a chalcogenide as the further element.
  • the chalcogenides comprise the elements S, Se and Te.
  • the material contains a metal that is very common in present IC technology, e.g. for conduction tracks and in particular for use a connection between conduction tracks at different levels.
  • the further elements in a device according to the invention provide several advantages.
  • Molybdenum is chosen as the metal and Tellurium are chosen as the chalcogenide. Good results are obtained with these elements.
  • Te was implanted into a molybdenum film, the workfunction of the resulting material was very close to 4.1 eV, and thus very suitable for use in a NMOST.
  • Molybdenum oxide with an oxygen subscript of 2 or less, results in a work function material very close to 5.2 and thus is very suitable for use in a PMOST.
  • the preferred metal element is molybdenum.
  • the first and second gate region comprises on top of the first and second conducting material a region of another material which is electrically conducting and acting as a barrier to silicon.
  • the another material comprises a metal nitride like titanium nitride.
  • Other metal nitrides like a tantalum nitride could be used as well. This promotes an efficient manufacturing of the device.
  • molybdenum is chosen as the metal and tellurium is chosen as the chalcogenide.
  • a first modification is characterized in that on the first and second dielectric regions a layer of the metal is formed which is at the location of the first dielectric region implanted with ions of the chalcogenide while the layer of the metal is protected at the location of the second dielectric region against the implantation by a mask.
  • Another modification is characterized in that on the first and second dielectric regions a layer of metal is formed which is at the location of the second dielectric region made to react with oxygen while the layer of the metal at the location of the first dielectric region is protected against the oxygen by a further mask.
  • both modifications allow for an easy forming of the two conducting materials.
  • the implantation is done before the oxidation.
  • the oxidation apparatus can be used to anneal both materials, with minimum delay. Only the atmosphere in the apparatus has to be made inert and another desired temperature cycles has to be programmed. Such features can easily be incorporated. A local oxidation can easily be performed using a mask like silicon nitride.
  • FIGs. 1 through 4 are sectional views of an example of a semiconductor device according to the invention at various stages in the manufacture of the device by means of an embodiment of a method in accordance with the invention.
  • the figures are diagrammatic and not drawn to scale, the dimensions in the thickness direction being particularly exaggerated for greater clarity. Corresponding parts are generally given the same reference numerals and the same hatching in the various figures.
  • FIGs. 1 through 4 show sectional views of an example of a semiconductor device according to the invention at various stages in the manufacture of the device by means of an embodiment of a method in accordance with the invention.
  • the (nearly) finished device 10 comprises a semiconductor body 12, here of p-type silicon which here is formed by a substrate 11 and in which a first transistor 1 is formed as an NMOST. In a N-well region 33 a second transistor 2 is formed as a PMOST.
  • the transistors 1,2 comprise source and drain regions 1A,1B,2A,2B, respectively of the n- and p-type conductivity, dielectric regions 1C,2C, here comprising silicondioxide, and gate regions 1D,2D.
  • isolation regions 25 are formed, here in the form of trenches filled with silicondioxide (or with another gate dielectric, e.g. a metal oxide).
  • the gate region ID of the NMOST 1 comprises in this example a compound comprising Mo and Te and of which the workfunction is about 4.1 eV, very close to the optimal value of about 4.2 eV.
  • the gate region 2D of the PMOST 2 comprises in this example a compound comprising Mo and O and with a composition Of MoO x , where x ⁇ 2, e.g. MoO 2 , of which the work function can be easily tuned to the optimal value of about 5.2 eV.
  • both gate regions comprise a region of TiN and poly silicon on top of the work function materials.
  • the device 10 is manufactured as follows. Starting point (see Fig. 1) is a p- type substrate 11 in which the n-well 33 and the STI ( ⁇ Shallow Trench Isolation) regions 25 are formed. Next a dielectric layer 21 is formed and on thereon a metal layer 22, here comprising, preferably porous, Mo, is deposited by vapor deposition and has a thickness in the range of 5 to 20 nm.
  • a metal layer 22 here comprising, preferably porous, Mo, is deposited by vapor deposition and has a thickness in the range of 5 to 20 nm.
  • a mask 15 is formed both at the location of the PMOST 2 and at the location of the NMOST 1.
  • the mask 15 comprises here TiN and is formed by deposition of a TiN layer, mask 15A e.g. comprises a photo resist layer.
  • Mask 15 has a thickness of 5 to 20 nm and mask 15A is 0.5 to 2 ⁇ m thick.
  • ions 30 of tellurium are implanted into the metal layer 22 at the location of the NMOST 1.
  • the tellurium ions are implanted with a flux in the range of 1-4 x 10 15 cm "2 and with an implantation energy in the range of 10 tot 20 keV.
  • the Te ions 30, or at least a large fraction thereof reaches the Mo layer 22.
  • the thickness of the TiN mask 15 can be adjusted in the ranges aforementioned such that the implantation of Te ions into the gate dielectric 1C at the location of the NMOST 1 is avoided, where below this gate dielectric 1C is located the substrate being composed of, for example, Si. Additionally, conditions can be optimized such that mask 15 is unnecessary and can be deposited after the Te implantation.
  • An additional advantage of the presence of the mask 15 in an early stage after formation of the Mo layer 22, is that it protect the Mo layer 22 against an uncontrolled exposure to oxygen at moderate conditions, e.g. during storage.
  • the device 10 which is still covered with the TiN layer 15, is protected by a mask 16.
  • the part thereof at the location of the PMOST 2 has been removed by photolithography and etching.
  • the mask 16 comprises in this example silicon nitride.
  • the Mo layer 22, at the position of the PMOST 2 is exposed to a gaseous compound 40 comprising O, here 02 under heating to T > 250 degrees Celsius.
  • the conditions are such that the Mo layer 22 is locally converted to MoO 2 (or to a compound with a composition in the range indicated before) which will form the gate region 2D of the PMOST 2. Since the mask 16 is impermeable for oxygen, the metal layer 22 containing Te atoms at the location of the NMOST 1 remains unaffected.
  • the device 10 is subjected to a thermal annealing step, e.g. a spike anneal in a nitrogen atmosphere and at a temperature in the range of 700 to 1050 degrees Celsius.
  • a thermal annealing step e.g. a spike anneal in a nitrogen atmosphere and at a temperature in the range of 700 to 1050 degrees Celsius.
  • This anneal can be done in the apparatus in which the MoO 2 has been formed. Thanks to the fact the implantation has been done first, the device thus at this stage is already in a suitable annealing apparatus. Therefore, the method of this example is rather efficient.
  • the mask 16 is removed by etching. The remainder of the mask 15 may be removed if desired. Its removal is however not necessary.
  • a capping layer - not shown in the drawing - of an electrically conducting material like a metal nitride, e.g. titanium nitride is deposited uniformly onto the device 10.
  • This material will block a reaction of the work function materials with silicon deposited afterwards and its presence in a gate stack is allowable because it is an electrically conducting material. Moreover, it protects the device against other exposures at moderate conditions.
  • the manufacturing is then continued in a usual manner in that gate stacks are formed by amorphous or poly-Si deposition, photolithography and etching. Formation of shallow parts of the source and drain regions 1A,1B,2A,2B is followed by the formation of spacers 44 and the deep source and drain implantations. Further steps like the deposition of pre-metal dielectric, patterning thereof, contact metal deposition and patterning thereof are not shown in the drawing.

Abstract

The invention relates to a CMOS device (10) with an NMOST 1 and PMOST 2 having gate regions (1D,2D) comprising respectively first and second conducting materials of a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and the first conducting material comprises oxygen as the further element and the second conducting material comprise a chalcogenide as the further element. The invention also provides an attractive method of manufacturing such a device.

Description

Semiconductor device and method of manufacturing such a semiconductor device
The invention relates to a semiconductor device with a substrate and a semiconductor body comprising a first field effect transistor with a first source and drain region and a first channel of a first conductivity type and with separated from the first channel by a first dielectric region a first gate region comprising a first conducting material and a second field effect transistor with a second source and drain region and a second channel of a second, opposite to the first, conductivity type and with separated from the second channel by a second dielectric region a second gate region comprising a second conducting material different from the first conducting material, wherein the first and second conducting material comprise a compound containing both a metal and a further element. In advanced CMOS (= Complimentary Metal Oxide Semiconductor) devices below the sub 0,1 micron region, the replacement of polysilicon gates by metal gates or alloys thereof is desirable for various reasons. The invention also relates to a method of manufacturing such a device.
A device as mentioned in the opening paragraph is known from US patent
6,130,123 that has been published on October 10, 2000. Therein various electrically conducting materials are described that are suitable for use in the NMOST (= N-type MOS
Transistor) and PMOST of a CMOS device. Examples of metals or metal alloys that are suitable for the former of which the workfunction is about 4.2 eV are Ru, Zr, Nb, Ta, MoSi and TaSi. For the latter, having a workfunction of about 5.2 eV Ni, RuO2, MoN and TaN are suitable material among others.
A drawback of the known conducting materials is that they are not always very compatible with existing IC technology. This includes the requirement that the materials should be compatible with the materials of the gate stack comprising the materials of the gate dielectric, the capping layer and the spacers. It is therefore an object of the present invention to avoid the above drawbacks and to provide a device which is very compatible with IC technology and easy to manufacture.
To achieve this, a device of the type mentioned in the opening paragraph is characterized in that the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and the second conducting material comprises oxygen as the further element and the first conducting material comprises a chalcogenide as the further element. The chalcogenides comprise the elements S, Se and Te. On the one hand the material contains a metal that is very common in present IC technology, e.g. for conduction tracks and in particular for use a connection between conduction tracks at different levels. On the other hand the further elements in a device according to the invention provide several advantages. Firstly, they allow for a good coverage of the two relevant workfunctions in CMOS devices, namely 5.2 eV and 4.1 eV respectively. Furthermore both molybdenum and tungsten on the one hand, and oxygen and the chalcogenides - all being elements of the VI column - on the other hand, behave similarly and all are well compatible with present IC technology. The latter in particular holds if the compounds are manufactured with a method according to the invention.
In a preferred embodiment Molybdenum is chosen as the metal and Tellurium are chosen as the chalcogenide. Good results are obtained with these elements. When Te was implanted into a molybdenum film, the workfunction of the resulting material was very close to 4.1 eV, and thus very suitable for use in a NMOST. Molybdenum oxide, with an oxygen subscript of 2 or less, results in a work function material very close to 5.2 and thus is very suitable for use in a PMOST. Thus the preferred metal element is molybdenum. Preferably, the first and second gate region comprises on top of the first and second conducting material a region of another material which is electrically conducting and acting as a barrier to silicon. Preferably the another material comprises a metal nitride like titanium nitride. Other metal nitrides like a tantalum nitride could be used as well. This promotes an efficient manufacturing of the device. A method of manufacturing a semiconductor device with a substrate and a semiconductor body comprising a first field effect transistor with a first source and drain region and a first channel of a first conductivity type and with separated from the first channel by a first dielectric region a first gate region comprising a first conducting material and a second field effect transistor with a second source and drain region and a second channel of a second, opposite to the first, conductivity type and with separated from the second channel by a second dielectric region a second gate region comprising a second conducting material different from the first conducting material, wherein for the first and second conducting materials a material is chosen comprising a compound containing both a metal and a further element, is according to the invention characterized in that for the first and second conducting material both a material is chosen comprising a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and for the second conducting material oxygen is chosen as the further element and for the first conducting material a chalcogenide is chosen as the further element. In this way a semiconductor device according to the invention is obtained.
In a preferred embodiment of the method according to the invention molybdenum is chosen as the metal and tellurium is chosen as the chalcogenide.
A first modification is characterized in that on the first and second dielectric regions a layer of the metal is formed which is at the location of the first dielectric region implanted with ions of the chalcogenide while the layer of the metal is protected at the location of the second dielectric region against the implantation by a mask.
Another modification is characterized in that on the first and second dielectric regions a layer of metal is formed which is at the location of the second dielectric region made to react with oxygen while the layer of the metal at the location of the first dielectric region is protected against the oxygen by a further mask.
Both modifications allow for an easy forming of the two conducting materials. Preferably, the implantation is done before the oxidation. In this way, the oxidation apparatus can be used to anneal both materials, with minimum delay. Only the atmosphere in the apparatus has to be made inert and another desired temperature cycles has to be programmed. Such features can easily be incorporated. A local oxidation can easily be performed using a mask like silicon nitride.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter, to be read in conjunction with the drawing, in which:
Figs. 1 through 4 are sectional views of an example of a semiconductor device according to the invention at various stages in the manufacture of the device by means of an embodiment of a method in accordance with the invention. The figures are diagrammatic and not drawn to scale, the dimensions in the thickness direction being particularly exaggerated for greater clarity. Corresponding parts are generally given the same reference numerals and the same hatching in the various figures.
Figs. 1 through 4 show sectional views of an example of a semiconductor device according to the invention at various stages in the manufacture of the device by means of an embodiment of a method in accordance with the invention.
The (nearly) finished device 10 (see Fig. 4) comprises a semiconductor body 12, here of p-type silicon which here is formed by a substrate 11 and in which a first transistor 1 is formed as an NMOST. In a N-well region 33 a second transistor 2 is formed as a PMOST. The transistors 1,2 comprise source and drain regions 1A,1B,2A,2B, respectively of the n- and p-type conductivity, dielectric regions 1C,2C, here comprising silicondioxide, and gate regions 1D,2D. In the surface of the semiconductor body 12 isolation regions 25 are formed, here in the form of trenches filled with silicondioxide (or with another gate dielectric, e.g. a metal oxide).
The gate region ID of the NMOST 1 comprises in this example a compound comprising Mo and Te and of which the workfunction is about 4.1 eV, very close to the optimal value of about 4.2 eV. The gate region 2D of the PMOST 2 comprises in this example a compound comprising Mo and O and with a composition Of MoOx, where x < 2, e.g. MoO2, of which the work function can be easily tuned to the optimal value of about 5.2 eV. In addition, both gate regions comprise a region of TiN and poly silicon on top of the work function materials.
The device 10 is manufactured as follows. Starting point (see Fig. 1) is a p- type substrate 11 in which the n-well 33 and the STI (^Shallow Trench Isolation) regions 25 are formed. Next a dielectric layer 21 is formed and on thereon a metal layer 22, here comprising, preferably porous, Mo, is deposited by vapor deposition and has a thickness in the range of 5 to 20 nm.
Subsequently (see Fig. 2) a mask 15 is formed both at the location of the PMOST 2 and at the location of the NMOST 1. At the location of the PMOST an additional mask 15A is provided. The mask 15 comprises here TiN and is formed by deposition of a TiN layer, mask 15A e.g. comprises a photo resist layer. Mask 15 has a thickness of 5 to 20 nm and mask 15A is 0.5 to 2 μm thick. Then ions 30 of tellurium are implanted into the metal layer 22 at the location of the NMOST 1. The tellurium ions are implanted with a flux in the range of 1-4 x 1015 cm"2 and with an implantation energy in the range of 10 tot 20 keV. For the given conditions, only at the location of the NMOST 1, the Te ions 30, or at least a large fraction thereof reaches the Mo layer 22. The thickness of the TiN mask 15 can be adjusted in the ranges aforementioned such that the implantation of Te ions into the gate dielectric 1C at the location of the NMOST 1 is avoided, where below this gate dielectric 1C is located the substrate being composed of, for example, Si. Additionally, conditions can be optimized such that mask 15 is unnecessary and can be deposited after the Te implantation. An additional advantage of the presence of the mask 15 in an early stage after formation of the Mo layer 22, is that it protect the Mo layer 22 against an uncontrolled exposure to oxygen at moderate conditions, e.g. during storage.
Hereinafter, a similar procedure is done (see Fig. 3) for the PMOST 2. Now the device 10, which is still covered with the TiN layer 15, is protected by a mask 16. After uniform deposition of such a masking layer 16, the part thereof at the location of the PMOST 2 has been removed by photolithography and etching. The mask 16 comprises in this example silicon nitride. With the mask 16 on top, the part of the TiN layer 15 at the location of the PMOST 2 is also removed. Now the Mo layer 22, at the position of the PMOST 2, is exposed to a gaseous compound 40 comprising O, here 02 under heating to T > 250 degrees Celsius. The conditions are such that the Mo layer 22 is locally converted to MoO2 (or to a compound with a composition in the range indicated before) which will form the gate region 2D of the PMOST 2. Since the mask 16 is impermeable for oxygen, the metal layer 22 containing Te atoms at the location of the NMOST 1 remains unaffected.
At this stage the device 10 is subjected to a thermal annealing step, e.g. a spike anneal in a nitrogen atmosphere and at a temperature in the range of 700 to 1050 degrees Celsius. This anneal can be done in the apparatus in which the MoO2 has been formed. Thanks to the fact the implantation has been done first, the device thus at this stage is already in a suitable annealing apparatus. Therefore, the method of this example is rather efficient. Next the mask 16 is removed by etching. The remainder of the mask 15 may be removed if desired. Its removal is however not necessary.
In this example subsequently, a capping layer - not shown in the drawing - of an electrically conducting material like a metal nitride, e.g. titanium nitride is deposited uniformly onto the device 10. This material will block a reaction of the work function materials with silicon deposited afterwards and its presence in a gate stack is allowable because it is an electrically conducting material. Moreover, it protects the device against other exposures at moderate conditions. The manufacturing is then continued in a usual manner in that gate stacks are formed by amorphous or poly-Si deposition, photolithography and etching. Formation of shallow parts of the source and drain regions 1A,1B,2A,2B is followed by the formation of spacers 44 and the deep source and drain implantations. Further steps like the deposition of pre-metal dielectric, patterning thereof, contact metal deposition and patterning thereof are not shown in the drawing.
It will be obvious that the invention is not limited to the examples described herein, and that within the scope of the invention many variations and modification are possible to those skilled in the art. It is for example in order to fine tune the workfunctions, traces of other elements can be introduced into the conducting materials. Also a mixture of elements like Se and Te can be used for that purpose.

Claims

CLAIMS:
1. Semiconductor device (10) with a substrate (11) and a semiconductor body
(12) comprising a first field effect transistor (1) with a first source and drain region (IA, IB) and a first channel of a first conductivity type and with separated from the first channel by a first dielectric region (1C) a first gate region (ID) comprising a first conducting material and a second field effect transistor (2) with a second source and drain region (2A,2B) and a second channel of a second, opposite to the first, conductivity type and with separated from the second channel by a second dielectric region (2C) a second gate region (2D) comprising a second conducting material different from the first conducting material, wherein the first and second conducting material comprise a compound containing both a metal and a further element, characterized in that the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and the second conducting material comprises oxygen as the further element and the first conducting material comprises a chalcogenide as the further element.
2. Semiconductor device (10) according to claim 1, characterized in that as the metal molybdenum is chosen and as the chalcogenide tellurium is chosen.
3. Semiconductor device (10) according to claim 1 or 2, characterized in that the first conductivity type comprises the n-type.
4. Semiconductor device (10) according to claim 1, 2 or 3, characterized that the first and second gate region comprises on top of the first and second material a region of another material which is electrically conducting and forming a barrier against silicon.
5. Semiconductor device (10) according to claim 4, characterized in that the another material comprises a metal nitride.
6. Method of manufacturing a semiconductor device (10) with a substrate (1 1) and a semiconductor body (12) comprising a first field effect transistor (1) with a first source and drain region (IA, IB) and a first channel of a first conductivity type and with separated from the first channel by a first dielectric region (1C) a first gate region (ID) comprising a first conducting material and a second field effect transistor (2) with a second source and drain region (2 A,2B) and a second channel of a second, opposite to the first, conductivity type and with separated from the second channel by a second dielectric region (2C) a second gate region (2D) comprising a second conducting material different from the first conducting material, wherein for the first and second conducting material a material is chosen comprising a compound containing both a metal and a further element, characterized in that for the first and second conducting material both a material is chosen comprising a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and the second conducting material comprises oxygen as the further element and the first conducting material comprises a chalcogenide as the further element.
7. Method according to according to claim 6, characterized in that for the metal molybdenum is chosen and for the chalcogenide tellurium is chosen.
8. Method according to claim 6 or 7, characterized in that on the first and second dielectric regions (1C,2C, 21) a layer (22) of the metal is formed which is at the location of the first dielectric region (1C) implanted with ions (30) of the chalcogenide while the layer (22) of the metal is protected at the location of the second dielectric region (2C) against the implantation by a mask (15,15A).
9. Method according to claim 6, 7 or 8, characterized in that on the first and second dielectric regions (1C,2C, 21) a layer (22) of the metal is formed which is at the location of the second dielectric region (2C) made to react with oxygen (40) while the layer (22) of the metal at the location of the first dielectric region (1C) is protected against oxygen (40) by a further mask (16).
10. Method according to claim 6, 7, 8 or 9, characterized in that after formation of the oxygen compound and/or the chalcogenide compound the device (10) is subjected to a thermal annealing step.
PCT/IB2005/052647 2004-08-24 2005-08-10 Semiconductor device and method of manufacturing such a semiconductor device WO2006021907A1 (en)

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