WO2006016414A1

WO2006016414A1 - Signal forming circuit, signal forming method, and electronic device

Info

Publication number: WO2006016414A1
Application number: PCT/JP2004/011704
Authority: WO
Inventors: Futoshi Fujiwara
Original assignee: Shearwater Kabushiki Kaisha
Priority date: 2004-08-13
Filing date: 2004-08-13
Publication date: 2006-02-16
Also published as: JPWO2006016414A1; JP4543042B2

Abstract

A signal forming circuit for forming an output signal in which EMI can be reduced, comprising a modulating signal generating part (3) and a clock modulating part (2). The modulating signal generating part (3) includes a reference signal producing part (33) for outputting a modulating signal that is a reference signal serving as a reference used for producing an ultimate modulating signal; and first and second sub-modulating signal producing parts (31,32) for outputting first and second sub-modulating signals. The modulating signal generating part (3) modulates the modulating signal by use of the first and second sub-modulating signals to output the ultimate modulating signal. The clock modulating part (2) modulates, by use of the ultimate modulating signal, a periodic signal outputted from a periodic signal forming circuit (1), thereby outputting an output signal in which EMI can be reduced by reducing spectrum caused by the output signal.

Description

Specification

Signal forming circuit, signal forming method, and electronic apparatus

Technical field

TECHNICAL FIELD [0001] The present invention relates to a signal forming circuit, a signal forming method, and an electronic device, and in particular, a spread spectrum signal forming circuit and a signal that reduce EMI more efficiently by using a modulated wave that further modulates a modulated wave. The present invention relates to a forming method and an electronic device including the signal forming circuit.

Background art

[0002] Electronic devices are required to reduce EMI (Electro Magnetic Interference). EMI is particularly affected by electromagnetic waves emitted from circuits that use periodically changing signals such as clocks (rectangular waves), triangular waves, and sine waves.

Therefore, for example, a spread spectrum clock generator (SSCG) is known as an example of a technique for reducing EMI in a clock forming circuit (clock generator) (for example, Patent Document 1). SSCG uses the modulated wave to slightly change the frequency of the oscillation clock in the clock generator (frequency modulation), thereby reducing EMI. Figure 19 illustrates this principle. That is, the spectrum spO indicates an accurate clock frequency spectrum without frequency modulation. In this case, the spectrum spO has the highest frequency component at the transmission frequency fO. When this clock is frequency-modulated, its frequency spectrum spl changes as shown in FIG. As a result, since the ratio of the unit time to the frequency within the modulation width is low, the peak of the spectrum spl is reduced, and EMI can be reduced.

FIGS. 20 (A) to 20 (C) show the relationship between the SSCG modulation wave and the clock spectrum. In each, the SSCG modulation wave is shown on the left and the clock spectrum is shown on the right. Show. Figure 20 (A) shows the spectrum of the clock when modulated with a sine wave. In this case, as shown by a circle in FIG. 21 (A), the density near the apex increases, so both ends of the spectrum increase. Figure 20 (B) shows the spectrum of the clock when modulated with a triangular wave. In this case, as shown in Fig. 21 (B), in order to obtain a uniform density without depending on time, There should be no peaks in the spectrum. In reality, however, the waveform at the apex of the triangular wave becomes dull due to deterioration of the characteristics of the modulator with respect to the modulation wave (specifically, the band limitation of the VCO (voltage controlled oscillator)), resulting in some peaks at both ends of the spectrum Exists. Furthermore, in practice, due to the band limitation of the PLL connected to the latter stage of SSCG, the peak waveform of the triangular wave becomes dull, and as a result, there are some peaks at both ends of the spectrum.

[0005] Therefore, it is known to use a waveform in which the apex of a triangular wave is emphasized as a modulated wave in consideration of the characteristics of the modulator (Patent Document 2). Figure 20 (C) shows the relationship between the modulated wave and the spectrum of the clock in this case. In this case, a flat spectrum is obtained, and thus a greater attenuation is obtained.

Patent Document 1: US Pat. No. 4,507,796

Patent Document 2: US Pat. No. 5,488,627

Disclosure of the invention

Problems to be solved by the invention

[0006] When the spectrum when a clock signal or a carrier wave (that is, a modulated wave) is modulated with a certain modulated wave (frequency fl) is strictly observed, as shown in FIG. Has fine peaks and peaks at intervals of the modulation frequency fl. Therefore, in practice, the spectrum shown in FIG. 20 (C) also has the same fine peak as shown in FIG. 22 (A). As shown in Fig. 22 (B), the conventional SSCG modulation method described above basically increases the number of peaks and decreases the density per unit time by lowering the frequency of the modulation wave. It can be said that the peak of the vector is reduced. If the spectrum peak can be reduced, EMI can be reduced.

[0007] According to the conventional SSCG modulation method, in principle, the spectrum peak cannot be reduced unless the frequency of the modulated wave is lowered. On the other hand, the lower limit of the modulation frequency fl is considered to be about 20 kHz which is an audible frequency in practice. If the frequency is lower than this, a part or the whole of the electronic device may vibrate at the modulation frequency fl, and the vibration sound may be heard by humans. Therefore, according to the conventional SSCG modulation method, there is a limit to reducing the spectrum peak due to the lower limit of the frequency of the modulation wave. [0008] In addition, when using a modulated wave in which the apex of a triangular wave is emphasized in order to obtain flatness of the spectrum, a signal having such a waveform cannot be easily obtained. That is, the configuration of the clock generation circuit becomes extremely complicated. In addition, when designing the clock generation circuit, it is necessary to consider the characteristics of each type of modulator, which is troublesome.

[0009] The above problems are not only limited to clocks, but also occur in circuits that use periodic signals such as triangular waves and sine waves. This is an obstacle to EMI reduction.

[0010] An object of the present invention is to provide a signal forming circuit capable of reducing EMI more efficiently by improving at least the flatness of a spectrum of a periodic signal or by reducing the peak of the spectrum.

[0011] In addition, an object of the present invention is to provide a signal forming method that improves EMI more efficiently by improving at least the flatness of the spectrum of a periodic signal or by reducing the peak of the spectrum. It is in.

[0012] Also, an object of the present invention is to provide an electronic device including a signal forming circuit that more efficiently reduces EMI.

Means for solving the problem

[0013] A signal forming circuit of the present invention is a signal forming circuit that forms an output signal capable of reducing EMI, and that modulates a reference signal serving as a reference for generating a final modulated signal. A modulation signal generation unit for outputting the final modulation signal generated by modulating the reference signal with at least one sub modulation signal, and a periodic signal forming unit. An output signal generated by modulating a periodic signal output from a circuit with the final modulation signal, and an output signal capable of reducing the EMI by reducing a spectrum caused by the output signal. A signal modulation unit for output.

[0014] A signal forming method of the present invention is a signal forming method for forming an output signal capable of reducing EMI, for generating at least one sub-modulation signal and generating a final modulation signal. A final reference signal is generated by modulating a reference signal serving as a reference with the at least one sub-modulation signal, and a periodic signal is modulated with the final modulation signal. Thus, an output signal capable of reducing the EMI is generated by reducing a spectrum caused by the output signal.

[0015] The electronic device of the present invention includes a periodic signal forming circuit that outputs a periodic signal, a reference signal generation unit that outputs a reference signal serving as a reference for generating a final modulation signal, and at least modulates the reference signal. A modulation signal generation unit that outputs the final modulation signal generated by modulating the reference signal with the at least one submodulation signal. And reducing the EMI by reducing the spectrum resulting from the output signal generated by modulating the periodic signal output from the periodic signal forming circuit with the final modulation signal. A signal modulating unit that outputs an output signal capable of performing a predetermined operation, and an operation unit that performs a predetermined operation based on the output signal.

The invention's effect

[0016] According to the study of the present inventor, SSCG basically has two problems. First, what kind of modulation signal is appropriate to obtain the flatness of the spectrum, and second, when the modulation width is the same, the spectrum peak is further reduced. How should we do it? The present invention is based on a new principle obtained by reexamining SSCG from its principle. By applying the new principle to not only a clock signal but also a periodic signal such as a sine wave. In addition, while maintaining the frequency of the modulation signal within the range that does not generate vibration sound, the flatness of the spectrum can be improved and the spectrum peak can be reduced.

In the present invention, the modulation signal is further modulated using the sub-modulation signal. In other words, the clock signal is modulated in multiple (double or higher). The type of sub-modulation is frequency modulation or amplitude modulation. By modulating the frequency of the modulation signal, it is possible to reduce the peak of the modulation frequency. By modulating the amplitude of the modulation signal, the spectrum can be flattened. The modulation signal may be frequency-modulated and amplitude-modulated, whereby the peak of the modulation frequency can be reduced and the spectrum can be flattened.

According to the signal forming circuit and the signal forming method of the present invention, the clock signal is generated by the final modulation signal generated by (sub) modulating the modulation signal with at least one 畐 IJ modulation signal. Etc. to modulate multiple periodic signals. Therefore, by modulating the modulation signal at least by frequency modulation or amplitude modulation, the peak of the modulation frequency can be reduced, or the spectrum can be flattened. As a result, even if the modulation frequency is not lower than the frequency (about 20kHZ) that generates vibration sound, the peak of the spectrum can be reduced, and the modulation wave that emphasizes the apex of the triangular wave is not used. However, the spectrum can be flattened. Therefore, due to the flatness of the spectrum, it is not necessary to consider the characteristics of the modulator, which does not require the use of a complicated clock generation circuit. As a result, it is possible to reduce the EMI of the signal forming circuit and the electronic device using the signal forming circuit by reducing the spectrum peak or flattening the spectrum.

[0019] According to the electronic device of the present invention, a signal forming that multiplexly modulates a periodic signal such as a clock signal by a final modulation signal generated by modulating the modulation signal with at least one sub-modulation signal. Provide circuit. Therefore, by modulating the modulation signal at least by frequency modulation or amplitude modulation, as described above, it is possible to flatten the force and spectrum for reducing the peak of the modulation frequency. Therefore, it is not necessary to consider the characteristics of the modulator, which does not require the use of a complex clock generation circuit, due to the flatness of the spectrum. As a result, the EMI of the electronic device can be reduced by at least reducing the spectrum peak or flattening the spectrum.

Brief Description of Drawings

FIG. 1 shows a configuration of a signal forming circuit according to the present invention.

FIG. 2 is a diagram illustrating clock modulation according to the present invention.

FIG. 3 is a diagram illustrating clock modulation according to the present invention.

FIG. 4 is a diagram illustrating clock modulation according to the present invention.

FIG. 5 shows a waveform in the modulation signal generator.

[Figure 6] Shows waveforms in the PLL that is the clock modulator.

FIG. 7 shows the configuration of another signal forming circuit according to the present invention.

FIG. 8 shows a configuration of still another signal forming circuit according to the present invention.

FIG. 9 shows a configuration of still another signal forming circuit according to the present invention.

FIG. 10 shows a configuration of still another signal forming circuit according to the present invention. FIG. 11 shows the configuration of still another signal forming circuit according to the present invention.

FIG. 12 shows the configuration of still another signal forming circuit according to the present invention.

FIG. 13 shows a configuration of still another signal forming circuit according to the present invention.

FIG. 14 shows a configuration of still another signal forming circuit according to the present invention.

FIG. 15 shows a configuration of still another signal forming circuit according to the present invention.

FIG. 16 shows a configuration of still another signal forming circuit according to the present invention.

FIG. 17 shows a configuration of an electronic device including a signal forming circuit of the present invention.

FIG. 18 shows a configuration of another electronic device including the signal forming circuit of the present invention.

FIG. 19 is an explanatory diagram of spread spectrum.

FIG. 20 is an explanatory diagram of spread spectrum.

FIG. 21 is an explanatory diagram of spread spectrum.

FIG. 22 is an explanatory diagram of spread spectrum.

Explanation of symbols

[0021] 1 period signal forming circuit (oscillator)

2 Signal modulator (clock modulator)

3 Modulation signal generator

31 First sub-modulation signal generator

32 Second sub-modulation signal generator

33 Reference signal generator

34 multiplier

100 signal forming circuit

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a configuration diagram of a signal forming circuit, and shows an example of a configuration of a signal forming circuit according to the present invention. The signal forming circuit 100 of the present invention includes a clock modulation unit 2 and a modulation signal generation unit 3 which are signal modulation units. The clock modulation unit 2 receives a clock signal (periodic rectangular wave) output from the oscillator 1 which is a periodic signal forming circuit. That is, this example shows an example of modulating a clock signal which is the most typical periodic signal. According to this example, a relatively simple configuration (that is, the circuit scale is not so large) allows almost all the clock signals to be included. By using a periodic signal, a sufficient EMI reduction effect can be obtained.

In this example, the oscillator 1 generates a clock signal, and the clock modulator 2 generates a modulation signal, a first submodulation signal that is an FM submodulation wave, and a second submodulation signal that is an AM submodulation wave. Is done. Then, as shown in FIG. 2, the modulation signal is modulated by the first and second sub-modulation signals (frequency modulation and amplitude modulation), thereby generating a final modulation signal. Furthermore, an output clock signal is generated by modulating the clock signal with the final modulation signal. As will be described later, the present invention is not limited to a clock signal, but can be widely applied to periodic signals such as a triangular wave and a sine wave. However, when applied to a clock signal, a particularly significant effect can be obtained in reducing EMI. That is, since the clock signal is rectangular, it contains more harmonic components (odd order) than triangular waves, etc. Also, in electronic devices that operate with digital signals, the amplitude (or instantaneous This is effective for reducing the effects of EMI.

The modulation signal (modulation wave) is a signal for slightly varying the frequency of the clock signal (carrier wave) output from the oscillator 1. The sub-modulation signal (sub-modulation wave) is a general term for signals that further modulate the modulation signal, and is referred to as a “sub-modulation signal” to distinguish it from the modulation signal. In this example, two types of sub-modulation signals called first and second sub-modulation signals are used.

[0025] If the modulation signal is composed of, for example, a triangular wave, the frequency modulation using the first sub modulation signal is modulation in the horizontal direction (time axis direction) in FIG. The amplitude modulation using the second sub-modulation signal is modulation in the vertical direction (voltage or current axis direction) in FIG. Therefore, the modulation signal is sub-modulated twice (in two directions). Since the clock signal is modulated by the modulation signal that is doubly submodulated, it can be said that the clock signal is triple modulated. Thereby, as shown in FIG. 2, the spectrum peak of the clock signal can be reduced and flattened.

The oscillator 1 generates and outputs a clock signal having a predetermined frequency, for example, 10 MHz. The oscillator 1 may be a clock generation device having a known configuration. The clock signal output from oscillator 1 is input to clock modulator 2. The clock modulation unit 2 modulates the clock signal output from the oscillator 1 with the final modulation signal to synchronize with the clock signal. Generate and output the expected output clock signal. For example, the clock modulation unit 2 is composed of a phase locked loop (PLL) that receives the clock signal output from the oscillator 1 as an input, uses the final modulation signal as a control signal, and outputs the output clock signal. As will be described later, the output clock is input to the operation unit (operation unit 300 in FIG. 17) of various electronic devices and used as a basic clock.

In this example, the modulation signal generation unit 3 includes a reference signal generation unit 33, a first sub modulation signal generation unit 31 that is an FM (frequency modulation) sub modulation signal generation unit, and an AM (amplitude modulation) sub modulation signal. A second sub-modulation signal generation unit 32 and a multiplier 34, which are generation units, are provided. FIG. 3 conceptually shows the waveform of each signal in the modulation signal generator 3.

The reference signal generation unit 33 generates and outputs a modulation signal FM (not shown) that is a reference signal (reference signal) for generating a final modulation signal. In this example, the reference signal generation unit 33 is provided inside the modulation signal generation unit 3. In this example, the modulation signal FM is a triangular wave (a symmetrical triangular wave). Therefore, the reference signal generation unit 33 in this example is a triangular wave generation circuit. The modulation signal FM may be a signal that changes continuously, for example, a sine wave. In this example, the reference signal generation unit 33 outputs the intermediate modulation signal FMsigo when the first sub modulation signal (FM sub modulation wave) FMo output from the first sub modulation signal generation unit 31 is input. To do. Actually, the intermediate modulation signal FMsigo is not a triangular wave because it is the result of FM modulation of the triangular wave that is the modulation signal FM. The intermediate modulation signal FM sigo is input to the multiplier 34.

[0029] The first sub-modulation signal generator 31 outputs a first sub-modulation signal FMo. The first sub-modulation signal F Mo is a signal that frequency-modulates the modulation signal FM, and is a triangular wave in this example. By modulating the frequency of the modulation signal FM, the modulation frequency in the modulation range on the spectrum can be dispersed, and as a result, the peak of the modulation frequency can be reduced. The first sub modulation signal FMo is a signal that changes continuously and does not change discontinuously. The frequency and phase of the first sub-modulation signal FMo need not depend on other oscillators. Specifically, the first sub-modulation signal FMo is a triangular wave having a period sufficiently longer than the modulation signal FM. The period is, for example, a period about 10 times as long as the modulation signal FM. The frequency sub-modulation width is preferably 0.5 to 1.5 times the frequency of the modulation signal FM. The first sub modulation signal FMo is input to the reference signal generation unit 33.

[0030] The second sub-modulation signal generator 32 outputs the second sub-modulation signal AMo. The second sub-modulation signal A Mo is a signal that modulates the amplitude of the modulation signal FM, and is a triangular wave in this example. By modulating the amplitude of the modulation signal FM, the peaks at both ends of the spectrum can be reduced, and as a result, the spectrum can be flattened. The second submodulation signal AMo is either a continuously changing signal (for example, a triangular wave) or a discontinuously changing signal (for example, a staircase wave). The frequency and phase of the second secondary modulation signal AMo do not depend on other oscillators. Specifically, the second submodulation signal AMo is a triangular wave having a period longer than the modulation signal FM and shorter, longer or equal to the first submodulation signal FMo. The period is, for example, a period about 23 times longer than the modulation signal FM. The second submodulation signal AMo is input to the multiplier 34.

[0031] Here, the first and second sub-modulation signals FMo and AMo (herein simply referred to as sub-modulation signals) may be any signals that continuously change in addition to the triangular wave. Even in this case, it is possible to obtain the effect of spreading the outer surface similarly. For example, the submodulation signal is composed of the sum of a sine wave of arbitrary amplitude An, a cosine wave of arbitrary amplitude Bn, a sine wave of arbitrary amplitude An of an integer multiple of these, and a cosine wave of arbitrary amplitude Bn. Signal (all periodic signals, or 8'11 '3111 (11 0 ^) + ∑811' (: 03 (11 0 ^), where ∑ is 1 to 1 n)), sawtooth wave (left and right The sub-modulated signal may be a signal generated by any irregular process such as uniform distribution noise, Gaussian distribution noise, binomial distribution noise, Poisson distribution noise, Rayleigh distribution, etc. In addition, the submodulation signal may be a signal obtained by combining two or more of the various signals described herein.

[0032] The multiplier 34 multiplies the intermediate modulation signal FMsigo output from the reference signal generation unit 33 by the second sub modulation signal AMo output from the second sub modulation signal generation unit 32, thereby finalizing the signal. Modulation signal MODo is output. That is, the multiplier 34 is for amplitude-modulating the frequency-modulated intermediate modulation signal FMsigo. Thus, the modulation signal generator 3 generates and outputs the final modulation signal MODo by modulating the modulation signal FM with the first and second sub modulation signals FMo and AMo (frequency modulation and amplitude modulation). . The final modulation signal MODo is input to the PLL that is the clock modulation unit 2. In this example, the PLL 2 includes a first divider 21 with a division ratio A, a second divider 22 with a division ratio B, a phase comparator 23, a loop filter 24, a voltage-current converter (VI ) 25, multiplier 26, current controlled oscillator (ICO) 27. The voltage-current converter 25 and the current-controlled oscillator 27 constitute a voltage-controlled oscillator (VCO). That is, the voltage controlled oscillator includes a multiplier 26. Figure 4 conceptually shows the waveform of each signal in PLL2.

[0034] The relationship between the frequency f (Fin) of the input signal Fin and the frequency f (Fout) of the output signal Fout in the PLL2 is f (Fout) = f (Fin) · ΑΖΒ. For example, Α is the division ratio of the first divider 21, B is the division ratio of the second divider 22, and if A = 40 and B = 3, the input clock signal is a 10 MHz clock signal. In this case, a 133 MHz output clock signal is obtained.

When the clock signal Fin having the frequency f (Fin) output from the oscillator 1 is input, the second frequency divider 22 outputs a signal Bo obtained by dividing the clock signal Fin by the frequency dividing ratio B. The frequency f (Bo) of the signal Bo is a value f (Fin) ZB obtained by dividing the frequency f (Fin) by the division ratio B. The signal Bo is input to the phase comparator 23.

The output Ao is also input to the phase comparator 23 from the first frequency divider 21. The phase comparator 23 compares the output Bo of the second frequency divider 22 with the output Ao of the first frequency divider 21, detects the phase difference PHCo, and outputs this to the loop filter 24.

[0037] The loop filter 24 has a time constant corresponding to its transfer function, and determines the response of the loop of the PLL control system. That is, the input phase difference PHCo is filtered and output. The output LPFo of the loop filter 24 is input to the voltage / current converter 25.

The voltage / current converter 25 converts the output LPFo (voltage value) from the loop filter 24 into a current value and outputs the current value to the multiplier 26. In general, in a voltage-current converter 25 composed of a MOS circuit, the output current is proportional to the square of the voltage. The multiplier 26 multiplies the input current value by the control signal M_in (signal M0Do in FIG. 3) and outputs the result to the current control oscillator 27. The current control oscillator 27 oscillates and outputs an output clock signal Fout having a frequency corresponding to the input current value. In general, in the current controlled oscillator 27 with MOS circuit power, the frequency of the output signal is proportional to the 1/2 power of the input current. Note that the PLL2 including the voltage-current converter 25 and the current-controlled oscillator 27 may be a BiCMOS circuit composed of a bipolar circuit, a bipolar circuit, and a CMOS circuit. Therefore, the frequency f (Fout) of the output clock signal Fout that is the output of the current control oscillator 27 is the control signal input to the multiplier 26, and the input current value from the voltage-current converter 25 is M−in. If Vio is Vio, then f (Fout) = M-in * (Vio * Kvco + F0). Where Kvco is a characteristic coefficient of the voltage controlled oscillator composed of the voltage-current converter 25 and the current controlled oscillator 27, and F0 is the original output frequency of the clock signal output from the oscillator 1.

The output clock signal Fout is output from the signal forming circuit 100 and also input to the first frequency divider 21. When a clock signal having a frequency f (Fout) = M_in * (Vio * Kvco + F0) is input, the first frequency divider 21 outputs a signal Ao obtained by dividing the clock signal by a frequency division ratio A. The frequency f (Ao) of the signal A 0 is a value obtained by dividing the frequency f (Fout) by the frequency division ratio A (M_in * (Vio * K vco + F0)) ZA. The signal Ao is input to the phase comparator 23 as described above.

Note that an adder can be used instead of the multiplier 26. That is, when the output frequency is constant, the input of the current control oscillator 27 is constant. Since the degree of modulation in frequency modulation is constant, an adder can be used instead of the multiplier 26. As a result, the scale of the PLL2 circuit can be reduced.

FIG. 5 is a waveform diagram of the modulation signal generation unit, and shows an example of the waveform in the modulation signal generation unit 3. FIG. 6 is a PLL waveform diagram showing an example of a waveform in the PLL that is the clock modulation unit 2.

In FIG. 5, the first sub-modulation signal generation unit 31 converts the first sub-modulation signal (FM sub-modulation wave) FMo, which is a triangular wave having a sufficiently longer period than the modulation signal FM, to the reference signal generation unit 33. Enter in. As a result, the reference signal generator 33 that generates the modulation signal FM that is essentially a triangular wave outputs an intermediate modulation signal FMsigo obtained by frequency-modulating the modulation signal FM with the first sub-modulation signal FMo in this example. Further, the second sub-modulation signal generating unit 32 outputs a second sub-modulation signal (AM sub-modulation wave) AMo that is a triangular wave having a period longer than the modulation signal FM and shorter than the first sub-modulation signal FMo. Therefore, the multiplier 34 converts the intermediate modulation signal FMsigo into the second sub-modulation signal AMo

Outputs the final modulated signal M0Do amplitude-modulated by. That is, the multiplier 34 frequency-modulates the modulation signal FM with the first sub-modulation signal FMo, and converts it to the second sub-modulation signal AMo. Outputs the final modulated signal MODo, which has been amplitude-modulated. The final modulation signal MODo is not a constant amplitude signal, rather than a constant periodic signal. The final modulation signal MODo is input to PLL2 as signal M-in in Fig. 6.

As can be seen from FIG. 5, the final modulation signal MODo output from the multiplier 34 has a change amount slightly deviating from a linear change that is not a linear change amount. Therefore, it is possible to disperse the modulation frequency in the modulation range on the spectrum and extinguish the peaks at both ends of the spectrum rather than the linear change. As a result, the peak at the modulation frequency of the spectrum can be further reduced, and the spectrum can be flattened.

In FIG. 6, the second frequency divider 22 outputs an output signal Bo obtained by dividing the clock signal Fin having a frequency of 10 MHz from the oscillator 1 by the frequency division ratio B = 3. The phase comparator 23 compares the output signal Bo of the second frequency divider 22 with the output signal Ao of the first frequency divider 21, and detects the phase difference PHCo. The loop filter 24 outputs a signal LPFo that is a result of filtering the input phase difference PHCo. The voltage / current converter 25 outputs a signal Vio obtained by converting the output LPFo (voltage value) from the loop filter 24 into a current value to the multiplier 26. The multiplier 26 multiplies the input current value Vio by the control signal M—in (final modulation signal MODo) obtained in FIG. 5 and outputs the result to the current control oscillator 27. The current control oscillator 27 oscillates and outputs an output clock signal Fout having a frequency corresponding to the input current value. The frequency f (Fout) of the output clock signal Fout is f (Fout) = M−in * (Vio * Kvco + F0). The output clock signal Fout is output from the signal forming circuit 100 and is also divided by the first divider 21 with the division ratio A = 40, and the frequency (M_in * (Vio * Kvco + F0)) / 40 The signal Ao is input to the phase comparator 23.

As described above, since the control signal M_in (final modulation signal MODo) of the multiplier 26 is a frequency-modulated triangular wave, the modulation frequency in the modulation range on the spectrum is dispersed, and as a result The peak at the modulation frequency of Tatonole can be reduced. This can be seen from the fact that the density decreases when the triangular wave in Fig. 21 (B) is modulated in the time axis (horizontal axis) direction. In addition, since the control signal M_in of the multiplier 26 is an amplitude-modulated triangular wave, the peaks at both ends of the spectrum are extinguished, and as a result, the spectrum is corrected. Torr can be flattened. This can be seen from the fact that the density decreases when the triangular wave in FIG. 21B is modulated in the voltage or current axis (vertical axis) direction.

[0047] The modulation signal FM, the first sub-modulation signal FMo, and the second sub-modulation signal AMo are all not required to be phase-synchronized with the input signal (clock signal) from the oscillator 1, and the frequency There is no need to synchronize. However, it is preferable that these signals are not phase-synchronized and frequency-synchronized with the clock signal, rather than phase-synchronized and / or frequency-synchronized. This is due to the following reasons. First, without phase synchronization and frequency synchronization, the modulation frequency in the modulation range on the spectrum can be dispersed, and the peak of the modulation frequency can be reduced. Second, spectrum flatness can be ensured by not synchronizing the phase and frequency.

For example, in general, in SSCG, when the modulation degree is ± 2% and the input frequency is 100 MHz, the period of the output signal changes between 9.8 nSec and 10.2 nSec. When the period of the output signal is 10.2nSec, if the time of 250nSec elapses, it is 24.5 periods. Meanwhile, the period of the input signal is 24 periods. Therefore, a half-circulator delay occurs. At this time, PLL2 suddenly changes to the state in which the state force advance that was detecting the delay was detected (causes a cycle slip), and tries to increase the frequency that it was trying to reduce until then. As a result, discontinuous points are generated in frequency, and the flatness of the spout is impaired.

[0049] However, by not synchronizing the phase and frequency of the modulation signal FM with the clock signal from the oscillator 1, the discontinuous operating point of the PLL 2 due to cycle slip can be spread over a long period of time, and the spectral flatness Can be prevented. Further, as in the present invention, the discontinuous operation point can be moved by amplitude-modulating the modulation signal FM with the second sub-modulation signal AMo. Thereby, the discontinuous operating point can be diffused for a long time, and the flatness of the spectrum can be prevented from being impaired.

[0050] The modulation signal does not necessarily need to be double-modulated by the first and second sub-modulation signals as described above, and may be simply modulated by one sub-modulation signal. That is, the final modulated signal may be generated by modulating the modulated signal with either the first or second sub-modulated signal (frequency modulation or amplitude modulation).

[0051] Therefore, the modulation signal generation unit 3 includes at least one sub-modulation signal generation unit, and the modulation signal May be modulated with at least one sub-modulated signal to generate a final modulated signal. That is, a clock signal, a modulation signal, and one sub-modulation signal are generated, and the modulation signal is modulated with the sub-modulation signal (frequency modulation or amplitude modulation) to generate a final modulation signal, and the clock signal is finally modulated. It is also possible to generate the output clock signal by modulating with the signal.

FIG. 7 is another signal forming circuit configuration diagram, and shows the configuration of another signal forming circuit according to the present invention. The signal forming circuit 100 in FIG. 7 has a configuration similar to that of the signal forming circuit 100 in FIG. 1, but the modulation signal generation unit 3 includes the first sub modulation signal generation unit 31 (only), and the second sub modulation signal generation unit 31 The difference is that the modulation signal generator 32 is not provided. In addition, the signal forming circuit 100 in FIG. According to this example, the signal forming circuit can have a very simple configuration, but the case where an EMI reduction effect can be obtained is limited. In other words, when there is only one (or small) operation part in the subsequent stage as shown in FIG. 17 (when there are no multiple operation parts (shown in FIG. 18)), an EMI reduction effect can be obtained. .

In this example, the reference signal generation unit 33 receives the first sub modulation signal output from the first sub modulation signal generation unit 31 and outputs the final modulation signal. As described above, the first sub-modulation signal is a signal that frequency-modulates the modulation signal, and is a triangular wave. Therefore, the final modulation signal is a signal obtained by frequency modulating the modulation signal with a triangular wave. By modulating the frequency of the modulation signal, it is possible to disperse the modulation frequency in the modulation range on the spectrum, and as a result, the peak of the modulation frequency can be reduced. Note that the final modulated signal in this example is equal to the signal FMsigo in FIG.

FIG. 8 is still another signal forming circuit configuration diagram showing the configuration of still another signal forming circuit according to the present invention. The signal forming circuit 100 in FIG. 8 has a configuration similar to that of the signal forming circuit 100 in FIG. 1, but the modulation signal generation unit 3 includes the second sub modulation signal generation unit 32 (only), and the first The difference is that the sub-modulation signal generation unit 31 is not provided. According to this example, the signal forming circuit can be made very simple, but the case where an EMI reduction effect can be obtained is limited. In other words, as shown in Fig. 18, when a PLL is provided in the subsequent stage, an EMI reduction effect can be obtained.

In this example, the modulation signal output from the reference signal generation unit 33 and the second sub-modulation signal generation The second sub-modulated signal output from the generator 32 is multiplied by the multiplier 34 to output the final modulated signal. As described above, the second sub-modulation signal is a signal that amplitude-modulates the modulation signal, and is a triangular wave. Therefore, the final modulation signal is a signal obtained by amplitude modulating the modulation signal with a triangular wave. By modulating the amplitude of the modulation signal, the peak at both ends of the spectrum can be reduced, and as a result, the spectrum can be flattened. Note that the final modulated signal in this example is a signal obtained by removing the influence of the signal FMo from the signal MODo in FIG. That is, the signal (modulated signal FM) before the frequency modulation of the signal FMsigo is amplitude-modulated with the signal AMo.

FIG. 9 is still another signal forming circuit configuration diagram, and shows the configuration of still another signal forming circuit according to the present invention. The signal forming circuit 100 in FIG. 9 has a configuration similar to that of the signal forming circuit 100 in FIG. 1, but the modulation signal generation unit 3 includes the first sub modulation signal generation unit 31 (only). The difference is that is used for two sub-modulations. In other words, in this example, the plurality of submodulation signal generation units 31 and 32 are actually composed of one submodulation signal generation unit 31 that is also used as the submodulation signal generation units 31 and 32. The final modulation signal is generated by modulating the modulation signal using one first submodulation signal generated by the one submodulation signal generation unit 31 twice (multiple times). According to this example, the chip area of the LSI can be minimized by the simplest configuration, and sufficient EMI reduction effect can be obtained for almost all periodic signals including clock signals. Can do.

In this example, when the first sub-modulation signal output from the first sub-modulation signal generation unit 31 is input, the reference signal generation unit 33 outputs a frequency-modulated modulation signal. The multiplier 34 multiplies the frequency-modulated modulation signal and the first sub-modulation signal to amplitude-modulate the frequency-modulated modulation signal. As a result, the final modulated signal is output. Therefore, the final modulated signal is a signal modulated twice by the first sub-modulated signal. By frequency-modulating and amplitude-modulating the modulation signal, it is possible to disperse the modulation frequency in the modulation range on the spectrum, and as a result, the peak of the modulation frequency can be reduced. Note that the final modulated signal in this example is a signal similar to the signal FMsigo in FIG.

In contrast to the example of FIG. 9, the modulation signal generation unit 3 includes a second sub modulation signal generation unit 32 (only), which is used for two sub modulations (frequency modulation and amplitude modulation). You may do it. This In this case, the modulation signal generation unit 3 is actually composed of one sub modulation signal generation unit 32 that is also used as the sub modulation signal generation units 31 and 32.

FIG. 10 is still another signal forming circuit configuration diagram showing the configuration of still another signal forming circuit according to the present invention. The signal forming circuit 100 in FIG. 10 has a configuration similar to that of the signal forming circuit 100 in FIG. 1, except that the modulation signal generation unit 3 includes third and fourth sub modulation signal generation units 3 11 and 321. Is different. In other words, in this example, the outputs of the other submodulation signal generation units 311 and 321 are input to the submodulation signal generation units 31 and 32, respectively. Thus, the first and second submodulation signals formed by further modulating (submodulation) the outputs of the other submodulation signal generation units 311 and 321 from the submodulation signal generation units 31 and 32, respectively. Is output. According to this example, the signal forming circuit has a complicated configuration, but the EMI reduction effect can be further improved compared to the signal forming circuit of FIG. However, the EMI reduction effect is not improved as the circuit becomes more complex.

[0060] In this example, the first and third submodulation signal generation units 31 and 311 have the same configuration,

The second and fourth submodulation signal generation units 32 and 321 have the same configuration. The first sub-modulation signal output from the first sub-modulation signal generation unit 31 is obtained by sub-modulating (frequency modulation) the output of the third sub-modulation signal generation unit 311 and output from the second sub-modulation signal generation unit 32. The second sub-modulated signal is obtained by sub-modulating (amplitude modulating) the output of the fourth sub-modulated signal generating unit 321. Therefore, the final modulation signal is further (sub) modulated by the first and second sub modulation signals once (sub) modulated. The clock signal is further modulated by the final modulation signal. That is, the clock signal is triple modulated.

Thus, in the present invention, the submodulation wave can be further submodulated.

That is, the example of FIG. 1 is an example of double modulation in which the clock signal is modulated and sub-modulated, but this example is an example of triple modulation of the clock signal. If the spectrum is observed closely, the frequency component of the sub-modulation signal is also present, which contributes to the deterioration of the spectrum. Therefore, the frequency component of the sub-modulated signal can be attenuated by triple modulation (frequency modulation) of the clock signal according to the present invention. Similarly, since amplitude modulation also has a slight effect on the frequency component force spectrum, the frequency component of the sub-modulation signal can be attenuated to some extent by modulating the clock signal in triplicate (amplitude modulation) according to the present invention. In wear.

[0062] It is possible to modulate the clock signal quadruple or more in order to attenuate the frequency spectrum of the sub-submodulation wave. However, in this case, the effect of attenuating the frequency spectrum is reduced for an increase in the circuit scale of the modulation signal generator 3.

[0063] Also, the first and third sub-modulation signal generation units 31 and 311 have different configurations, and the second and fourth sub-modulation signal generation units 32 and 321 have different configurations. Also good. That is, when either one is a circuit that performs frequency modulation, the other may be a circuit that performs amplitude modulation. Furthermore, only the first and third sub-modulation signal generation units 31 and 311 having the same or different configurations may be provided, and the second and fourth sub-modulation signal generation units 32 and 321 may be omitted. Moreover, the reverse may be sufficient. The same applies when the clock signal is modulated in quadruple or higher.

[0064] In this way, by inputting the output of another submodulation signal generation unit to at least one submodulation signal generation unit, another submodulation signal generation unit from at least one submodulation signal generation unit The sub-modulation signal formed by further (sub-) modulating the output of the signal may be output.

FIG. 11A is still another signal forming circuit configuration diagram showing the configuration of still another signal forming circuit according to the present invention. A signal forming circuit 100 in FIG. 11A is an example in which, in the signal forming circuit 100 in FIG. 1, the clock modulation unit 2 is configured by an integrator and a variable delay unit instead of the PLL.

The integrator outputs an integration signal obtained by integrating the final modulation signal output from the modulation signal generation unit 3. The integrator is composed of, for example, a known integration circuit. As shown in Fig. 11 (B), the integrator is reset so that the output becomes 0 π when the output reaches 2 π, and the output is output when the output becomes Ο π. 2 Reset to π. The variable delay unit receives the clock signal output from the oscillator 1 as an input, uses an integrated signal obtained by integrating the final modulation signal as a control signal, and outputs an output clock signal. The variable delay device includes, for example, a known gmC delay circuit, a phase interpolation circuit, a series connection circuit of a plurality of inverters, and the like.

[0067] As can be seen from FIG. 1, the final modulation signal output from the modulation signal generator 3 is Has a corresponding dimension. In this example, by integrating the final modulation signal having such a property, a signal having a dimension corresponding to the phase is obtained as an integration signal. By providing this integration signal as a control signal to the variable delay device, the delay amount of the clock signal can be changed based on the final modulation signal obtained by frequency-modulating and amplitude-modulating the modulation signal. Therefore, the signal forming circuit 100 of this example can obtain the same result as the signal forming circuit 100 of FIG.

Note that the clock modulation unit 2 of this example is not limited to the signal forming circuit 100 of FIG. 1, but the signal forming circuit 100 of FIG. 7 or FIG. 8 described above, or the signal forming circuit of FIG. 17 or FIG. Can be applied to 100.

FIG. 1 and FIG. 11 described above are examples in which the signal forming circuit of the present invention is configured by an analog circuit, but the signal forming circuit of the present invention can also be configured by a digital circuit. The FIG. 12 to FIG. 16 show examples in which the signal forming circuit of the present invention is configured by a digital circuit

FIG. 12 is still another signal forming circuit configuration diagram, and shows the configuration of still another signal forming circuit according to the present invention. FIG. 13 is a waveform diagram of the modulation signal generation unit, and shows an example of a waveform in the modulation signal generation unit configured by the digital circuit of the signal formation circuit of FIG. According to this example, it is possible to obtain a sufficient EMI reduction effect for almost all periodic signals including a clock signal by a digital circuit having a relatively simple configuration.

The signal forming circuit 100 in FIG. 12 has a force similar to that of the signal forming circuit 100 in FIG. 1. The modulation signal generating unit 3 is configured by a digital circuit, and accompanying this, The difference is that the configuration of PLL2 is changed. That is, in this example, the modulation signal generating unit 3 includes a third frequency divider 35, a first triangular wave generating unit 36, a second triangular wave generating unit 37, a fourth frequency divider 38, and an adder / subtractor 39. The PLL 2 includes a voltage-controlled oscillator (VC0) 210 instead of the voltage-current converter 25, the multiplier 26, and the current-controlled oscillator (ICO) 27, and the control signal from the modulation signal generator 3 is divided by the first frequency. Receive with vessel 21 'and loop filter 24'.

[0072] As described above, the output frequency Fout of the PLL is usually determined as f (Fout) = f (Fin) · ΑΖΒ. As is well known, the output frequency Fout can be modulated by periodically changing the set value of the first frequency divider 21 ′. That is, two values are set for the first frequency divider 21 ′. Prepare values NO and N1, and set value NO at time t2n and value N1 at time Ijt2n + 1 to first divider 21 'and select the loop constant of loop filter 24' appropriately. Thus, modulation can be performed using the transient response due to the integral characteristic of the loop filter 24 '. In this case, the output frequency Fout repeats a continuous change from NO ZM 'Fin to Nl ZM' Fin.

[0073] In the example of FIG. 12, this modulation method is expanded so that Nk and Nk are not fixed.

(k = 0, l, 2 ...) and set time tk (k = 0, l, 2 ...) are calculated sequentially and set to the first divider 21 'each time. As a result, the output frequency Fout can be made a transition force S as in the example of FIG.

The examples in FIGS. 12 and 13 show examples in which the modulated wave is sub-modulated by both frequency modulation and amplitude modulation as in the example of FIG. Therefore, in this example, Nk is obtained as follows.

The reference clock signal generation circuit 4 generates and outputs a modulation signal (not shown) which is a reference signal (reference signal) for generating the final modulation signal. Therefore, this example is also an example in which the reference signal generation unit (33) is provided outside the signal forming circuit 100. In this example, the reference signal or modulation signal is the second clock signal. The second clock signal has a frequency that is not an integral multiple of the clock signal (first clock signal) output from the oscillator 1 in order to sufficiently obtain the effect of submodulation.

First, as shown in FIG. 13, the first triangular wave generator 36 creates a number ijijFMk corresponding to the frequency submodulation wave from the reference clock signal using an up / down counter or an addition / subtraction circuit. Next, the third divider 35 divides the reference clock signal using the generated sequence FMk. As a result, the divided reference clock signal becomes a frequency-modulated clock signal tk. Figure 13 shows the clock signal tk. The clock signal tk has a modulated period.

The frequency-modulated clock signal tk is supplied as a clock signal to the second triangular wave generation unit 37 in the next stage. The second triangular wave generator 37 generates an amplitude submodulated wave. That is, the second triangular wave generation unit 37 generates the output Sk by adding or subtracting the constant C to the current output value of the second triangular wave generation unit 37 for each frequency-modulated clock. Figure Output Sk It is shown in 13.

The number of bits of the adder / subtracter (not shown) in the second triangular wave generation unit 37 is finite, and there is a maximum numerical value that can be processed by the second triangular wave generation unit 37. Assuming that the value is G max, G max is determined by the number of bits of the adder / subtracter in the second triangular wave generator 37. When the number of bits is n, the minimum numerical value that can be handled by the second triangular wave generation unit 37 is the maximum numerical value Gmax_ (2 n_l).

[0079] When the second triangular wave generator 37 functions as an adder, the constant C is added for each frequency submodulation clock. When the result of this addition reaches the maximum value due to the limitation on the number of bits, the second triangular wave generator 37 switches to a subtracter. As a result, the constant C is subtracted for each frequency sub-modulation clock, and thereafter, the subtraction is continued until the minimum value is reached due to the limitation on the number of bits. In addition, when the output of the second triangular wave generation unit 37 reaches the minimum value in the subtractor state, the second triangular wave generation unit 37 switches to an adder, and the constant C is set for each frequency submodulation clock. It is added until it reaches the maximum value G max that can be handled by this calculator.

By repeating the above processing, the numerical value of the output of the second triangular wave generator 37 repeats the increase to the maximum value and the decrease to the minimum value according to the constant C for each frequency submodulation clock. As a result, a sequence Sk representing the triangular wave subjected to frequency submodulation is generated.

[0081] On the other hand, l / 2tk is obtained by dividing the frequency-modulated clock signal tk by two. Figure 13 shows the signal l / 2tk. The signal l / 2tk is high when the value of k is even and low when it is odd. The signal l / 2tk is input to the adder / subtractor 39 to switch between addition and subtraction. That is, the adder / subtracter 39 is switched to an adder when k is an even number, and is switched to a subtractor when k is an odd number. As a result, the adder / subtractor 39 obtains Nk = Fn +/− Sk by repeating the addition / subtraction alternately for the number 歹 IjSk using the set frequency setting value Fn and the signal lZ2tk. This generates a sequence of Nk.

[0082] An appropriate loop constant can be obtained by multiplying the original loop constant by k -Nk / FMk or k -Nk / tk. Where k is a proportionality constant. Set the generated sequence Nk to the first divider 21 'for each generated frequency submodulated clock and set the appropriate loop constant Is set to loop filter 24 by Nk and FMk. As a result, the output LPFo of the loop filter 24 'becomes as shown in FIG. By inputting this output LPFo to the voltage controlled oscillator 210, it is possible to generate a clock signal Font that is modulated by a modulation wave subjected to frequency sub-modulation and amplitude sub-modulation. Therefore, according to the present invention, by performing frequency sub-modulation and amplitude sub-modulation on the modulated wave, the spectrum can be effectively spread and attenuated, and as a result, EMI can be greatly reduced.

FIG. 14 is still another signal forming circuit configuration diagram, and shows the configuration of still another signal forming circuit according to the present invention. That is, the signal forming circuit in FIG. 14 is configured by a digital circuit, and shows an example in which the modulated wave is submodulated by frequency modulation as in the example of FIG. Therefore, the relationship between FIG. 12 and FIG. 14 corresponds to the relationship between FIG. 1 and FIG.

The signal forming circuit 100 in FIG. 14 has a configuration similar to that of the signal forming circuit 100 in FIG. 12, except that the second triangular wave generating unit 37 is omitted in the modulation signal generating unit 3. Different. As a result, the reference clock signal, which is a modulation signal, can be frequency-modulated. As a result, the modulation frequency can be dispersed and the peak thereof can be reduced.

FIG. 15 is still another signal forming circuit configuration diagram showing the configuration of still another signal forming circuit according to the present invention. That is, the signal forming circuit in FIG. 15 is configured by a digital circuit, and shows an example in which the modulated wave is submodulated by amplitude modulation as in the example in FIG. Therefore, the relationship between FIG. 12 and FIG. 15 corresponds to the relationship between FIG. 1 and FIG.

The signal forming circuit 100 in FIG. 15 has a configuration similar to that of the signal forming circuit 100 in FIG. 12, except that the first triangular wave generating unit 36 is omitted from the modulation signal generating unit 3. The connection is changed accordingly. As a result, the amplitude of the reference clock signal, which is a modulation signal, can be modulated, and as a result, the peaks at both ends of the spectrum can be reduced to flatten the spectrum.

FIG. 16 is still another signal forming circuit configuration diagram, and shows the configuration of still another signal forming circuit according to the present invention. That is, the signal forming circuit in FIG. 16 is configured by a digital circuit, and in the same manner as in the example of FIG. 10, an example of further submodulating the submodulation wave for modulating the modulation wave (an example of multiple modulation). Show. Therefore, the relationship between FIG. 12 and FIG. 16 corresponds to the relationship between FIG. 1 and FIG. The signal forming circuit 100 in FIG. 16 has a configuration similar to that of the signal forming circuit 100 in FIG. 12, but in the modulation signal generating unit 3, the third triangular wave is placed in front of the first triangular wave generating unit 36. The difference is that the generation unit 310 is inserted and the fourth triangular wave generation unit 312 is inserted before the second triangular wave generation unit 37. As a result, the reference clock signal, which is a modulation signal, is further (sub) modulated by the first and second sub modulation signals once modulated (sub). Therefore, as in FIG. 10, the reference clock signal that is the modulation signal is triple-modulated.

As described above, even when the signal forming circuit is configured by a digital circuit, the reference clock signal, which is a modulated wave, can be modulated in a triple (multiplex) manner. As described above, the frequency component of the sub-modulation signal also contributes to the deterioration of the spectrum characteristics. Therefore, the frequency component of the sub-modulation signal can be attenuated to some extent by triple modulation of the reference clock signal. Furthermore, as described above, it is possible to modulate the reference clock signal, which is a modulated wave, to quadruple or more. However, in this case, the effect of attenuating the frequency spectrum is reduced for an increase in the circuit scale of the modulation signal generator 3.

FIG. 17 is a configuration diagram of an electronic device, and shows an example of the configuration of an electronic device 200 including the signal forming circuit 100 ′ of the present invention. The electronic device 200 includes a signal forming circuit 100 ′ according to the present invention and an operation unit 300 that performs a predetermined operation based on an output clock signal output from the signal forming circuit 100 ′. The signal forming circuit 100 ′ of the present invention has one of the configurations shown in FIG. 1, FIG. 7, or FIG. Therefore, the modulation signal generation unit 3 only needs to include the sub modulation signal generation unit 31 or 32 that outputs at least one sub modulation signal. FIG. 17 shows an example in which two sub-modulation signal generation units 31 and 32 are provided.

[0091] For example, the operation unit 300 includes, for example, a personal computer, a facsimile machine, a copier, and a printer. Since the wiring that propagates the clock signal extends long inside the large housing, these wirings can easily operate as an antenna. Therefore, in reality, EMI is reduced by attaching the electromagnetic wave absorbing sheet inside the housing and absorbing the emitted electromagnetic waves. According to the present invention, it is possible to omit or thin the attachment of the electromagnetic wave absorbing sheet while reducing EMI, and to reduce the cost.

[0092] In addition, the operating unit 300 may have, for example, a class D amplifier power. Class D amplifiers filter the digital signal obtained by processing the clock signal and input it directly to the speaker. It is said that it is efficient. Since the class D amplifier is accompanied by switching of a large current, it is easy to radiate electromagnetic waves. However, according to the present invention, radiation of electromagnetic waves can be suppressed and EMI can be reduced.

FIG. 18 is a configuration diagram of another electronic device, and shows an example of the configuration of another electronic device 200 including the signal forming circuit of the present invention. The electronic device in FIG. 18 has a configuration similar to the configuration of the electronic device in FIG. 17, but the operation unit 300 includes a plurality of PLLs 301a 301η and a plurality of operation units 302a to 302η corresponding thereto. The signal forming circuit 100 ′ has one of the configurations shown in FIG. 1, FIG. 8, FIG. 11, and FIG. FIG. 18 shows an example in which two sub-modulation signal generation units 31 and 32 are provided.

[0094] Each of the plurality of operation units 302a to 302η includes, for example, a notebook personal computer, a facsimile, a copier, a printer, a class D amplifier, and the like. The plurality of operating units 302a 302 n each have an operating frequency fa fn having a different value. Therefore, each of the plurality of PLLs 30 la-301η supplies the operating frequency fa-fn to the corresponding operating unit 302a-302η based on the output Fout from the clock modulation unit 2.

[0095] At this time, in actuality, as shown in FIG. 21 (A), due to the band limitation of the PLL 301 connected to the subsequent stage of the signal forming circuit 100 ', the waveform of the apex of the triangular wave becomes dull. Some peaks appear at the edges. Therefore, in this example, the amount of change in amplitude modulation by the second sub modulation signal generation unit 32 is increased. As a result, it is possible to compensate for the dull waveform at the apex of the triangular wave due to the band limitation of PLL301. As a result, while reducing EMI, attachment of the electromagnetic wave absorbing sheet can be omitted or made thinner, and the cost can be reduced.

Note that the signal forming circuit 100 ′ of the present invention includes the oscillator 1 as a part thereof as shown in FIGS. Similarly, the signal forming circuit of the present invention shown in each of FIGS. 1, 7, and 8 may include the oscillator 1 as a part thereof.

The present invention is not limited to clock signals, and can be widely applied to circuits that use periodically changing signals such as triangular waves and sine waves. Accordingly, the present invention is, for example, a data interface driving circuit (or driver), a photodiode (ie, laser diode or LED) driving circuit, a motor driving circuit, a display driving circuit, an EL driving circuit, a CCD driving circuit, etc. Can be applied to.

[0098] In general data interface driving circuits, for example, single-ended circuits or differential data transmission circuits, the wiring length is generally long, and when data is transmitted, the driving current is large and alternating current or pulsating current (plus or minus) It is easy to radiate electromagnetic waves. The photodiode driving circuit may be driven by alternating current (or alternating voltage) when the diode is turned on. In this case, the drive current is large, and it is driven by an alternating current or a pulsating flow, so that it is easy to radiate electromagnetic waves. The motor drive circuit is apt to radiate electromagnetic waves because the motor drive current is very large and is driven by alternating current or pulsating current. Since the display drive circuit and EL drive circuit have a large display area, the drive current is very large, and the display drive circuit and the EL drive circuit are driven by an alternating current or a pulsating current, so that they easily radiate electromagnetic waves. Since the CCD drive circuit is driven by alternating current or pulsating current when sending image signals from the CCD, it easily radiates electromagnetic waves.

Therefore, such a circuit radiates electromagnetic waves and deteriorates EMI characteristics. However, according to the present invention, in such a circuit or an electronic apparatus including such a circuit, the amount of radiated electromagnetic waves can be reduced and EMI can be reduced.

Industrial applicability

[0100] According to the present invention, in the signal forming circuit and the signal forming method, at least frequency modulation or amplitude modulation is performed on the modulation signal using at least one sub-modulation signal, so that the period of the clock signal or the like is increased. Multiple modulations of a typical signal. As a result, the peak of the modulation frequency can be reduced without making the modulation frequency lower than the frequency (about 20 kHz) that generates vibration noise, or without using a modulation wave that emphasizes the top of the triangular wave. Or the spectrum can be flattened. Therefore, it is not necessary to consider the characteristics of the modulator, which does not require the use of a complicated clock generation circuit, due to the flatness of the spectrum. As a result, it is possible to reduce the EMI of the signal forming circuit and the electronic device using the signal forming circuit by reducing the spectrum peak or flattening the spectrum.

[0101] According to the present invention, the electronic device includes the signal forming circuit of the present invention that multiplexly modulates a periodic signal such as a clock signal, thereby at least reducing the peak of the spike. Alternatively, the spectrum can be flattened. Therefore, the spectral flatness Therefore, it is not necessary to consider the characteristics of the modulator, which does not require the use of a complicated clock generator circuit. As a result, EMI of the electronic device can be reduced by at least reducing the spectrum peak or flattening the spectrum.

Claims

The scope of the claims

[1] A signal forming circuit that forms an output signal capable of reducing EMI,

It comprises at least one sub-modulation signal generator that outputs a sub-modulation signal that modulates a reference signal that is a reference for generating a final modulation signal, and modulates the reference signal with at least one sub-modulation signal. A modulation signal generator for outputting the final modulation signal generated by

An output signal generated by modulating the periodic signal output from the periodic signal forming circuit with the final modulation signal, and the EMI can be reduced by reducing the spectrum caused by the output signal. With a signal modulator that outputs output signals

A signal forming circuit.

[2] The modulation signal generation unit includes one sub modulation signal generation unit

The signal forming circuit according to claim 1, wherein:

[3] The sub-modulation signal generation unit outputs a signal that frequency-modulates the reference signal as the sub-modulation signal.

The signal forming circuit according to claim 2, wherein:

[4] The sub-modulation signal generation unit outputs a signal for amplitude-modulating the reference signal as the sub-modulation signal

The signal forming circuit according to claim 2, wherein:

[5] The modulation signal generation unit includes a plurality of sub-modulation signal generation units having the same or different configurations.

The signal forming circuit according to claim 1, wherein:

[6] The modulation signal generation unit includes a first sub modulation signal generation unit that outputs a first sub modulation signal;

And a second sub-modulation signal generation unit that outputs two sub-modulation signals, and outputs a final modulation signal generated by modulating the reference signal with the first and second sub-modulation signals. Item 5. The signal forming circuit according to Item 5.

[7] The plurality of sub-modulation signal generation units include one sub-modulation signal generation unit that is also used as the plurality of sub-modulation signal generation units, and the reference signal is used as the one sub-modulation signal generation unit. Outputs the final modulation signal generated by modulating one sub-modulation signal generated by multiple times.

6. The signal forming circuit according to claim 5, wherein:

[8] By inputting the output of the other sub-modulation signal generation unit to at least one sub-modulation signal generation unit, the at least one sub-modulation signal generation unit outputs the other sub-modulation signal. Outputs the sub-modulation signal formed by further modulating the output of the generator

6. The signal forming circuit according to claim 5, wherein:

[9] The first sub-modulation signal generation unit outputs a signal that frequency-modulates the reference signal as the first sub-modulation signal.

The signal forming circuit according to claim 6.

[10] The modulation signal generation unit outputs the final modulation signal by receiving the first sub modulation signal output from the first sub modulation signal generation unit.

The signal forming circuit according to claim 9.

[11] The second sub-modulation signal generation unit outputs a signal for amplitude-modulating the reference signal as the second sub-modulation signal.

The signal forming circuit according to claim 6.

[12] The modulation signal generator further includes a multiplier,

The multiplier outputs the final modulation signal by multiplying the modulation signal output from the modulation signal generation unit by the second sub modulation signal output from the second sub modulation signal generation unit. Do

12. The signal forming circuit according to claim 11, wherein:

[13] The first sub-modulation signal generation unit outputs a signal that frequency-modulates the reference signal as the first sub-modulation signal,

The second sub-modulation signal generation unit outputs a signal for amplitude-modulating the reference signal as the second sub-modulation signal.

The signal forming circuit according to claim 6.

[14] The first sub-modulation signal is a triangular wave having a period sufficiently longer than the reference signal. The second sub modulation signal is a triangular wave having a longer period than the reference signal and shorter than the first sub modulation signal.

The signal forming circuit according to claim 13.

[15] The modulation signal generation unit outputs the intermediate modulation signal by receiving the first sub modulation signal output from the first sub modulation signal generation unit,

The modulation signal generator further includes a multiplier,

The multiplier multiplies the intermediate modulation signal output from the modulation signal generation unit by the second sub modulation signal output from the second sub modulation signal generation unit, thereby obtaining the final modulation signal. Output

The signal forming circuit according to claim 13.

[16] The periodic signal forming circuit is an oscillator, and the periodic signal is a clock signal.

The signal forming circuit according to claim 1, wherein:

[17] The reference signal is any one of a triangular wave, a sine wave, and a clock.

The signal forming circuit according to claim 1, wherein:

[18] The sub-modulation signal may be a triangular wave, a sine wave, a cosine wave, a signal composed of a sum of a sine wave having an integral multiple frequency and a cosine wave, a signal generated by an irregular process, or these signals. Is a signal obtained by combining

The signal forming circuit according to claim 1, wherein:

[19] The signal modulation unit includes a phase synchronization circuit that receives the periodic signal output from the periodic signal forming circuit, receives the final modulation signal as a control signal, and outputs the output signal.

The signal forming circuit according to claim 1, wherein:

[20] The signal modulation unit includes:

An integrator that outputs an integrated signal obtained by integrating the final modulation signal;

2. The variable delay device according to claim 1, further comprising: a variable delay device that receives the periodic signal output from the periodic signal forming circuit as input, uses the integrated signal of the final modulation signal as a control signal, and outputs the output signal. Signal forming circuit.

[21] A signal forming method for forming an output signal capable of reducing EMI, Generate at least one submodulation signal,

The final modulation signal is generated by modulating a reference signal serving as a reference for generating a final modulation signal with the at least one sub-modulation signal,

By modulating a periodic signal with the final modulation signal, an output signal capable of reducing the EMI is generated by reducing a spectrum caused by the output signal.

A signal forming method.

[22] generating the first and second submodulation signals as the submodulation signal,

A final modulation signal is generated by modulating the modulation signal with the first and second sub-modulation signals.

The signal forming method according to claim 21, wherein

[23] The periodic signal is a clock signal.

23. The signal forming method according to claim 22, wherein:

[24] The sub-modulation signal includes at least one of a first sub-modulation signal that frequency-modulates the reference signal, or a second sub-modulation signal that amplitude-modulates the reference signal.

23. The signal forming method according to claim 22, wherein:

[25] a periodic signal forming circuit for outputting a periodic signal;

A reference signal generation unit that outputs a reference signal serving as a reference for generating a final modulation signal; and a sub-modulation signal generation unit that outputs at least one sub-modulation signal that modulates the reference signal. A modulation signal generator for outputting the final modulation signal generated by modulating the at least one sub-modulation signal;

It is an output signal generated by modulating the periodic signal output from the periodic signal forming circuit with the final modulation signal, and the EMI can be reduced by reducing the spectrum caused by the output signal. A signal modulation unit that outputs an output and an operation unit that performs a predetermined operation based on the output signal

An electronic device characterized by that.