WO2006007764A1

WO2006007764A1 - A low temperature polysilicon thin film transistor and method of manufacturing the same

Info

Publication number: WO2006007764A1
Application number: PCT/CN2004/000848
Authority: WO
Inventors: Zhengzhang Guo
Original assignee: Quanta Display Inc.; Quanta Display Japan Inc.
Priority date: 2004-07-22
Filing date: 2004-07-22
Publication date: 2006-01-26

Abstract

A low temperature polysilicon thin film transistor is provided. It comprises a gate electrode, a gate dielectric layer, a patterned silicon layer, a patterned insulating layer, an ohmic contact layer and a source/drain electrode layer. The gate electrode and the gate dielectric layer are disposed sequently on a substrate. The patterned silicon layer and the patterned insulating layer are disposed sequently above the gate dielectric layer. And the patterned silicon layer comprises a polysilicon channel region and a amorphous silicon hot carrier suppressing region. The ohmic contact layer is disposed on a part of the patterned insulating layer,which is over the gate dielectric layer and the amorphous silicon hot carrier suppressing region, and connects to the amorphous silicon hot cagier region. The source/drain electrode layer is disposed on the gate dielectric layer and the ohmic contact layer. The amorphous silicon hot carrier suppressing region is positioned between the ohmic contact layer and the polysilicon channel region, to suppress hot carrier effect, to reduce leakage current, thus it improves efficiency of the transistor.

Description

Low-temperature polysilicon thin film transistor and manufacturing method thereof

The present invention relates to a structure of a transistor and a method of fabricating the same, and, in particular, to a low temperature poly-silicon (LTPS) transistor and a method of fabricating the same. Background technique

In general components, switches are required to drive the operation of the components. Taking an active display element as an example, it is usually a Thin Film Transistor (TFT) as a driving switch. Thin film transistors can be classified into amorphous silicon (abbreviated as a-Si) thin film transistors and poly-silicon thin film transistors according to the material of the channel layer. In addition, the thin film transistor can be divided into a top-gate TFT and a bottom-gate TFT according to the relative positions of the channel layer and the gate. Since the bottom gate type thin film transistor process has a relatively uncontaminated interface (insulating layer/amorphous silicon layer) and can be combined with mature back-channel etch technology, current generations of liquid crystals Panel manufacturers generally use amorphous silicon bottom gate thin film transistors as the switching elements of liquid crystal displays. However, polycrystalline silicon thin film transistors have received increasing attention from the market because they consume less power and have higher electron mobility than amorphous silicon thin film transistors.

The processing temperature of early polysilicon thin film transistors was as high as 1000 degrees Celsius, so the choice of substrate material was greatly limited. However, due to the development of laser technology, the process temperature can be reduced to below 600 degrees Celsius, and the process is formed by using such a process. A polysilicon thin film transistor is called a low temperature polysilicon thin film transistor. The main technique of this process is to use a laser annealing process to melt and crystallize the amorphous silicon film formed on the substrate (Re-ciystallization). It becomes a polysilicon film, and the commonly used laser annealing process is excimer laser annealing.

(Excimer Laser Annealing, referred to as ELA) process.

However, although the polysilicon thin film transistor having a high carrier mobility and a high driving current (approximately ^10.4 microamperes) excellent properties, but relatively speaking, which also has a high leakage current (leakage current) (about 10_ ⁹ microamperes), and it is easy to induce a hot carrier effect at the drain, which in turn leads to component degradation. Therefore, the design of Light Doped Drain (LDD) is added between the channel layer and the source/drain in the transistor to avoid the hot carrier effect.

1A to 1E are schematic cross-sectional views showing a manufacturing process of a conventional low-gate polysilicon thin film transistor of a bottom gate type. Referring to FIG. 1A, a gate 102, a gate dielectric layer 104, and an amorphous silicon layer 106 are sequentially formed on the substrate 100. Then, the ELA process is performed, and the amorphous silicon layer 106 is irradiated with the excimer laser beam 118 to be melted and then crystallized to become a polysilicon layer. Referring to FIG. 1B, the polysilicon layer 106a is patterned to define the active region of the thin film transistor.

Referring to FIG. 1C, a silicon oxide layer 108 is formed on the polysilicon layer 106a over the gate 102, and the doping process implants the ions 130 with the silicon oxide layer 108 as a mask/mask to define the ohmic contact of the transistor. Layer 110. The polysilicon layer 106a above the gate 102 is the channel layer 112 of the transistor.

Referring to FIG. 1D, another shallow silicon oxide layer 108a is used as a mask to perform a shallow doping drain process, and a lower concentration of ions 140 is implanted to form a shallow doping between the channel layer 112 and the ohmic contact layer 110. Miscellaneous drain 114. Finally, a source/drain layer 116 is formed on the ohmic contact layer 110 and the gate dielectric layer 104, and a portion of the silicon oxide layer 108a is covered, that is, the low-temperature polysilicon thin film transistor 120 of the bottom gate type is completed, as shown in FIG. 1E. .

It can be seen from the above process that at least five masks are required to complete the existing low temperature polysilicon thin film transistor 120, and the LDD process is complicated, so that the low temperature polysilicon thin film transistor has a high manufacturing cost. Summary of the invention

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a low temperature polysilicon thin film transistor for improving the element characteristics of a transistor through an amorphous silicon hot carrier suppression region therein.

Another object of the present invention is to provide a method for fabricating a low temperature polysilicon thin film transistor which can save manufacturing cost, and can also appropriately arrange an amorphous silicon thermal carrier suppression region in a transistor to improve element characteristics of the transistor.

The present invention provides a low temperature polysilicon thin film transistor which is mainly composed of a gate, a gate dielectric layer, a patterned silicon layer, a patterned insulating layer, an ohmic contact layer and a source/drain layer which are sequentially disposed on a substrate. Wherein, the patterned silicon layer is disposed on the gate dielectric layer and is located directly above the gate. And the patterned silicon layer comprises a polysilicon channel region and an amorphous silicon thermal carrier suppression region on both sides of the polysilicon channel region, and the amorphous silicon thermal carrier suppression region herein can be used to reduce the heat carrier generated during operation of the transistor. The probability of degradation due to effects. The patterned insulating layer covers the patterned silicon layer, and the ohmic contact layer is disposed on a portion of the insulating layer and a portion of the insulating layer above the amorphous silicon thermal carrier suppression region to expose the patterned insulating layer above the polysilicon channel region, and Amorphous silicon hot carrier suppression zone is connected. The source/drain layers are disposed on the ohmic contact layer, even on a portion of the substrate.

According to an embodiment of the invention, the low temperature polysilicon thin film transistor further includes a protective layer disposed on the source/drain layer and covering the insulating layer.

According to an embodiment of the present invention, the ohmic contact layer of the present invention may be an n-type doped ohmic contact layer or a p-type doped ohmic contact layer. In other words, the low temperature polysilicon thin film transistor of the present invention may be an n-type transistor or a p-type transistor. In yet another embodiment, the material of the insulating layer is, for example, silicon nitride or silicon oxide.

The invention provides a method for manufacturing a low temperature polysilicon thin film transistor, first forming a gate on a substrate, and then forming a gate dielectric layer on the gate and the substrate. Then form the first non-order a crystalline silicon layer, a patterned insulating layer, and a second amorphous silicon layer. Wherein, the patterned insulating layer is disposed on a portion of the first amorphous silicon layer and directly above the gate. The second patterned amorphous silicon layer is disposed on the first patterned amorphous silicon layer and the patterned insulating layer. The first and second amorphous silicon layers are then patterned to form first and second patterned amorphous silicon layers to expose portions of the gate dielectric layer. Wherein, the second patterned amorphous silicon layer simultaneously exposes a portion of the patterned insulating layer.

After the second patterned amorphous silicon layer is disposed on the substrate, a portion of the first patterned amorphous silicon layer is then melted and then recrystallized to form a polysilicon channel region directly above the gate. Wherein, an amorphous silicon thermal carrier suppression region is naturally formed under the overlap of the second patterned amorphous silicon layer and the patterned insulating layer. A source/drain layer is then formed over the second patterned amorphous silicon layer.

The present invention also provides a method of fabricating a low temperature polysilicon thin film transistor by first forming a gate on a substrate and then forming an intermediate dielectric layer on the interpole and the substrate. Then, a first amorphous silicon layer, a patterned insulating layer, and a second amorphous silicon layer are sequentially formed. Wherein, the patterned insulating layer is disposed on a portion of the first amorphous silicon layer and directly above the gate. The second patterned amorphous silicon layer is disposed on the first patterned amorphous silicon layer and the patterned insulating layer. The first and second amorphous silicon layers are then patterned to form first and second patterned amorphous silicon layers to expose portions of the gate dielectric layer. Wherein, the second patterned amorphous silicon layer simultaneously exposes a portion of the patterned insulating layer.

After the second patterned amorphous silicon layer is disposed on the substrate, the source/drain layer is formed on the second patterned amorphous silicon layer, and the source/drain layer is made of metal or other conductive material. material. A portion of the first patterned amorphous silicon layer above the gate is then melted and recrystallized to form a polysilicon channel region. Wherein, an amorphous silicon thermal carrier suppression region is naturally formed on both sides of the polysilicon channel region.

In accordance with an embodiment of the present invention, the method of forming the polysilicon channel region is, for example, a laser annealing process, which in an embodiment is, for example, an excimer laser annealing process.

According to an embodiment of the invention, before the forming the patterned insulating layer and before forming the source/drain layer, the first amorphous silicon layer is further doped. In another embodiment, it is for example The first amorphous silicon layer and the second amorphous silicon layer are doped simultaneously or simultaneously after forming the second amorphous silicon layer and before forming the source/drain layer. In addition, in still another embodiment of the present invention, the portion of the polysilicon channel region and the amorphous silicon hot carrier suppression region may be first after forming the polysilicon channel region and before forming the source/drain layer. The patterned amorphous silicon layer and the second patterned amorphous silicon layer are doped. Moreover, after completing the cumbersome process, a portion of the first patterned amorphous silicon layer and the second patterned amorphous silicon layer doped with impurities may be activated.

(activation) process to repair the crystal lattice defects (defects of crystal latticed

According to the embodiment of the present invention, when the polysilicon channel region is formed, the first patterned amorphous silicon layer and the second patterned amorphous silicon outside the polysilicon channel region and the amorphous silicon hot carrier suppression region may be simultaneously simultaneously formed. The layer is melted and then recrystallized to form a polysilicon ohmic contact layer.

According to an embodiment of the invention, after forming the source/drain layer, further comprising forming a protective layer on the source/drain layer and the substrate and covering the patterned insulating layer.

Since the process of the low-temperature polysilicon thin film transistor of the present invention is less than the process of the conventional low-temperature polysilicon thin film transistor, a LDD process and a photomask can be eliminated, thereby saving manufacturing costs. Further, the low temperature polysilicon thin film transistor of the present invention can have both a high driving current of a polysilicon thin film transistor and a low leakage current of an amorphous silicon thin film transistor.

The above and other objects, features and advantages of the present invention will become more < DRAWINGS

1A to 1E are schematic cross-sectional views showing a manufacturing process of a conventional low-temperature polysilicon thin film transistor of a bottom gate type.

2A to 2H are schematic cross-sectional views showing a manufacturing process of a low temperature polysilicon thin film transistor according to a preferred embodiment of the present invention.

3A to 3C illustrate a low temperature polysilicon thin film transistor according to another embodiment of the present invention. A schematic diagram of the process section of the manufacturing section.

4A to 4B are cross-sectional views showing a process of manufacturing a low temperature polysilicon thin film transistor according to still another embodiment of the present invention.

5A to 5B are schematic cross-sectional views showing a process of manufacturing a low temperature polysilicon thin film transistor according to another embodiment of the present invention. detailed description

The invention designs a region composed of amorphous silicon between the channel region and the source/drain region of the low temperature polysilicon thin film transistor to reduce the impact of high-speed electrons in the source/drain regions under high electric field, thereby avoiding heat The occurrence of the carrier effect. Moreover, the low temperature polysilicon film transistor of the present invention can be completed in a variety of different processes, as will be described in the following examples. It is to be noted that the following embodiments are intended to illustrate the low temperature polysilicon thin film transistor of the present invention and a method of fabricating the same, and are not intended to limit the present invention. Those skilled in the art can make appropriate modifications and variations in accordance with the teachings of the present invention, which are also within the scope of the present invention. First embodiment

2A to 2H are schematic cross-sectional views showing a manufacturing process of a low temperature polysilicon thin film transistor according to a preferred embodiment of the present invention. Referring to FIG. 2A, a gate 202, a gate dielectric layer 204, a first amorphous silicon layer 206, and a patterned insulating layer 208 are sequentially formed on the substrate 200. The patterned insulating layer 208 is disposed on the first amorphous silicon layer 206 and above the gate 202. In this embodiment, the material of the patterned insulating layer 208 is, for example, silicon oxide or silicon nitride.

Referring to FIG. 2B, a doping process is performed by patterning the insulating layer 208 as a mask, for example, performing an ion implantation process to dope the dopant ions 230 into a portion of the first non-patterned insulating layer 208. Within the crystalline silicon layer 206, the impedance within the first amorphous silicon layer 206 is reduced to facilitate the ohmic contact layer of the transistor in subsequent processes. Among them, 230 cases of ions If it is an n-type or p-type dopant ion, those skilled in the art can choose an n-type transistor or a p-type transistor according to the actual process.

Referring to FIG. 2C, a second amorphous silicon layer 210 is formed on the first amorphous silicon layer 206 to cover the patterned insulating layer 208. The second amorphous silicon layer 210 is, for example, an amorphous silicon layer having a dopant. The method for forming the second amorphous silicon layer 210 having a dopant is, for example, in a deposition process of the second amorphous silicon layer 210 (for example, a plasma gain chemical vapor deposition process), and simultaneously performing a doping process, that is, a so-called doping process. In-situ doping method.

Referring to FIG. 2D, the first amorphous silicon layer 206 and the second amorphous silicon layer 210 are patterned to form a first patterned amorphous silicon layer 206a and a second patterned amorphous silicon layer 210a to expose portions. The gate dielectric layer 204 is adapted to define the active region of the transistor. It should be noted that the second patterned amorphous silicon layer 210a simultaneously exposes a portion of the patterned insulating layer above the gate 202.

208. The method of patterning the first amorphous silicon layer 206 and the second amorphous silicon layer 210 is, for example, a lithography/etching process.

Referring to FIG. 2E, a laser annealing process is then performed, and the laser annealing process used in the embodiment is, for example, an excimer laser annealing process. The structure formed in Fig. 2D is irradiated with an excimer laser beam 222 such that a portion of the first patterned amorphous silicon layer 206a is melted and then recrystallized to form a polysilicon channel region 212, as shown in Fig. 2F.

In particular, the second patterned amorphous silicon layer 210a can be considered as an energy-absorbing mask in a laser annealing process. Referring to FIG. 2D to FIG. 2E, since the second patterned amorphous silicon layer 210a can absorb the thermal energy of the excimer laser beam 222 to form the ohmic contact layer 214 of the silicon atom partially or completely in a crystalline state, the excimer laser beam 222 The energy in the second patterned amorphous silicon layer 210a is gradually attenuated and cannot be transferred to a portion of the first patterned amorphous silicon layer 206a below it. Meanwhile, since the patterned insulating layer 208 does not absorb the thermal energy of the excimer laser beam 222, a portion of the first patterned amorphous silicon layer 206a under the patterned insulating layer 208 will absorb the thermal energy of the excimer laser beam 222 to form polysilicon. Channel area 212. In addition, a portion of the first patterned amorphous silicon layer 206a under the patterned insulating layer 208 does not have a dopant, so the portion below the overlap between the second patterned amorphous silicon layer 210a and the patterned insulating layer 208 An amorphous silicon thermal carrier suppression region 216 having no dopants is naturally formed in the first patterned amorphous silicon layer 206a. It can be seen from the above that the present invention can accurately determine the growth regions of polycrystalline silicon and amorphous silicon. And because the impedance of the amorphous silicon to electron migration is high, the amorphous silicon hot carrier suppression region 216 can effectively reduce the leakage current in the transistor. In other words, the electric field here is suppressed by the amorphous silicon, so that the carrier is not easily emitted from the source/drain of the transistor to become a leak current.

Moreover, the excimer laser annealing process performed at this time can not only recrystallize part of the amorphous silicon but also recrystallize it into polycrystalline silicon, and simultaneously repair the lattice damaged in the doping process to rearrange it. Reduce the lattice defects in it. It can be seen from this that this embodiment can save an activation process for repairing a crystal lattice.

Referring to FIG. 2G, a source/drain layer 218 is formed on the ohmic contact layer 214 and the dummy dielectric layer 204, and the material thereof is made of, for example, metal or other conductive material. It should be noted that when the present invention is applied to the process of the display device, since the source/drain layer 218 of the thin film transistor is to be connected to the data wiring (not shown) in the display device, the source can be formed. / Drain layer 218 simultaneously performs a data wiring process to reduce the process steps.

The fabrication of the low temperature polysilicon thin film transistor is substantially completed in FIG. 2G, but in general, the protective layer 220 is further formed to cover the source/drain layer 218 and the patterned insulating layer after the source/drain layer 218 is formed. Layer 208, as shown in Figure 2H, protects the internal components of the low temperature polysilicon thin film transistor 400 from damage during processing.

In addition, in another embodiment of the present invention, the source/drain layer 218 may be formed first, and then the laser annealing process is performed. The second embodiment will be described below. Second embodiment 3A to 3C are schematic cross-sectional views showing a process of manufacturing a low temperature polysilicon thin film transistor according to another embodiment of the present invention. Referring to FIG. 3A, after the first patterned amorphous silicon layer 206a and the second patterned amorphous silicon layer 210a are completed according to the description of the flow of FIG. 2A to FIG. 2D, then the substrate 200 and the second patterned non- A source/drain layer 218 is formed on the crystalline silicon layer 210a. Here, the second patterned amorphous silicon layer 210a is an ohmic contact layer as a thin film transistor.

Referring to FIG. 3B, the structure completed in FIG. 3A is irradiated with, for example, an excimer laser beam 222, so that a portion of the first patterned amorphous silicon layer 206a located above the gate 202 is melted and then recrystallized to form a polysilicon channel region. 212, as shown in Figure 3C. At this time, since the thermal conductivity of the source/drain layer is good, the second patterned amorphous silicon layer 210a and the first patterned amorphous silicon layer 206a located underneath cannot absorb the thermal energy of the excimer laser beam 222. . Therefore, the undoped first patterned amorphous silicon layer 206a on both sides of the polysilicon channel region 212 will naturally form an amorphous silicon thermal carrier suppression region 216. A protective layer (not shown) is then formed on the source/drain layer 218, depending on the actual situation, whether or not the process of Figure 2H is desired.

In addition, the present invention can also adjust the timing of the complicated process according to the actual process requirements. The embodiments will be described in detail below, and the components of the drawings in the following embodiments are the same as those of the above-described embodiments, and the materials are the same as or similar to those in the above embodiments. No longer. Third embodiment

4A to 4B are cross-sectional views showing a process of manufacturing a low temperature polysilicon thin film transistor according to still another embodiment of the present invention. Referring to FIG. 4A, after the patterned insulating layer 208 is formed on the substrate 200 according to the flow of FIG. 2A, a second amorphous silicon layer 310 is formed on the first amorphous silicon layer 206 to cover the patterned insulating layer 208. . The second amorphous silicon layer 310 may be an amorphous silicon layer with or without dopants. Referring to FIG. 4B, the first patterned amorphous silicon layer 206a and the second patterned amorphous silicon layer 310a are formed as described in the description of FIG. 2D. Then, a doping process is performed with the patterned insulating layer 208 as a mask to dope the dopant ions 230 into a portion of the first patterned amorphous silicon layer 206a and the second patterned amorphous silicon layer 310a. The subsequent process is as described in the foregoing two embodiments.

Further, in another embodiment of the present invention, the laser annealing process may be performed before the doping process illustrated in Fig. 4B of the third embodiment, and the fourth embodiment will be described below. Fourth embodiment

Referring to FIG. 5A, after the structure shown in FIG. 4A is completed, an excimer laser annealing process is performed, for example, with an excimer laser beam 222, so that a portion of the first patterned amorphous silicon layer 206a is melted and then recrystallized to form a pattern. The polysilicon channel region 212 is depicted by 5B. Here, as in the first embodiment, the second patterned amorphous silicon layer 310a also absorbs the thermal energy of the excimer laser beam 222 in the laser annealing process to form the patterned polysilicon layer 311 (as shown in FIG. 5B).

Referring to FIG. 5B, a doping process is then performed to dope the cerium ions 230 into the patterned polysilicon layer 311 and a portion of the first patterned amorphous silicon layer 206a that is not covered by the patterned insulating layer 208. The ohmic contact layer 214, and naturally forms an undoped amorphous silicon thermal carrier suppression region 216 on either side of the polysilicon channel region 212, as shown in Figure 2F.

It should be noted that since the doping process is performed after the laser annealing process in this embodiment, after the doping process, an annealing activation process (not shown) must be performed to repair the ohmic contact layer 214 and below. A portion of the first patterned amorphous silicon layer 206a has a lattice defect. After the annealing activation process is completed, the remaining subsequent processes are as described in the foregoing embodiments.

It is particularly noteworthy that the energy of the laser beam used in the process of the present invention is dominated by the ability to form a polysilicon channel region. Under this premise, the laser beam used in the present invention is, for example, insufficient to penetrate the second patterned amorphous silicon layer, and even, for example, can only make the second patterned non- The silicon atoms in the crystalline silicon layer near the surface are melted and then recrystallized into polycrystalline silicon. Therefore, the ohmic contact layer of the present invention may have a silicon atom in an amorphous state, or may have a silicon atom in a crystalline state, which may depend on actual process parameters.

The present invention provides a variety of different fabrication processes for producing the low temperature polysilicon thin film transistor of Figure 2H. Therefore, those skilled in the art can choose one of these processes according to the actual process requirements. The structure of the low temperature polysilicon thin film transistor 400 shown in Fig. 2H will be described in detail below, and the method of forming each element has been described in the above embodiment, and will not be described below.

Referring to FIG. 2H, the low temperature polysilicon thin film transistor 400 is mainly composed of a substrate 200 and a structure disposed on the substrate 200. The structure includes a gate 202, a gate dielectric layer 204, a patterned insulating layer 208, a patterned silicon layer 402, an ohmic contact layer 214, a source/drain layer 218, and a protective layer 220. The gate 202 and the gate dielectric layer 204 are sequentially disposed on the substrate 200, the patterned silicon layer 402 is disposed on the gate dielectric layer 204, and in particular, the patterned silicon layer 402 is disposed above the gate 202. The polysilicon channel region 212 and the amorphous silicon thermal carrier suppression region 216 on either side of the polysilicon channel region 212. The patterned insulating layer 208 is disposed on the patterned silicon layer 402, and the material thereof is, for example, silicon oxide or silicon nitride.

The ohmic contact layer 214 is disposed on a portion of the gate dielectric layer 204 and the partially patterned insulating layer 208 over the amorphous silicon thermal carrier suppression region 216, exposing a portion of the patterned insulating layer 208 over the polysilicon channel region 212, and It is connected to the amorphous silicon thermal carrier suppression zone 216. The ohmic contact layer 214 is, for example, an n-type polysilicon doped ohmic contact layer or a p-type polysilicon doped ohmic contact layer. In other words, the low temperature polysilicon thin film transistor 400 is, for example, an n-type transistor or a p-type transistor.

The source/drain layer 218 is disposed on the ohmic contact layer 214 and the gate dielectric layer 204, and the protective layer 220 is disposed on the source/drain layer 218 and the patterned insulating layer 208 for protecting the low temperature polysilicon thin film transistor. 400 internal components to avoid damage in subsequent processes.

In summary, the present invention has the following advantages: 1. Compared with the existing low temperature polysilicon thin film transistor process, one LDD process and mask can be saved to save manufacturing cost.

2. In the process of the low temperature polysilicon thin film transistor of the present invention, the second patterned amorphous silicon layer is used as an absorption mask in the laser annealing process, thereby effectively controlling the growth region of polysilicon and amorphous silicon.

3. The amorphous silicon hot carrier suppression region allows the grains to grow from the sides of the polysilicon channel region to the center, thereby allowing the grains in the polysilicon channel region to have better dimensional uniformity.

4. At the same time, it has the high driving current (I _0N ) of the polysilicon thin film transistor and the low leakage current (I _OTF ) of the amorphous silicon thin film transistor, so it has a high ION/IOFF ratio to improve the low temperature polysilicon thin film transistor. Electrical characteristics.

5. The conversion of the old amorphous silicon production line to the production of the bottom gate polysilicon is highly feasible and can save costs.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection shall be subject to the contents as defined in the appended claims. Description of the reference numerals

100, 200: substrate

102, 202: Gate

104, 204: gate dielectric layer

106: amorphous silicon layer

106, 311: patterned polysilicon layer

108: silicon oxide layer

110, 214: ohmic contact layer 112: channel layer

114: shallow miscellaneous drain

116, 218: source/drain layer

118, 222: Excimer laser beam

120, 400: low temperature polysilicon thin film transistor

130, 140, 230: ion

206: first amorphous silicon layer

206a: first patterned amorphous silicon layer

208: patterned insulation

210, 310: second amorphous silicon layer

210a> 310a: second patterned amorphous silicon layer

212: polysilicon channel area

216: Amorphous silicon hot carrier suppression zone

220: Protective layer

402: patterned silicon layer

Claims

Rights request

A low temperature polysilicon thin film transistor adapted to be disposed on a substrate, wherein the low temperature polysilicon thin film transistor comprises:

a gate disposed on the substrate;

a gate dielectric layer disposed on the substrate and the gate;

a patterned silicon layer disposed on the dummy dielectric layer and located above the sky electrode, wherein the patterned silicon layer includes a polysilicon channel region and amorphous silicon heat on one of the two sides of the polysilicon channel region Carrier suppression zone;

a patterned insulating layer disposed on the silicon layer;

An ohmic contact layer disposed on a portion of the gate dielectric layer and a portion of the patterned insulating layer above the amorphous silicon thermal carrier suppression region to expose a portion of the patterned insulating layer over the polysilicon channel region and connected The amorphous silicon hot carrier suppression zone;

A source/drain layer disposed on the ohmic contact layer.

The low temperature polysilicon thin film transistor according to claim 1, further comprising a protective layer disposed on the source/drain layer and covering the insulating layer.

The low temperature polysilicon thin film transistor according to claim 1, wherein the ohmic contact layer comprises one of an n-type doped ohmic contact layer and a p-type doped ohmic contact layer.

The low temperature polysilicon thin film transistor according to claim 1, wherein the insulating layer is made of one of silicon oxide and silicon nitride.

A method of fabricating a low temperature polysilicon thin film transistor, comprising: forming a gate on a substrate;

Forming a gate dielectric layer on the substrate and the interpole;

Forming a first amorphous silicon layer, a patterned insulating layer, and a layer on the gate dielectric layer a second amorphous silicon layer, wherein the patterned insulating layer is disposed on a portion of the first amorphous silicon layer and above the gate, and the second amorphous silicon layer is disposed on the first amorphous silicon layer and The patterned insulating layer;

Patterning the first amorphous silicon layer and the second amorphous silicon layer to form a first patterned amorphous silicon layer and a second patterned amorphous silicon layer to expose a portion of the gate dielectric layer, Wherein the second patterned amorphous silicon layer exposes a portion of the patterned insulating layer;

And partially recrystallizing a portion of the first patterned amorphous silicon layer to form a polysilicon channel region over the gate, wherein the second patterned amorphous silicon layer overlaps the patterned insulating layer An amorphous silicon hot carrier suppression region is naturally formed in a portion of the first patterned amorphous silicon layer;

A source/drain layer is formed on the second patterned amorphous silicon layer.

6. The method of fabricating a low temperature polysilicon thin film transistor according to claim 5, wherein the step of forming the polysilicon channel region comprises performing a laser annealing process.

7. The method of fabricating a low temperature polysilicon thin film transistor according to claim 6, wherein the laser annealing process comprises an excimer laser annealing process.

The method of manufacturing a low temperature polysilicon thin film transistor according to claim 5, further comprising: after forming the patterned insulating layer and before forming the second amorphous silicon layer, further comprising a portion of the first amorphous The silicon layer is miserable.

The method of manufacturing a low temperature polysilicon thin film transistor according to claim 5, further comprising: after forming the second amorphous silicon layer and before forming the source/drain layer The amorphous silicon layer and the second amorphous silicon layer are doped.

The method of manufacturing a low temperature polysilicon thin film transistor according to claim 9, further comprising: after forming the polysilicon channel region and before forming the source/drain layer, a portion of the first amorphous silicon The layer and the second patterned amorphous silicon layer are doped.

11. The method of fabricating a low temperature polysilicon thin film transistor according to claim 10, wherein The method further includes: after doping the portion of the first amorphous silicon layer and the second patterned amorphous silicon layer, and before forming the source/drain layer, further comprising a portion of the first amorphous silicon The layer and the second patterned amorphous silicon layer are subjected to an annealing activation process.

The method of fabricating a low temperature polysilicon thin film transistor according to claim 5, further comprising forming a protective layer on the source/drain layer and covering the insulating layer.

The method of manufacturing a low-temperature polysilicon thin film transistor according to claim 5, wherein when the polysilicon channel region is formed, the second patterned amorphous silicon layer is simultaneously melted and then recrystallized.

Forming a gate dielectric layer on the substrate and the gate;

Forming a first amorphous silicon layer, a patterned insulating layer, and a second amorphous silicon layer, wherein the patterned insulating layer is disposed on a portion of the first amorphous silicon layer and above the gate The second amorphous silicon layer is disposed on the first amorphous silicon layer and the patterned insulating layer;

Forming a source/drain layer on the second patterned amorphous silicon layer;

And partially re-crystallizing a portion of the first patterned amorphous silicon layer to form a polysilicon channel region over the drain electrode, wherein the second patterned amorphous silicon layer overlaps the patterned insulating layer A portion of the first patterned amorphous silicon layer naturally forms an amorphous silicon thermal carrier suppression region.

A method of fabricating a low temperature polysilicon thin film transistor according to claim 14, wherein the step of forming the polysilicon channel region comprises performing a laser annealing process.

16. The method of fabricating a low temperature polysilicon thin film transistor according to claim 15, wherein The laser annealing process includes an excimer laser annealing process.

The method of manufacturing a low temperature polysilicon thin film transistor according to claim 14, further comprising: after forming the patterned insulating layer and before forming the second amorphous silicon layer, further comprising a portion of the first amorphous silicon The layers are doped.

18. The method of fabricating a low temperature polysilicon thin film transistor according to claim 14, further comprising: after forming the second amorphous silicon layer and before forming the source/drain layer, further comprising a portion of the first non- The crystalline silicon layer and the second amorphous silicon layer are doped.

The method of manufacturing a low temperature polysilicon thin film transistor according to claim 18, further comprising: after doping a portion of the first amorphous silicon layer and the second amorphous silicon layer The first amorphous silicon layer and the second amorphous silicon layer are subjected to an activation process.