WO2005122180A1

WO2005122180A1 - Method for inspecting semiconductor memory

Info

Publication number: WO2005122180A1
Application number: PCT/JP2004/007962
Authority: WO
Inventors: Yukinobu Hikosaka; Tomohiro Takamatsu; Yoshinori Obata
Original assignee: Fujitsu Limited
Priority date: 2004-06-08
Filing date: 2004-06-08
Publication date: 2005-12-22
Also published as: CN1957424A; US20070058416A1; US7982466B2; JPWO2005122180A1; CN100592426C; JP4387407B2

Abstract

A method for inspecting a semiconductor memory having a nonvolatile memory employing a ferroelectric capacitor is disclosed which comprises the following steps (a)-(c) after leaving the ferroelectric capacitor in a first polarized state: step (a) for writing a second polarized state reverse to the first polarized state; step (b) for leaving the ferroelectric capacitor in the second polarized state; and step (c) for reading the second polarized state. The temperature or the voltage in the step (a) is lower than the temperature or the voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.

Description

Specification

Inspection method for semiconductor memory device

Technical field

The present invention relates to a method for testing a semiconductor memory device, and more particularly to a method for testing a semiconductor memory device using a ferroelectric substance.

Background art

[0002] In recent years, with the spread of portable devices, the demand for energy saving, the demand for waste reduction, and the like, the demand for non-volatile storage devices that can retain stored contents even when the power is turned off has been increasing. Semiconductor memory devices (FeRAMs) using strong dielectric capacitors are non-volatile memory devices that operate at a low voltage and can be rewritten many times, and are widely used in integrated circuit devices mixed with logic circuits. It has become.

FIG. 6A is a sectional view schematically showing a configuration of a ferroelectric capacitor. A ferroelectric layer 105 is sandwiched between the lower electrode 101 and the upper electrode 102 to form a ferroelectric capacitor. The lower electrode is connected to, for example, a plate line PL, and the upper electrode is connected to a bit line BL via, for example, a switching transistor.

When a positive pulse voltage is applied to the lower electrode 101 relative to the upper electrode 102, the first upward polarization state S 1 remains in the ferroelectric layer 105. When a pulse voltage of the opposite polarity is applied, a downward second polarization state S2 remains in the ferroelectric layer 105.

FIG. 6B is a graph showing a hysteresis characteristic of the ferroelectric layer capacitor. The horizontal axis is the voltage applied to the lower electrode 101 with respect to the upper electrode. The vertical axis indicates the polarization P (charge) of the ferroelectric layer. When the applied voltage is run, the state changes with hysteresis as shown by the arrow. The voltage at the point where the hysteresis curve crosses the voltage axis is the coercive voltage Vc. This will be described in more detail below. Now, it is assumed that the ferroelectric layer is in the state of polarization S1 and a positive pulse Vp is applied to the lower electrode 101.

[0006] As shown in Fig. 6C, as the voltage of the lower electrode increases, the state of the ferroelectric layer changes as indicated by an arrow, the upward polarization decreases, and as the voltage further increases, the downward polarization decreases. Increase. State T1 at peak voltage VI. During this time, positive charges flow into the lower electrode Then, a positive charge P is emitted from the upper electrode 102 to the bit line BL. As the applied voltage drops, the ferroelectric layer changes from state T1 to state S2. With this change, a negative charge Pa is released from the upper electrode 102 to the bit line BL.

FIG. 6D shows a state change when a positive pulse Vp is applied to the lower electrode of the ferroelectric capacitor in the polarization state S2. With the rise of the noise voltage, the state of the ferroelectric capacitor changes from S2 to T1, and the amount of positive charge U is released from the upper electrode 102 to the bit line BL. When the pulse voltage falls, the state of the ferroelectric capacitor changes from T1 to S2, and the amount of negative charge Ua is released from the upper electrode 102 to the bit line BL.

FIG. 6E shows a state change when a negative polarity pulse Vn is applied to the lower electrode of the ferroelectric capacitor in the polarization state S2. With the rise of the negative pulse voltage Vn, the state of the strong dielectric capacitor changes from S2 to T2, and the upper electrode 102 emits a negative charge N to the bit line BL. With the fall of the negative pulse voltage Vn, the state of the ferroelectric capacitor changes from T2 to S1, and the upper electrode 102 emits the positive charge Na to the bit line BL.

FIG. 6F shows a state change when a negative pulse Vn is applied to the lower electrode of the ferroelectric capacitor in the polarization state S1. With the rise of the negative pulse voltage, the state of the ferroelectric capacitor changes from S1 to T2, and the amount of negative charges D is released from the upper electrode 102 to the bit line BL. When the negative pulse voltage falls, the state of the ferroelectric capacitor changes from T2 to S1, and the positive charge Da is released from the upper electrode 102 to the bit line BL.

As shown in FIG. 7A, a ferroelectric capacitor shows a phenomenon called imprint. In the figure, the horizontal axis and the vertical axis show the voltage and polarization of the lower electrode as in FIG. 6B. If the polarization state S1 is maintained, the hysteresis characteristic tends to change from H0 to HI. If the opposite polarization state S2 is maintained, the hysteresis characteristic changes from H0 to H2, which is the opposite direction to HI.

As shown in Fig. 7B, when the polarization state S1 is maintained and the hysteresis characteristic is imprinted from H0 to HI, when writing S2 of the opposite polarity, the amount of polarization stored decreases by Δ 量 1 Resulting in.

[0011] As shown in FIG. 7C, when the polarization state S2 is maintained and the hysteresis characteristic is imprinted from H0 to H2, when the opposite polarity S1 is written thereafter, the amount of polarization accumulated is polarized. The amount Δ Ρ2 decreases. If the amount of polarization decreases and the data cannot be read, the function of the storage device is lost.

FIG. 8A shows an example of a memory cell configuration of a 2-transistor, 2-capacitor (2T / 2C) FeRAM. One FeRAM memory cell includes two ferroelectric capacitors Cx, Cy and switching transistors Tx, Ty each having a drain electrode connected to an upper electrode of each ferroelectric capacitor. The source electrodes of the two switching transistors Tx and Ty are connected to the bit lines BL and / BL, the gate electrodes are commonly connected to the word line WL, and the lower electrodes of the ferroelectric capacitors Cx and Cy are commonly connected to the plate line PL. Connected to. The sense amplifier SA is connected between the bit lines BL and / BL.

[0013] The ferroelectric capacitors Cx and Cy store information of opposite polarities. For example, when "1" is stored, information "1" is stored in the ferroelectric capacitor Cx, and "0" is stored in the ferroelectric capacitor Cy. At the time of reading, the voltage difference between the bit line BL and the bit line ZBL is detected by the sense amplifier SA.

[0014] A 1T / 1C configuration in which one transistor and one capacitor constitute one memory cell is also used. In this case, for example, a combination of the right transistor and the ferroelectric capacitor is used, and a reference cell is used instead of the combination of the left transistor and the ferroelectric capacitor. Although the amount of charge that can be distinguished is reduced by half, but there is no essential difference, the following description will be made using 2T / 2C as an example.

FIG. 8B shows an inspection procedure of the FeRAM. FIG. 8C is a diagram showing a pulse voltage applied to two ferroelectric capacitors Cx and Cy included in one FeRAM and a charge output emitted to a bit line according to the procedure of FIG. 8B. Note that the pulse voltage is indicated by a voltage with respect to the lower electrode when the upper electrode is set to the reference voltage.

First, in step ST100, first data is written. After that, reading of the same data, writing and reading of the second data of the opposite polarity are performed, so that the first data is called the same state (SS) and the second data is called the opposite polarity state (OS).

[0017] As shown on the left side of FIG. 8C, first, a positive pulse voltage Vp is applied to the capacitors Cx and Cy to align both capacitors to the polarization state of "0". Subsequently, a positive polarity voltage is applied to the capacitor Cx, and a negative polarity pulse voltage is applied to the capacitor Cy. Write "0" to the capacitor Cy. First data (SS) is stored.

In the next step ST110, both capacitors in which the first data (SS) has been written are left in a heated state, for example, at 150 ° C. for a long time, for example, for 10 hours. The deterioration of the stored information is accelerated in the heating state. A hysteresis shift due to imprinting may occur. After that, the first data (SS) is read in step ST120.

As shown on the left side of the center of FIG. 8C, a positive pulse voltage is applied to both capacitors.

At the rise of the pulse voltage, a positive charge U corresponding to "0" is released from the capacitor Cx and a positive charge P corresponding to "1" is released from the capacitor Cy to each bit line, and the first data stored by the difference is stored. Read (SS). Since information stored by reading is lost, "0" is written again to the capacitor Cx and "1" is written to the capacitor Cy based on the read information. If the polarization is demagnetized, the first data may not be able to be read. Retention characteristics can be detected by reading the first data (SS).

[0020] In step ST130, second data (OS) having the opposite polarity is written. As shown on the right side of the center of Fig. 8C, a positive pulse voltage Vp is applied to both capacitors to align both capacitors to a polarization state of "0", and then a negative pulse voltage Vn is applied to capacitor Cx. Write '1' and apply a positive polarity pulse voltage Vp to the capacitor Cy to write '0'. When imprinting occurs, the stored polarization is reduced. .

[0021] In step ST140, the written second data is once left, for example, for 5 seconds. It has a function to stabilize relaxation and temperature, and to prevent the evaluation of imprint from becoming too sweet.

[0022] In the next step ST150, the second data (OS) is read. As shown on the right side of FIG. 8C, a positive pulse voltage Vp is applied to both capacitors. At the rise of the noise voltage, a positive charge P corresponding to “” is released from the capacitor Cx and a positive charge U corresponding to “0” is released to each bit line from the capacitor Cy, and the second data ( 〇S) is read, and the stored information is lost, so “1” is written again to the capacitor Cx and “0” to the capacitor Cy based on the read information.

If the amount of polarization is reduced by imprinting the first data, the second data may not be read out. By reading the second data (ΔS), the imprint characteristics can be detected. Rye When the evaluation is performed, the process returns from step ST150 to step ST100, and the same detection steps are repeated.

In an actual FeRAM inspection, a device inspection for determining the presence or absence of a defect in all the memory cells and a monitor inspection for measuring the amount of charge read from the selected memory cells are performed.

FIG. 9A is a table collectively showing the conditions of the device inspection and the monitor inspection. The voltage, temperature, and time for device inspection and monitor inspection are shown for each step. All device inspection voltages are performed at the minimum voltage in the operating voltage region. This is to make the conditions strict and make a strict judgment. The temperature is 150 ° C in the thermal storage step ST110, and the other steps are high temperature. The standing time is 10 hours for the thermal standing step ST110 and 5 seconds for the step ST140. The monitor detection voltage is the center voltage of the operating voltage region. The temperature is 150 ° C. in the thermal standing step ST110 and room temperature in the other steps. The standing time is 10 hours for the heat standing step ST110 and 30 seconds for the step ST140. In each of the device inspection and the monitor inspection, the voltage and temperature in the data writing and reading processes are constant.

The configuration and manufacturing method of FeRAM are disclosed in US Pat. No. 5,953, 618, which is incorporated herein by reference, for example. An inspection method of FeRAM is disclosed in USP 6,008,659, which is incorporated herein by reference, for example.

[0027] A particular problem in FeRAM is imprint inspection. Japanese Patent Application Laid-Open No. 2001-67896 proposes measuring the operating voltage of data of opposite polarity before and after high-temperature storage, and inspecting imprint occurrence from the difference. Japanese Patent Application Laid-Open No. 2002-8397 discloses that after the first data is written at the maximum operating voltage (in this embodiment, the number of times the predetermined imprint occurs), the imprint is generated, and then the second data having the opposite polarity is written. It is proposed to write, leave, and read the data to perform the inspection reflecting the imprint.

Disclosure of the invention

An object of the present invention is to provide a method for inspecting a semiconductor memory device, which can evaluate imprint characteristics in a short time.

According to one aspect of the present invention, there is provided a ferroelectric capacitor of a semiconductor memory device having a nonvolatile memory using a ferroelectric capacitor. (a) writing a first polarization state at a first write voltage,

(b) thermally leaving the first polarization state;

(c) reading the first polarization state at a first read voltage;

(d) after the step (c), writing a second polarization state opposite to the first polarization state;

(e) leaving the second polarization state;

(f) reading the second polarization state at a second read voltage;

At least one of the voltage and temperature for writing and reading differs depending on the process, and the retention performance is inspected in the steps (a), (b) and (c), and the subsequent steps (d), (e) and ( In step f), there is provided a semiconductor memory device inspection method for inspecting imprint performance.

According to another aspect of the present invention, after the ferroelectric capacitor of the semiconductor memory device having the nonvolatile memory using the ferroelectric capacitor is left in the first polarization state,

(a) writing a second polarization state opposite to the first polarization state,

(b) leaving the second polarization state;

(c) reading the second polarization state;

Wherein the temperature or voltage of the step (a) is different from the temperature or voltage of the step (c).

[0030] Imprint characteristics can be evaluated in a short period of time by impressing and accelerating the imprint.

Brief Description of Drawings

FIG. 1 is a flowchart showing a flow of a method for detecting a semiconductor memory device having a ferroelectric capacitor.

[FIG. 2] FIGS. 2A-2D are tables and graphs explaining experiments in which the temperature for writing and reading OS was changed.

[FIG. 3] FIGS. 3A to 3C are a table and a graph explaining an experiment in a case where the storage time after OS writing is set to a high temperature and the storage time is changed.

[FIG. 4] FIGS. 4A to 4C are a table and a graph illustrating an experiment when the OS write voltage is changed. FIG. 5A to FIG. 5C are a table and a graph for explaining an experiment when the SS write voltage is changed.

6A to 6F are a cross-sectional view and a graph illustrating a ferroelectric capacitor.

FIG. 7A to FIG. 7C are graphs for explaining imprinting of a ferroelectric capacitor.

8A to 8C are an equivalent circuit diagram, a flowchart, and a diagram for explaining detection of a ferroelectric capacitor.

FIG. 9A and FIG. 9B are a table showing a method of detecting a ferroelectric capacitor and a graph showing a life measurement result of device detection.

BEST MODE FOR CARRYING OUT THE INVENTION

First, the results of the present inventors' evaluation of the life of the FeRAM device by the conventional inspection method will be described.

FIG. 9B is a graph showing the result of performing the life evaluation of the defective bit by repeatedly performing the inspection flow shown in FIG. 8B. The horizontal axis indicates the integration time, and the vertical axis indicates the number of defective bits of the retention characteristic (SS) and the imprint characteristic (OS). The SS bad bit is good with no bit out in a 504 hour life evaluation. The number of OS failure bits was one bit in a short time, and started to increase from over 100 hours, reaching 5 bits in 504 hours. Since the number of defective bits is extremely small, it has been more than 500 hours to detect the occurrence of imprint. If imprinting is found to occur, it will mainly improve the ferroelectric layer fabrication process. If detection takes more than 500 hours, feedback is slow and development time is prolonged and development costs rise.

FIG. 1 is a flowchart showing a flow of a method for detecting a semiconductor memory device having a ferroelectric capacitor. Basically includes SS writing step ST100, heat leaving step ST110, SS reading step ST120, OS writing step ST130, ΔS leaving step ST140, OS reading step ST150 similar to the detection method shown in FIG. 8B. By changing the voltage and temperature of force data writing and data reading, an attempt was made to make the imprint look larger or to accelerate it.

FIG. 2 is a table and a graph illustrating an experiment in which the temperature of writing and reading of the OS was changed. Figure 2A is a table that summarizes the experimental conditions. As shown in the top row, Steps ST100, OS writing step ST130, OS leaving step ST140, and OS reading step ST150 will be described. SS writing step ST100 was performed at room temperature (approximately 25 ° C) at 3.6 V instead of the conventional minimum voltage and high temperature. It was expected that writing at high voltage would add more habit to the ferroelectric. The heat leaving step ST110 and the SS reading step ST120 were performed in the same manner as in the past.

[0039] OS writing step ST130 is 2.7V and the temperature is -45. C, _5 ° C, run at 25 ° C, leaving step ST140 as long as 15 minutes, perform at high temperature of 85 ° C, and ΔS reading step ST150 reduce the temperature by 2.7V Performed at ° C and 85 ° C. The combination of write temperature and read temperature is (_45 ° C, _45.C), (-45 ° C, 85.C), (-5 ° C, 85.C), (25.C, 85 ° C) There are four types. -45 ° C is the minimum operating temperature, 85 ° C is the maximum operating temperature.

FIG. 2C shows a change in hysteresis expected when the ferroelectric is cooled to a low temperature. At low temperatures, the hysteresis changes from the dashed line to the solid line, and expands in the horizontal direction (voltage direction). The high voltage Vc will be high and writing will be difficult.

FIG. 2D shows a change in hysteresis expected when the ferroelectric is heated to a high temperature. When the temperature is increased, the hysteresis changes from the broken line to the solid line, and the vertical direction (polarization direction) decreases. A decrease in polarization (demagnetization) will make reading difficult.

FIG. 2B shows the experimental results. When writing and reading were performed at 45 ° C, the number of defective bits was 0. It can be considered that writing and reading can be performed normally even at the minimum operating temperature. However, when the force reading temperature was changed to 85 ° C, the number of defective bits increased to 1471. The imprint should have looked big. When the writing temperature was raised to 5 ° C, the number of defective bits became 0. Even when the writing temperature was raised to 25 ° C (room temperature), the number of defective bits was 0.

When the forces S and ΔS, for which the detailed reason is unknown, are written at a low temperature and read at a high temperature, it is considered that the imprint can be emphasized and detected. Although the results of the defect determination in the device inspection have been described, if the monitor inspection is performed and the charge amount is detected, the influence of the temperature difference between the writing temperature and the reading temperature will be clearer. From these results alone, the imprint does not look large at a temperature difference of 90 ° C, and the imprint looks remarkably large at a temperature difference of 130 ° C. A temperature difference of 100 ° C or more would be preferred. Performing steps ST130 and ST150 in FIG. 1 at a low temperature and a high temperature, respectively, expects such an imprint enhancement effect.

Figure 3 is a table and a graph that describe an experiment in which the temperature after leaving the OS was elevated and the duration was varied. Figure 3A is a table that summarizes the experimental conditions. The SS writing step ST100 was performed at a voltage of 3.7 V and at room temperature (about 25 ° C). 〇S writing step ST130 was performed at 2.6 V and room temperature, and then, leaving step ST140 was performed at 0, 1, 10, 20, 60 (min) and 90 ° C. OS reading step ST150 was performed at 2.6 V and room temperature.

FIG. 3B is a graph showing ΔS standing time dependency. The horizontal axis shows the integrated value of the SS heat storage time, and the vertical axis shows the difference between the charge amount P from the capacitor Cx and the charge amount U from the capacitor Cy when reading the OS.測定 The measurement results are plotted for each of the samples with S standing times of 0, 1, 10, 20, and 60 (minutes). Under all conditions, the OS charge decreases as the thermal storage time increases. It is considered that the decrease in the OS charge indicates that the imprint is progressing.

[0046] FIG. 3C shows the percentage (OS rate) of how much the amount of OS charge decreased when the heat exposure time was 1000 hours with respect to the OS charge amount when the heat exposure time was 24 hours. It is the graph shown. Shows the OS rate for each OS idle time. Since the steps ST100 and ST110 where the imprint is considered to occur in each sample are the same, it is considered that the larger the absolute value of the OS rate, the stronger the influence of the imprint is. The tendency is that the absolute value of the OS rate tends to increase as the OS leaving time increases, and that the increase tends to saturate when the OS leaving time exceeds 10 minutes.

[0047] It can be seen that the ΔS leaving time should be set to 10 minutes or more to make the imprint appear large.

Although the OS leaving temperature is set to the maximum temperature of 85 ° C., it is preferable to further extend the leaving time when the operating temperature is left lower than 85 ° C. The high temperature of step ST140 in FIG. 1 for more than 10 minutes indicates this.

FIG. 4 is a table and a graph illustrating an experiment when the ΔS write voltage is changed. FIG. 4A is a table summarizing the experimental conditions. The SS writing step ST100 and the ΔS reading step ST150 are the same as those in FIG. 3A. OS write step ST130 write power The pressure was changed to 2.2V, 2.6V, and 3.0V. The temperature is room temperature. In addition, OS standing step ST140 was made sufficiently long, 20 minutes, and the temperature was further increased to 90 ° C.

FIG. 4B is a graph showing OS write voltage dependency. The horizontal axis shows the integrated value of the SS heat storage time, and the vertical axis shows the difference between the charge amount P from the capacitor Cx and the charge amount U from the capacitor Cy when reading the OS. 〇 Measurement results are plotted for each sample of 3.0V, 2.6V, and 2.2V S write voltage. Under all conditions, the OS charge decreased with increasing heat exposure time.減少 The decrease in S charge is considered to indicate that imprinting is progressing.

[0050] FIG. 4C shows the ratio (〇S rate) of how much the amount of OS charge decreased when the heat exposure time was 1000 hours to the amount of OS charge when the heat exposure time was 24 hours. This is the graph indicated by. The Δs rate is shown for each OS write voltage. Since the steps ST100 and ST110 at which imprint is considered to occur at each sample are the same, it is considered that the larger the absolute value of the OS rate, the stronger the influence of imprint is. As the OS write voltage decreases, the absolute value of the OS rate tends to increase. For example, it may be preferable to write the OS at the lowest operating voltage. The low voltage at step ST130 in FIG. 1 indicates this.

FIG. 5 is a table and a graph illustrating an experiment when the SS write voltage is changed. FIG. 5A is a table summarizing the experimental conditions. SS write step The write voltage of ST100 was changed to 4.4V, 3.7V, and 3.0V. The temperature is room temperature. The OS writing step ST130 was performed at a voltage of 2.6 V and at room temperature. That is, the SS write voltage was set higher than the SS read voltage. OS leaving step ST140 and OS reading step ST150 are the same as those in FIG. 4A.

FIG. 5B is a graph showing the SS write voltage dependency. The horizontal axis shows the integrated value of the SS heat storage time, and the vertical axis shows the difference between the charge amount P from the capacitor Cx and the charge amount U from the capacitor Cy when reading the OS. The measurement results are plotted for each of the SS writing voltage samples of 4.4V, 3.7V and 3.OV. Under all conditions, the OS charge decreased with increasing heat exposure time.減少 The decrease in S charge is considered to indicate that imprinting is progressing. [0053] Figure 5C shows the percentage (OS rate) of how much the amount of OS charge decreased when the heat exposure time was 1000 hours compared to the OS charge amount when the heat exposure time was 24 hours. It is the graph shown. OS rate is shown for each SS write voltage. Since OS writing, leaving, and reading are the same conditions, it is considered that imprint occurs more strongly as the absolute value of the ΔS rate is larger. It has been shown that the absolute value of the OS rate tends to increase as the SS write voltage increases. For example, it may be preferable to perform SS writing at the highest operating voltage. The high voltage at step ST100 in FIG. 1 indicates this.

As described above, the present invention has been described with reference to the examples. However, the present invention is not limited to these examples. For example, it will be apparent to those skilled in the art that various modifications, improvements, and combinations are possible.

Claims

The scope of the claims

[1] For a ferroelectric capacitor of a semiconductor memory device having a nonvolatile memory using a ferroelectric capacitor,

(a) writing a first polarization state at a first write voltage,

(b) thermally leaving the first polarization state;

(c) reading the first polarization state at a first read voltage;

(e) leaving the second polarization state;

(f) reading the second polarization state at a second read voltage;

At least one of the voltage and temperature for writing and reading differs depending on the process, and the retention performance is inspected in the steps (a), (b) and (c), and the subsequent steps (d), (e) and ( Inspection method of semiconductor memory device for inspecting imprint performance in f).

[2] The inspection method for a semiconductor memory device according to claim 1, wherein the temperature in the step (d) is lower than the temperature in the step (f).

3. The method for testing a semiconductor memory device according to claim 2, wherein the temperature of the step (d) is lower than the temperature of the step (f) by 100 ° C. or more.

4. The semiconductor memory device inspection method according to claim 1, wherein the second write voltage is lower than the first write voltage.

5. The semiconductor memory device inspection method according to claim 1, wherein the first write voltage is higher than the first read voltage.

6. The method of manufacturing a semiconductor memory device according to claim 1, wherein in the step (e), the second polarization state is left for at least 10 minutes.

[7] After the ferroelectric capacitor of the semiconductor memory device having the nonvolatile memory using the ferroelectric capacitor is left in the first polarization state,

(b) leaving the second polarization state; (c) reading the second polarization state;

A method for inspecting a semiconductor memory device, wherein the temperature or voltage in the step (a) is different from the temperature or voltage in the step (c).

8. The method according to claim 7, wherein the temperature or the voltage in the step (a) is lower than the temperature or the voltage in the step (c).

9. The method of claim 8, wherein the temperature of the step (a) is lower than the temperature of the step (c) by 100 ° C. or more.

[10] The method for inspecting a semiconductor memory device according to claim 7, wherein the first step (b) is left for 10 minutes or more.