KR20070004087A - Method for inspecting semiconductor memory - Google Patents

Abstract

A method for inspecting a semiconductor memory having a nonvolatile memory employing a ferroelectric capacitor is disclosed which comprises the following steps (a)-(c) after leaving the ferroelectric capacitor in a first polarized state: step (a) for writing a second polarized state reverse to the first polarized state; step (b) for leaving the ferroelectric capacitor in the second polarized state; and step (c) for reading the second polarized state. The temperature or the voltage in the step (a) is lower than the temperature or the voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time. ® KIPO & WIPO 2007

Description

Inspection method of semiconductor memory device {METHOD FOR INSPECTING SEMICONDUCTOR MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a semiconductor memory device, and more particularly to a method for inspecting a semiconductor memory device using a ferroelectric.

In recent years, the demand for nonvolatile memory devices capable of retaining the contents of memory even when the power is turned off has increased in response to the spread of portable devices, requests for energy saving, and requests for waste reduction. BACKGROUND OF THE INVENTION A semiconductor memory device (FeRAM) using a ferroelectric capacitor is a nonvolatile memory device capable of low voltage operation and rewriting many times, and is widely used in an integrated circuit device mixed with logic circuits.

FIG. 6A is a cross-sectional view schematically showing the configuration of a ferroelectric capacitor. The ferroelectric layer 105 is sandwiched between the lower electrode 101 and the upper electrode 102 to form a ferroelectric capacitor. The lower electrode is connected to the plate line PL, for example, and the upper electrode is connected to the bit line BL via, for example, a switching transistor.

When a positive pulse voltage is applied to the lower electrode 101 relative to the upper electrode 102, an upward first polarization state S1 remains in the ferroelectric layer 105. When the reverse polarity pulse voltage is applied, the second polarization state S2 of the downward direction remains in the ferroelectric layer 105.

FIG. 6B is a graph showing hysteresis characteristics of the ferroelectric layer capacitor. The horizontal axis is a voltage based on the upper electrode applied to the lower electrode 101. The vertical axis represents polarization P (charge) of the ferroelectric layer. When the applied voltage is scanned, the state changes along hysteresis characteristics (hysteresis) as indicated by the arrow. The voltage at the point where the hysteresis curve intersects the voltage axis is the constant voltage Vc. It demonstrates in more detail below. Now, it is assumed that the ferroelectric layer is in the state of polarization S1 and the positive pulse Vp is applied to the lower electrode 101.

As shown in Fig. 6 (c), at the same time as the voltage of the lower electrode increases, the ferroelectric layer changes state as indicated by the arrow, the upward polarization decreases, and as the voltage increases, the downward polarization increases. Going. The state T1 is reached at the peak voltage V1. During this time, the static charge flows into the lower electrode, and the amount of static charge P is emitted from the upper electrode 102 to the bit line BL. Simultaneously with the drop of the applied voltage, the ferroelectric layer changes from the state T1 to the state S2. Along with this change, the negative charge Pa is emitted from the upper electrode 102 to the bit line BL.

FIG. 6D shows a state change when a positive pulse Vp is applied to the lower electrode of the ferroelectric capacitor in the polarization state S2. At the same time as the pulse voltage rises, the ferroelectric capacitor changes state from S2 to T1, and the amount of static charge U is emitted from the upper electrode 102 to the bit line BL. When the pulse voltage falls, the ferroelectric capacitor changes state from T1 to S2, and the negative charge amount Ua is emitted from the upper electrode 102 to the bit line BL.

FIG. 6E shows the state change when the negative pulse Vn is applied to the lower electrode of the ferroelectric capacitor in the polarized state S2. Simultaneously with the rise of the negative pulse voltage Vn, the ferroelectric capacitor changes state from S2 to T2, and the upper electrode 102 emits a negative charge amount N to the bit line BL. Simultaneously with the falling of the negative pulse voltage Vn, the ferroelectric capacitor changes state from T2 to S1, and the upper electrode 102 emits the electrostatic charge Na to the bit line BL.

FIG. 6F shows the state change when the negative pulse Vn is applied to the lower electrode of the ferroelectric capacitor in the polarization state S1. Simultaneously with the rise of the negative pulse voltage, the ferroelectric capacitor changes state from S1 to T2, and the negative charge amount D is emitted from the upper electrode 102 to the bit line BL. When the negative pulse voltage falls, the ferroelectric capacitor changes state from T2 to S1, and the electrostatic charge Da is released from the upper electrode 102 to the bit line BL.

As shown in Fig. 7A, a phenomenon called imprint appears in the ferroelectric capacitor. In the figure, the horizontal axis and the vertical axis represent the voltage and polarization of the lower electrode as in Fig. 6B. If the polarization state S1 is maintained continuously, the hysteresis characteristic tends to change from H0 to H1. If the reverse polarization state S2 is maintained continuously, the hysteresis characteristic tends to change from H0 to H2 in the reverse direction to H1.

As shown in FIG. 7B, when the polarization state S1 is continuously maintained and the hysteresis characteristic is imprinted from H0 to H1, when the reverse polarity S2 is written thereafter, the amount of polarization accumulated is It decreases by the polarization amount (DELTA) P1.

As shown in FIG. 7C, when the polarization state S2 is maintained and the hysteresis characteristic is imprinted from H0 to H2, when the reverse polarity S1 is written thereafter, the amount of polarization accumulated is equal to the polarization amount ( Decrease by ΔP2). If the amount of polarization decreases and cannot be read, the memory device loses its function.

FIG. 8A shows an example of a memory cell configuration of a FeRAM of two transistors and two capacitors (2T / 2C). One FeRAM memory cell includes two ferroelectric capacitors (Cx, Cy) and switching transistors (Tx, Ty) in which a drain electrode is connected to an upper electrode of each ferroelectric capacitor. The source electrodes of the two switching transistors Tx and Ty are connected to the bit lines BL and / BL, the gate electrode is commonly connected to the word line WL, and the lower electrodes of the ferroelectric capacitors Cx and Cy are Commonly connected to plate line PL. The sense amplifier SA is connected between the bit lines BL and / BL.

Reverse polarity information is stored in the ferroelectric capacitors Cx and Cy. For example, when "1" is stored, information "1" is stored in the ferroelectric capacitor Cx, and "0" is stored in the ferroelectric capacitor Cy. In reading, the sense amp SA detects a voltage difference between the bit line BL and the bit line / BL.

A 1T / 1C configuration, which consists of one memory cell with one transistor and one capacitor, is also available. In this case, for example, a combination of the transistor on the right side and the ferroelectric capacitor can be used, and a reference cell can be used instead of the combination of the transistor on the left side and the ferroelectric capacitor. Although the amount of identifiable charge is halved, but there is no essential difference, the following description will be given using 2T / 2C as an example.

Fig. 8B shows the inspection procedure of FeRAM. FIG. 8C is a diagram showing a pulse voltage applied to two ferroelectric capacitors Cx and Cy included in one FeRAM and a charge output emitted to a bit line in the order of FIG. 8B. In addition, the pulse voltage is represented by the voltage with respect to the lower electrode when the upper electrode is made into the reference voltage.

First, in step ST100, first data is written. After that, since the same data is read, the second data of the reverse polarity is written and read, the first data is referred to as the same state (SS) and the second data is referred to as the reverse polarity state (OS).

As shown on the left side of Fig. 8C, first, a positive pulse voltage Vp is applied to the capacitors Cx and Cy, and both capacitors are matched in a polarized state of " 0 ". Subsequently, a positive pulse voltage is applied to the capacitor Cx, a negative pulse voltage is applied to the capacitor Cy, and " 1 " is written in the capacitor Cx, and " O " is written in the capacitor Cy. The first data SS is stored.

In the next step ST110, both capacitors in which the first data SS is written are left in a heating state, for example, 150 ° C. for a long time, for example, 10 hours. Deterioration of the stored information is accelerated in the heating state. There is also a possibility of hysteresis shift accompanying imprints. Thereafter, the first data SS is read in step ST120.

As shown in the center left of FIG. 8C, a positive pulse voltage is applied to both capacitors. When the pulse voltage rises, the electrostatic charge U corresponding to "0" from the capacitor Cx and the electrostatic charge P corresponding to "1" from the capacitor Cy are emitted to each bit line. The first data SS memorized by the difference is read out. Since the information stored by the reading is lost, "0" is written to the capacitor Cx and "1" is written to the capacitor Cy again based on the read information. If the polarization is demagnetized, the first data may not be read. By reading the first data SS, the retention characteristic can be checked.

In step ST130, the second data OS having reverse polarity is written. As shown on the right side of the center of FIG. 8C, positive pulse voltages Vp are applied to both capacitors to match both capacitors in a polarized state of "O", and then the capacitor Cx is negatively polarized. A pulse voltage Vn is applied to write "1", and a positive pulse voltage Vp is applied to the capacitor Cy to write "O". When imprint is occurring, the stored polarization is decreasing.

The second data written in step ST140 is once left, for example, for 5 seconds. It has an effect of preventing relaxation or temperature stabilization, and insufficient evaluation of imprint.

In the next step ST150, the second data OS is read. As shown in the right side of Fig. 8C, a positive pulse voltage Vp is applied to both capacitors. When the pulse voltage rises, the electrostatic charge P corresponding to "1" from the capacitor Cx and the electrostatic charge U corresponding to "0" from the capacitor Cy are emitted to each bit line. The second data OS stored by the difference is read. Since the information stored by the reading is lost, "1" is written to the capacitor Cx and "0" is written to the capacitor Cy again based on the read information.

If the polarization amount is reduced by imprinting the first data, the second data may not be read. By reading the second data OS, the imprint characteristic can be inspected. When the life evaluation is performed, the process returns from step ST150 to step ST100 and the same inspection step is repeated.

In actual FeRAM inspection, device inspection for determining the presence or absence of a defect for all the memory cells and monitor inspection for measuring the amount of charge read for the selected memory cell are performed.

9A is a table showing the conditions of the device inspection and the monitor inspection collectively. The voltage, temperature and time of the device test and the monitor test are shown for each step. The voltages of the device test are all the minimum voltages in the operating voltage range. This is to strictly judge the conditions. The temperature is 150 ° C. in the heat leaving step ST110 and high temperature in the other step. The leaving time is 10 hours in the heat leaving step ST110 and 5 seconds in the step ST140. The voltage of the monitor test is the center voltage of the operating voltage range. The temperature is 150 ° C. in the heat leaving step ST110 and room temperature in the other step. The leaving time is 10 hours in the heat leaving step ST110 and 30 seconds in the step ST140. In the device inspection and the monitor inspection, the voltage and the temperature of the data writing and reading process are constant.

The configuration and manufacturing method of FeRAM are disclosed, for example, in USP 5,953,619, which is cited herein. A test method for FeRAM is disclosed, for example, in US Pat. No. 6,008,659, which is incorporated herein.

Of particular concern with FeRAM is the imprint test. Japanese Laid-Open Patent Publication No. 2001-67896 proposes to measure the operation ramp voltage of the reverse polarity data before and after high temperature storage, and to check the state where the imprint has occurred from the difference. Japanese Laid-Open Patent Publication No. 2002-8397 discloses writing the first data at the maximum operating voltage (in the embodiment, writing only the number of times a predetermined imprint occurs) to generate an imprint, and then writing and leaving the second polarity data of reverse polarity. It is proposed to perform inspection by reflecting the imprint by reading.

It is an object of the present invention to provide a method for inspecting a semiconductor memory device capable of evaluating imprint characteristics in a short time.

According to one aspect of the present invention, a ferroelectric capacitor of a semiconductor memory device having a nonvolatile memory using a ferroelectric capacitor,

(a) writing the first polarization state at the first write voltage,

(b) thermally leaving the first polarized state;

(c) reading the first polarization state at a first read voltage,

(d) after the step (c), writing a second polarization state inverse to the first polarization state,

(e) leaving the second polarization state to stand, and

(f) reading said second polarization state at a second read voltage

At least one of the voltage and temperature of writing and reading differs according to the process, and the holding performance is examined in said process (a), (b), (c), and following said process (d), (e) In (f), an inspection method of a semiconductor memory device for inspecting imprint performance is provided.

According to another aspect of the invention, after leaving the ferroelectric capacitor of the semiconductor memory device having a nonvolatile memory using a ferroelectric capacitor in the first polarization state,

(a) writing a second polarization state inverse to the first polarization state,

(b) leaving the second polarization state to stand, and

(c) reading the second polarization state

And a temperature or voltage of the step (a) is different from the temperature or voltage of the step (c).

Imprint characteristics can be evaluated in a short time by making the imprint appear large or accelerating.

1 is a flowchart showing a flow of a method of inspecting a semiconductor memory device having a ferroelectric capacitor.

2A to 2D are tables and graphs for explaining experiments in which the temperatures of OS writing and reading are changed.

FIG.3 (a)-(c) are the table | surface and graph which demonstrate the experiment at the time of leaving to stand after OS writing to high temperature, and leaving time to change.

4A to 4C are tables and graphs for explaining experiments when the OS write voltage is changed.

5A to 5C are tables and graphs illustrating an experiment when the OS write voltage is changed.

6A to 6F are cross-sectional views and graphs illustrating ferroelectric capacitors.

7A to 7C are graphs for explaining the imprint of a ferroelectric capacitor.

8A to 8C are equivalent circuit diagrams, flowcharts, and diagrams for explaining inspection of ferroelectric capacitors.

9 (a) and 9 (b) are tables showing the inspection method of the ferroelectric capacitor, and graphs showing the life measurement results of the device inspection;

First, the result of having performed life evaluation of a FeRAM device by the present inventors by the conventional test method is shown.

FIG. 9B is a graph showing a result of life evaluation of a bad bit by repeatedly performing the inspection flow shown in FIG. 8B. The horizontal axis represents the integration time, and the vertical axis represents the number of defective bits of the retention characteristic SS and the imprint characteristic OS. The SS bad bit is good without even coming out one bit in the life evaluation of 504 hours. The OS bad bit is 1 bit in a short time, and starts to increase from over 100 hours, to 5 bits at 504 hours. Since the number of bad bits is extremely small, it took over 500 hours to detect the occurrence of imprint. If it is found that the imprint occurs, the manufacturing process of the ferroelectric layer is mainly improved. If the detection takes more than 500 hours, the feedback does not take any time, the development time is long, and the development cost also increases.

1 is a flowchart showing a flow of a method of inspecting a semiconductor memory device having a ferroelectric capacitor. Basically, the same SS writing step (ST100), heat leaving step (ST110), SS reading step (ST120), OS writing step (ST130), OS leaving step (ST140), which are the same as the inspection method shown in FIG. Although the OS read step (ST150) is included, an attempt was made to make the imprint appear large or to accelerate by changing the voltage and temperature of data writing and data reading.

2 is a table and a graph for explaining an experiment in which the temperatures of OS writing and reading are changed. Fig. 2A is a table showing experimental conditions together. As shown at the top, the SS writing step ST100, OS writing step ST130, OS leaving step ST140, and OS reading step ST150 will be described. SS writing step (ST100) was performed at 3.6V and room temperature (about 25 degreeC) instead of the conventional minimum voltage and high temperature. It is expected that writing at high voltage will highlight the characteristics of the ferroelectric. The heat standing step ST110 and the SS reading step ST120 were performed in the same manner as in the prior art.

The OS writing step ST130 is performed at 2.7 V, the temperature is -45 ° C, -5 ° C, and 25 ° C, and the leaving step ST140 is lengthened to 15 minutes, and is performed at a high temperature of 85 ° C, and the OS reading step (ST150). ) Was 2.7 V, and the temperature was performed at -45 ° C and 85 ° C. The combination of writing temperature and reading temperature is four kinds of (-45 degreeC, -45 degreeC), (-45 degreeC, 85 degreeC), (-5 degreeC, 85 degreeC), and (25 degreeC, 85 degreeC). -45 ° C is the lowest operating temperature and 85 ° C is the highest operating temperature.

Fig. 2C shows the change in hysteresis expected when the ferroelectric is made low temperature. At low temperatures, the hysteresis changes as shown by the solid line from the broken line, and widens in the horizontal direction (voltage direction). The high voltage Vc will be high, making writing difficult.

Fig. 2 (d) shows a change in hysteresis expected when the ferroelectric is made high temperature. At high temperatures, the hysteresis changes as shown by the solid line from the broken line, and the longitudinal direction (polarization direction) is reduced. As the polarization is reduced (potato), it will be difficult to read.

2 (b) shows the experimental results. When writing and reading were performed at -45 deg. C, the number of defect bits was zero. It is considered that writing and reading are normally performed even at the minimum operating temperature. By the way, when the reading temperature was changed to 85 占 폚, the number of defect bits increased to 1471. The imprint will look big. When the write temperature was raised to -5 ° C, the number of defect bits became zero. Even if the writing temperature was raised to 25 ° C (room temperature), the number of defect bits was zero.

Although the detailed reason is not clear, it is thought that if the OS is written at low temperature and read at high temperature, the imprint can be emphasized and detected. Although the defect inspection result of the device inspection has been described, the effect of the temperature difference between the write temperature and the read temperature becomes clearer when the charge amount is detected by the monitor inspection. As a result, the imprint does not appear large at the temperature difference of 90 ° C., but the imprint appears remarkably large at the temperature difference of 130 ° C. A temperature difference of at least 100 ° C. will be preferred.

Performing steps ST130 and ST150 of FIG. 1 at low and high temperatures respectively, is expected to have such an imprint emphasis effect.

3 is a table and a graph illustrating an experiment when the leaving time after OS writing is set to a high temperature and the leaving time is changed. 3A is a table showing the experimental conditions together. SS writing step (ST100) was performed at the voltage of 3.7V and room temperature (about 25 degreeC). The OS writing step (ST130) was performed at 2.6V and room temperature, the leaving time of the subsequent leaving step (ST140) was 0, 1, 10, 20, 60 (minutes), and the temperature was 90 degreeC. The OS reading step (ST150) was performed at 2.6V and room temperature.

FIG. 3B is a graph showing OS idle time dependency. The horizontal axis represents the integrated value of the SS thermal standing time, and the vertical axis represents the difference between the charge amount P from the capacitor Cx and the charge amount U from the capacitor Cy at the time of OS reading. The measurement result is shown about each sample of OS standing time 0, 1, 10, 20, 60 (minutes). In any condition, the amount of OS charge decreases at the same time as the heat leaving time is increased. Reduction of the OS charge amount is considered to indicate that the imprint is in progress.

FIG. 3C is a graph showing the percentage (OS rate) of the amount of OS charge decreased when the heat leaving time is 1000 hours with respect to the OS charge amount when the heat leaving time is 24 hours. The OS rate is shown for each OS idle time. Since the steps ST100 and ST110 in which the imprint is considered to occur in each sample are the same, it is considered that the influence of the imprint is stronger as the absolute value of the OS rate is larger. If the OS leaving time is longer, the absolute value of the OS rate tends to be larger, but if the OS leaving time is more than 10 minutes, the increase tendency is saturated.

In order to make the imprint look large, it is understood that the OS idle time is preferably 10 minutes or more. In addition, although OS leaving temperature is made into the maximum temperature of 85 degreeC, when leaving at lower temperature than that, it will be preferable to lengthen the leaving time longer. The high temperature of step ST140 of FIG. 1 for 10 minutes or more indicates this.

4 is a table and a graph for explaining an experiment when the OS write voltage is changed. FIG. 4A is a table showing experimental conditions together. The SS write step ST100 and the OS read step ST150 are the same as in FIG. The write voltages of the OS write step ST130 were changed to 2.2V, 2.6V, and 3.0V. The temperature is room temperature. In addition, the OS leaving step (ST140) was sufficiently lengthened to 20 minutes, and the temperature was also set to 90 ° C.

4B is a graph showing OS write voltage dependency. The horizontal axis represents the integrated value of the SS thermal standing time, and the vertical axis represents the difference between the charge amount P from the capacitor Cx and the charge amount U from the capacitor Cy at the time of OS reading. The measurement result is shown for each sample of OS write voltage 3.0V, 2.6V, and 2.2V. In any condition, the amount of OS charge decreases at the same time as the heat leaving time is increased. Reduction of the OS charge amount is considered to indicate that the imprint is in progress.

FIG. 4C is a graph showing the percentage (OS rate) of how much the OS charge amount decreases when the heat leaving time is 1000 hours with respect to the OS charge amount when the heat leaving time is 24 hours. The OS rate is shown for each OS write voltage. Since the steps ST100 and ST110 in which imprint is considered to occur in each sample are the same, it is considered that the influence of the imprint is stronger as the absolute value of the OS rate is larger. As the OS write voltage decreases, the absolute value of the OS rate tends to increase. For example, OS writing may be desirable at the lowest operating voltage. The low voltage of step ST130 of FIG. 1 indicates this.

5 is a table and a graph for explaining an experiment when the SS write voltage is changed. FIG. 5A is a table showing experimental conditions together. The write voltages of the SS write step ST100 were changed to 4.4V, 3.7V, and 3.0V. The temperature is room temperature. The OS writing step (ST130) was performed at a voltage of 2.6V and room temperature. In other words, the SS write voltage was set higher than the SS read voltage. The OS leaving step ST140 and the OS reading step ST150 are the same as in FIG. 4A.

5B is a graph showing the SS write voltage dependency. The horizontal axis represents the integrated value of the SS thermal standing time, and the vertical axis represents the difference between the charge amount P from the capacitor Cx and the charge amount U from the capacitor Cy at the time of OS reading. The measurement result is shown about each sample of SS write voltage 4.4V, 3.7V, and 3.0V. In any condition, the amount of OS charge decreases at the same time as the heat leaving time is increased. Reduction of the OS charge amount is considered to indicate that the imprint proceeds.

FIG. 5C is a graph showing, as a percentage, the percentage (OS rate) of how much the OS charge amount decreased when the heat leaving time was 1000 hours with respect to the OS charge amount when the heat leaving time was 24 hours. The OS rate is shown for each SS write voltage. Since OS write, neglect, and read are the same conditions, it is considered that imprint occurs strongly as the absolute value of the OS rate increases. As the SS write voltage increases, the absolute value of the OS rate tends to increase. For example, it would be desirable to perform SS writing at the highest operating voltage. The high voltage of step ST100 of FIG. 1 indicates this.

As mentioned above, although this invention was demonstrated about the Example, this invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, and combinations are possible.

Claims (10)

Regarding ferroelectric capacitor of semiconductor memory device having nonvolatile memory using ferroelectric capacitor, (a) writing the first polarization state at the first write voltage, (b) thermally leaving the first polarized state; (c) reading the first polarization state at a first read voltage, (d) after the step (c), writing a second polarization state inverse to the first polarization state, (e) leaving the second polarization state to stand, and (f) reading said second polarization state at a second read voltage Wherein at least one of the voltage and temperature of writing and reading differs depending on the process, and checking the retention performance in the steps (a), (b) and (c), followed by the step (d) (e) and (f), wherein the imprint performance is examined. The method of claim 1, And the temperature of said step (d) is lower than the temperature of said step (f). The method of claim 2, The temperature of said process (d) is 100 degreeC or more lower than the temperature of said process (f), The inspection method of the semiconductor memory device characterized by the above-mentioned. The method according to any one of claims 1 to 3, And said second write voltage is lower than said first write voltage. The method according to any one of claims 1 to 3, And said first write voltage is higher than said first read voltage. The method according to any one of claims 1 to 3, And the step (e) leaves the second polarization state for at least 10 minutes. After the ferroelectric capacitor of the semiconductor memory device having the nonvolatile memory using the ferroelectric capacitor is left in the first polarization state, (a) writing a second polarization state inverse to the first polarization state, (b) leaving the second polarization state to stand, and (c) reading the second polarization state And the temperature or voltage of the step (a) is different from the temperature or voltage of the step (c). The method of claim 7, wherein And the temperature or voltage of said step (a) is lower than the temperature or voltage of said step (c). The method of claim 8, And the temperature of said step (a) is at least 100 占 폚 lower than the temperature of said step (c). The method according to any one of claims 7 to 9, And said step (b) is left for 10 minutes or more.

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