Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
  • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
  • H04N25/17—Colour separation based on photon absorption depth, e.g. full colour resolution obtained simultaneously at each pixel location
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N2209/00—Details of colour television systems
  • H04N2209/04—Picture signal generators
  • H04N2209/041—Picture signal generators using solid-state devices
  • H04N2209/042—Picture signal generators using solid-state devices having a single pick-up sensor
  • H04N2209/047—Picture signal generators using solid-state devices having a single pick-up sensor using multispectral pick-up elements

Definitions

• the present invention relates to pixel sensors. More particularly, the present invention relates to full-color pixel sensors and arrays that use semiconductor material to chromatically filter light vertically and sense multiple wavelength bands at the same location.
• BACKGROUND OF THE INVENTION In active pixel sensors a traditional approach has been to supply a voltage reference for the reset operation of the photodiode within each pixel sensor along one set of wires running through an array of pixel sensors and to read the pixel photocurrent value out on another set of wires running through the array. Wiring for a pixel sensor directly affects the fill factor and the number of components required, thus limiting the performance of the array and affecting the cost to manufacture pixel sensor arrays.
• the present invention provides a passive vertical-color-filter pixel formed on a semiconductor substrate and comprising at least two detector layers configured to collect photo-generated carriers of a first polarity, separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity, the at least two layers disposed substantially in vertical alignment with each other and having different spectral sensitivities as a function of their different depths in the semiconductor substrate, the pixel having a plurality of photodiodes, a plurality of color enable gates and a column output line.
• the present invention provides an active vertical-color-filter pixel formed on a semiconductor substrate and comprising at least two detector layers configured to collect photo-generated carriers of a first polarity, separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity, the at least two layers disposed substantially in vertical alignment with each other and having different spectral sensitivities as a function of their different depths in the semiconductor substrate, the pixel having a plurality of photodiodes, the pixel having a pixel reset voltage and column-output sharing a common line.
• the present invention provides an active vertical-color-filter pixel formed on a semiconductor substrate and comprising at least two detector layers configured to collect photo-generated carriers of a first polarity, separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity, the at least two layers disposed substantially in vertical alignment with each other and having different spectral sensitivities as a function of their different depths in the semiconductor substrate, the pixel having a plurality of photodiodes, the pixel having a shared source-follower voltage and reset voltage.
• the present invention provides an active vertical-color-filter pixel formed on a semiconductor substrate and comprising at least two detector layers configured to collect photo-generated carriers of a first polarity, separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity, the at least two layers disposed substantially in vertical alignment with each other and having different spectral sensitivities as a function of their different depths in the semiconductor substrate, the pixel having a plurality of photodiodes, the pixel having a common line for reset voltage signals, source-follower voltage, and row-enable signals.
• the present invention provides an array of active vertical-color- filter pixels, each pixel formed on a semiconductor substrate and comprising at least two detector layers configured to collect photo-generated carriers of a first polarity, separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity, the at least two layers disposed substantially in vertical alignment with each other and having different spectral sensitivities as a function of their different depths in the semiconductor substrate, the pixel having a plurality of photodiodes, the pixel having at least one read transistor for reading the pixel and a common line for row reset signals and row-enable signals, wherein array is arranged in rows and columns of pixels, the array configured such that the read transistors from one row are cross connected with the photodiodes of another row while the common line shares reset signals for one row in the array and row-enable signals for an adjacent row in the array.
• FIG. 1 is a cross-sectional view of a prior-art three-color VCF pixel sensor.
• FIG. 2A is a combination semiconductor cross sectional diagram and schematic diagram of a VCF pixel sensor according to the present invention.
• FIG. 2B is a schematic diagram depicting the same VCF pixel sensor as shown in FIG. 2 A in which the photodiodes are represented schematically as semiconductor diode symbols.
• FIG. 2C is a schematic diagram depicting transistor circuitry that may be used in a storage version of the VCF pixel sensor of the present invention to which each of the red, green, and blue photodiodes is coupled.
• FIG. 1 is a cross-sectional view of a prior-art three-color VCF pixel sensor.
• FIG. 2A is a combination semiconductor cross sectional diagram and schematic diagram of a VCF pixel sensor according to the present invention.
• FIG. 2B is a schematic diagram depicting the same VCF pixel sensor as shown in FIG. 2 A in which the photodiodes
• FIG. 3 is a semiconductor cross sectional diagram illustrating a vertical-color- filter pixel sensor employing epitaxial semiconductor technology.
• FIGS. 4A through 4E are cross sectional diagrams showing the structure resulting after completion of selected steps in the fabrication process.
• FIG. 5 is a diagram of an imaging array according to the present invention.
• FIGS. 6A and 6B are timing diagrams that illustrate the operation of pixel sensors.
• FIG. 7 is a schematic of a passive VCF pixel sensor.
• FIG. 8 is a schematic of a pixel sensor having a common line for pixel-reset voltage signals and column-output signals as shown in previous active pixel sensors.
• FIG. 9 is a schematic of a VCF pixel sensor having a common line for pixel-reset voltage signals and column-output signals.
• FIG. 10 is a schematic of a VCF pixel sensor having a shared line for the reset voltage signals and column-output signals and another shared line for the pixel-reset signals and row-enable signals as shown in previous active pixel sensors.
• FIG. 11 is a schematic of a VCF pixel sensor having a shared line for pixel-reset signals and row-enable signals and another shared lines for the reset voltage and the column- output signals.
• FIG. 12 is a schematic of a VCF pixel sensor array having an enhanced layout utilizing shared pixel reset and row-enable lines.
• FIG. 13 is a diagram that illustrates operation of a sensor in rolling shutter and video mode.
• FIG. 14 is a diagram of a timeline illustrating rolling shutter mode integration timing.
• FIG. 15 is a schematic illustrating a VCF pixel sensor having a shared line for reset signals and row-enable signals and a shared line for reset voltage and source-follower voltage.
• FIG. 16 is a schematic illustrating a pixel sensor having a shared reset voltage, source-follower voltage, and row-enable line as taught in prior art.
• FIG. 17 is a schematic illustrating a VCF pixel sensor having a shared reset voltage, source-follower voltage, and row-enable line.
• FIG. 18 is a schematic illustrating a simplified VCF pixel sensor having shared reset, source-follower voltage, and row-enable lines and shared reset voltage and column-output lines.
• FIG. 19 is a schematic illustrating a VCF pixel sensor with one output line that is also used for the pixel reset voltage and shared reset, source-follower voltage, and row- enable lines.
• FIG. 20 is a schematic illustrating a pixel sensor having a shared line for source- follower voltage and reset voltage as shown in previous active pixel sensors.
• FIG. 21 is a schematic illustrating a VCF pixel sensor having one column-output line with a shared line for reset voltage and source-follower voltage.
• FIG. 22 is a schematic illustrating the timing for the operation of a simplified VCF pixel sensor.
• FIG. 1 illustrates a first illustrative and non-limiting example of a VCF pixel sensor that can be used to practice the present invention.
• the cross-sectional view shows a prior- art VCF pixel sensor 10 of the type disclosed in United States Patent No. 5,965,875 to Merrill.
• FIG. 1 shows a VCF pixel sensor fabricated in a triple-well process wherein the blue, green, and red sensors are disposed at different depths beneath the surface of the
• the red photodiode is comprised of the junction between the p-type substrate 12 and the n-type well 14
• the green photodiode is comprised of the junction between the n-type well 14 and the p-type well 16
• the blue photodiode is comprised of the junction between the p-type well 16 and the n-type lightly-doped-drain implant 18 at the surface of the substrate.
• Photocurrent is sensed from the red, green, and blue photodiodes as indicated symbolically by current meters 20, 22, and 24, respectively.
• FIG. 2 A illustrates a second illustrative and non-limiting example of a VCF pixel sensor that may be used to practice the present invention.
• VCF pixel sensor 30 is a six- layer structure that is shown schematically in cross-sectional view fabricated on p-type semiconductor substrate 32. This type of VCF pixel sensor has three n-type regions, isolated vertically by p-regions that are all connected to the substrate potential. The blue, green, and red photodiode sensors are formed by the junctions between the n-type and p-type regions, and are disposed at different depths beneath the surface of the semiconductor structure.
• FIG. 2B depicts the same VCF pixel sensor as shown in FIG. 2A.
• the photodiodes are represented schematically as semiconductor diode symbols.
• FIGS. 2 A and 2B show a non-storage version of a VCF pixel sensor in which each of the red, green, and blue photodiodes is coupled to a transistor circuit.
• Each circuit has a reset transistor 54 driven from a RESET signal line and coupled between the photodiode cathode and a reset potential, a source-follower amplifier transistor 56 coupled to the photodiode cathode, and a row-select transistor 58 driven from a ROW-SELECT signal line and coupled between the source of the source-follower amplifier transistor and a row line.
• the suffixes "r,” “g,” and “b” are used to denote the color associated with each transistor.
• the RESET signal is active to reset the pixel sensor and is then inactive during exposure, after which the row-select line is activated to read out the pixel data. Referring now to FIG.
• FIG. 2C a schematic diagram depicts transistor circuitry that may be used in a storage version of the VCF pixel sensor of the present invention to which each of the red, green, and blue photodiodes is coupled.
• the transistor circuit of FIG. 2C includes an additional transfer transistor 59 not found in the circuits of FIGS. 2 A and 2B.
• the gate of transfer transistor 59 is coupled to a XFR line that is held active for at least part of the time that the RESET voltage line is active and goes inactive at the end of the exposure time, after which the row-select line is activated to read out the pixel data.
• One advantage of the circuit of FIG. 2C is that the use of the transfer transistors eliminates the need for a mechanical shutter.
• VCF pixel sensors in a semiconductor structure.
• the six-layer structure of alternating p-type and n-type regions can be formed using a semiconductor substrate as the bottom layer and forming five concentric wells of alternating conductivity type in the substrate.
• the hatched areas of FIG. 3 show the approximate locations of the implants used to create the p-type and n-type regions of the structure.
• the dashed line 76 defines the approximate border between the net-P and net-N doping for the blue detector 74.
• the dashed line 78 defines the approximate border between the net-P and net-N doping for the green detector 70 with its vertical portion to the surface of the second epitaxial layer 72 forming the contact to the green detector 70.
• the dashed line 80 defines the approximate border between the net-P and net- N doping for the red detector 64 with its vertical portion to the surface of the second epitaxial layer 72 forming the contact to the red detector 64.
• FIGS. 4A through 4E cross-sectional diagrams showing the structure resulting after completion of selected steps in the process.
• the process starts with a lei 5 p-type substrate 90 shown in FIG. 4 A.
• a blanket boron implant (shown at reference numeral 92) is performed to a depth of about 0.5 um.
• This boron implant 92 must be more heavily doped than the substrate because it acts as weak diffusion barrier to prevent electrons generated in the substrate 90 from diffusing up to the green photodiode, as well as separating the red photodiodes.
• This blanket implant may also serve to counteract autodoping during the subsequent epitaxial layer deposition step.
• This blanket implant should generally be anywhere from about 3X to 100X of the substrate doping level and in one embodiment of the invention is about lel6.
• an implant masking layer (not shown) is then applied using conventional photolithographic techniques. Next, as shown in FIG.
• a masked phosphorus lel7 implant (shown at reference numeral 94) is performed at an energy of around 50keV followed by an activation cycle as is known in the art to form the n-type layer for the red detector.
• This implant dose should be selected to be sufficient to overcompensate the blanket p-type implant.
• the drive cycle must ensure adequate annealing for both the boron and phosphorus implants prior to growth of an epitaxial silicon layer.
• the order of the p- type blanket implant and the n-type masked implant to form the red photodiode n-type region could be reversed. Referring now to FIG.
• a layer of lel5 p-type epitaxial silicon 96 is grown to a thickness of about 2.0 um.
• the dopant concentration in the epitaxial layer 96 is as lightly doped as will guarantee p-type material in order that it will function as a potential well region so that photo-electrons generated therein do not diffuse past the p-type layers above or below it.
• Punch-through from red to green photodiodes is another design constraint affecting doping level in this layer, i.e., the doping needs to be sufficient to prevent depletion regions from the red and green photodiode cathodes from getting too close to each other, or fully depleting the p-type region between them.
• a plug implant masking layer (not shown) is then applied using conventional photolithographic techniques.
• a lel7 phosphorus plug implant and an anneal sequence is then performed to form a plug contact to the cathode of the red photodiode.
• This plug implant should be a high-energy implant (i.e., about 1,000 KeV) or should comprise multiple implant steps at different energies.
• a tall, thin plug contact plug is formed by a combination of two different implants, one a high-energy implant 98 (i.e., about 1,200 KeV) for deep doping the bottom region of the plug contact, and the other a lower energy implant 100 (i.e., about 600 KeV) for doping the intermediate region of the plug contact, followed by a third implant or diffusion that is performed along with the doping for the green photodiode to complete the shallow surface region of the plug contact.
• the plug resistance is not important since the photocurrent is small, however the size of the plug should be as small as possible to minimize pixel area and maximize fill factor.
• a plug size of 1 micron is a good target, but the depth of the plug contact needs to be about 2 microns.
• the multiple-implant plug disclosed herein makes it possible to achieve such a plug with a depth greater than its width.
• an implant-masking layer (not shown) is then applied using conventional photolithographic techniques.
• a lel7 phosphorus implant at an energy of around 50 KeV (shown at reference numeral 104) and activation sequence is then performed to form the n-type layer for the green detector.
• a second, smaller aperture in this masking layer serves to form the surface region 102 of the plug contact implant for the contact to the underlying cathode of the red detector.
• this implant requires activation drive to restore lattice integrity before the subsequent epitaxial layer deposition step.
• a blanket boron implant 106 of the epitaxial layer 96 is performed.
• This implant serves to counteract autodoping during the subsequent epitaxial layer deposition step.
• This implant also serves as a weak diffusion barrier to prevent green-photon- generated carriers from diffusing upward to the blue detector and separates the green photodiodes.
• This blanket implant 106 should generally be anywhere from about 3X to 100X of the doping level of the first epitaxial layer 96 and in one embodiment of the invention is about lel6.
• a layer of lei 5 p-type epitaxial silicon 108 is grown to a thickness of about 0.7 to 1.0 um.
• An implant masking layer (not shown) is then applied using conventional photolithographic techniques.
• a standard CMOS n-well implant is performed to form n-well regions 110 to make contact to the cathode 104 of the underlying green detector and n-well region 112 to make contact to the top of the plug contact 102 for the cathode 94 of the bottom red detector.
• the n-well regions 110 and 112 may require a double implant to reach the buried layers comprising the cathode 106 of the green detector and the plug contact for the cathode 94 of the red detector; typical CMOS n-well implant energies are around 500 KeV and 100 KeV, respectively, for the deep and shallow implants in n-well regions 110 and 112.
• an implant masking layer (not shown) is then applied using conventional photolithographic techniques.
• a CMOS p-well implant step is then performed to create p-well regions 114.
• the CMOS p-well implant step may require a double energy implant to minimize the n-well-to-n-well spacing.
• These p-well regions 114 are for isolation between the contacts for the red and green detector plugs as well as between pixels (the rightmost and leftmost edge p-well regions).
• this p-well implant is used to create wells in which NMOS transistors for the rest of the circuitry on the chip is formed.
• an implant masking layer (not shown) is then applied using conventional photolithographic techniques.
• a lightly-doped-drain implant shown at reference numeral 116 is then performed to form the cathode of the blue detector.
• other apertures in this masking layer form surface portions of the deep contact regions for the red and green detectors, to allow good electrical contact to an overlying metal interconnect layer.
• more heavily doped n-type regions may be formed in a separate processing step to form surface portions 118 and 120 of the deep contact regions for the red and green detectors as well as a contact region within the lightly-doped- drain implant for the blue detector.
• the cathode of the blue detector might be formed with a p-well underneath (i.e., an extension of regions 114).
• the process employed for fabricating the VCF pixel sensor of the present invention is compatible with standard CMOS processes. The additional process steps are all performed prior to the standard CMOS steps, thus minimizing interactions. Two epitaxial layers 96 and 108, as sometimes employed in BiCMOS, are required, as well as two extra implant activation cycles, one before each epitaxial growth step. As is apparent to such persons of ordinary skill, three extra masks are required in the process for implanting the n-type regions 94, 98, 100 102, and 104 for the red detector, the red contact plug, and the green detector.
• the process requires five extra implants including the red detector counterdoping 92 and the green detector counterdoping 106 (six extra implants are required if regions 98 and 100 are formed separately).
• the masking, implanting, drive-in and anneal, and epitaxial growth fabrication process steps described above for fabricating the novel structure disclosed herein are individually well known to persons of ordinary skill in the semiconductor processing art for fabricating other semiconductor devices. Process parameters, such as times, temperatures, reactant species, etc. will vary between individual processes but are known for use in such individual processes. Such details will not be recited herein to avoid overcomplicating the disclosure and thus obscuring the invention.
• the fabrication process disclosed herein provides several advantages. There are no large lateral diffusions associated with implant and drive wells, resulting in a smaller pixel area.
• the vertical plugs that are needed in order to connect to buried layers can be small. There is no need for large n-type or p-type isolation rings. Only the detector plug contacts need to be isolated from each other and the other detectors. This allows for a small sensor group area. As shown, this six-layer three-color photodiode structure uses two epitaxial layers, as are sometimes found in BiCMOS processes. Silicon quality generally improves as more epitaxial layers are grown.
• the sensor group including pixel readout circuits according to this embodiment of the present invention can be made in any BiCMOS fabrication facility. The topmost layers may be formed using a conventional CMOS process, (i.e., n+, n-well, and p-well).
• FIG. 5 a diagram shows an illustrative 2 by 2 portion 120 of an array of VCF pixel sensors that may be used in accordance to the present invention.
• the array portion disclosed in FIG. 5 is illustrative only and that arrays of arbitrary size may be fabricated using the teachings herein.
• the illustrative array example of FIG. 5 employs circuitry with a storage feature such as is depicted in FIG. 2C including a transfer transistor and so includes a global transfer signal line serving the array.
• the 2 by 2 portion 120 of the array in FIG. 5 includes two rows and two columns of VCF pixel sensors.
• a first row includes VCF pixel sensors 122-1 and 122-2; a second row includes VCF pixel sensors 122-3 and 122-4.
• a first column includes VCF pixel sensors 122-1, 122-3; a second column includes VCF pixel sensors 122-2 and 122-4.
• a first ROW-SELECT line 124-1 is connected to the row-select inputs (ROW- SELECT) of VCF pixel sensors 122-1 and 122-2.
• a second ROW-SELECT line 124-2 is connected to the row-select inputs (ROW-SELECT) of VCF pixel sensors 122-3 and 122- 4.
• the first and second ROW-SELECT lines may be driven from a row decoder (not shown) as is well known in the art.
• a first set of three (blue, green, and red) COLUMN-OUT lines 126-1 is connected to the outputs of VCF pixel sensors 122-1 and 122-3.
• a second set of three COLUMN- OUTPUT lines 126-2 is connected to the outputs of VCF pixel sensors 122-2 and 122-4.
• the first and second sets of COLUMN-OUTPUT lines are coupled to sets of column readout circuits (not shown) as is well known in the art.
• a global RESET voltage line 128 is connected to the reset (R) inputs of all of the VCF pixel sensors 122-1 through 122-4.
• a first VSFD line 130-1 is connected to the VSFD inputs of the VCF pixel sensors 122-1 and 122-2 in the first row of the array.
• a second VSFD line 130-2 is connected to the VSFD inputs of the VCF pixel sensors 122-3 and 122-4 in the second row of the array.
• a global XFR line 132 is connected to the XFR inputs of all of the VCF pixel sensors 122-1 through 122-4.
• a global PIX-VCC line 134 is connected to the PIX-VCC inputs of all of the VCF pixel sensors 122-1 through 122-4. Alternately, multiple PIX-VCC lines (one for each color) could be provided.
• FIG. 6A a timing diagram illustrates the operation of the embodiment of the VCF pixel sensors shown in FIG. 2C of the present invention. Initially, the RESET signal is asserted high. The drains of the reset transistors 54b, 54g, and 54r are brought from zero volts to the voltage PLX-VCC.
• This action resets all VCF pixel sensors in the array by placing the voltage potential PIX-VCC at the cathode of each photodiode.
• the voltage PIX-VCC is initially at a low level (e.g., to zero volts) while RESET is high to reset the cathode voltages of all photodiodes in the array to a low value to quickly equalize their states.
• the voltage PIX-VCC is raised (e.g., to about 2 volts) for a predetermined time (preferably on the order of a few milliseconds) while the RESET signal is still asserted to allow the photodiodes in all VCF pixel sensors to charge up to about 2.0 volts.
• the black level at the photodiode cathodes is thus set to PIX-VCC, less a little for the capacitive turn-off transient from the reset transistors.
• the RESET signal is de-asserted and photointegration begins, charge accumulates on the photodiode cathodes.
• the voltage at the source of the source-follower transistors 56b, 56g, and 56r follows the voltage on their gates.
• the XFR signal is asserted throughout the reset period and the integration period and is de-asserted to end the integration period as illustrated in FIG. 6A.
• the low level of the XFR signal is preferably set to zero or a slightly negative voltage, such as about -0.2 volts, to thoroughly turn off transfer transistors 59b, 59g, and 59r.
• the drains of the source-follower transistors 56b, 56g, and 56r are driven to the voltage VSFD on the PixVCC line, the ROW-SELECT signal for the row of the array containing the transistors 59b, 59g, and 59r is asserted, and the output signal is thereby driven onto COLUMN-OUTPUT lines.
• the timing of the assertion of the VSFD voltage on the PixVCC signal is not critical, except that it should remain high until after the ROW-SELECT signal is de-asserted as illustrated in FIG. 6A.
• FIG. 6B a timing diagram illustrates one method for operating the sensor group realization of FIG. 2B.
• the reset operation proceeds as described relative to FIG. 6A. After RESET falls, exposure can begin; however, since without the XFR switch the active pixel sensor does not have an electronic shutter capability, it may be the case that a mechanical shutter is used to control the exposure.
• a SHUTTER signal is shown, indicative of a time when a shutter is letting light fall on the sensor.
• the RESET signal is not re-asserted as it was in FIG. 6A, since the signal needs to remain stored on the photodiode cathodes until after readout.
• Readout using ROW-SELECT and VSFD works as described with respect to FIG. 6A.
• PIX-VCC and RESET can be cycled back to their initial states.
• the control signals depicted in FIGS. 6 A and 6B may be generated using conventional timing and control logic.
• FIG. 7 shows a passive VCF pixel sensor 200 having no amplifier. This results in a reduced number of components per pixel and improved fill factor.
• VCF pixel sensor has detector layers configured to collect photo-generated carriers of a first polarity, separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity. The layers are disposed substantially in vertical alignment with each other and have different spectral sensitivities as a function of their different depths in the semiconductor substrate.
• VCF pixel sensor 200 includes a column-output line 202 and a plurality of color-enable lines 204, 206, and 208 associated with the different detector layers. Also included in VCF pixel sensor 200 is a plurality of color-enable transistors 210, 212, and 214. Each color-enable transistor is coupled between a different detector layer and the column-output line 202, and has a gate coupled to a different color-enable line.
• the charge stored in the photodiodes must directly drive column-output line 202 that can have a higher capacitance than the photodiode. Thus, the voltage on column- output line 202 doesn't vary much when a photodiode value is read.
• the operation of VCF pixel sensor 200 is as follows.
• Reset voltage V ref is driven onto the column-output line 202 through a switch (not shown), and signals on the three color-enable lines 204, 206, and 208 are asserted. This charges the photodiodes to a known voltage. If different reset voltages are desired for the different colors, they can be set in sequence by applying, for example, the red reset voltage to the column-output line 202 and asserting the red color-enable line 204, then driving the green reset voltage onto the column- output line 202 and asserting the green color-enable line 206 and likewise for blue. After an integration period, the voltage on the photodiodes decreases proportionally to the number of photons intercepted by each of the photodiodes.
• Sensor 200 is read out a row at a time and a color at a time by first charging column-output line 202 to a known voltage through a switch (not shown), and then asserting the red color-enable line 204 and reading the voltage difference on the column-output line 202.
• the column-output line 202 is charged to a known voltage, the green color-enable line 206 is asserted and the voltage difference on the column-output line 202 is read. These steps are repeated for blue.
• VCF pixels such as VCF pixel 200, the next row of pixels can be read out in the same way.
• FIG. 8 illustrates a pixel sensor 230 having a common line for pixel-reset voltage signals and column-output signals as shown in US patent 5,654,537.
• FIG. 9 illustrates a VCF pixel sensor 240 having shared lines 242, 244, 246 for reset voltage V ref , and column-output signals. This sharing removes one wire from the pixel sensor.
• VCF pixel sensor 240 also includes reset-signal line 248, row-enable line 250, and source-follower-drain-voltage line 252.
• Reset transistor 254 is coupled between a detector layer and column-output/reference-voltage line 242, and has a gate coupled to reset-signal line 248.
• Reset transistor 256 is coupled between a second detector layer and column- output/reference-voltage line 244, and has a gate coupled to reset-signal line 248.
• Source- follower transistor 258 has a gate coupled to the first detector layer, a drain coupled to source-follower-drain-voltage line 252, and a source.
• Source-follower transistor 260 has a gate coupled to the second detector layer, a drain coupled to source-follower-drain-voltage line 252, and a source.
• Output-enable transistor 262 has a gate coupled to row-enable line 250, a drain coupled to the source of source-follower transistor 258, and a source coupled to column-output/reference-voltage line 242.
• Output-enable transistor 264 has a gate coupled to row-enable line 250, a drain coupled to the source of source-follower transistor 260, and a source coupled to column-output/reference-voltage line 244.
• a third detector layer can be included in VCF pixel sensor 240 with reset transistor 266, source-follower transistor 268 and output-enable transistor 270 arranged as described above.
• the reset signal is driven high while a switch (not shown) connects the column-output lines to the reset voltage V ref . This charges the photodiodes to a known voltage.
• Pixel sensor 240 is then is exposed to light for a fixed period of time.
• each photodiode decreases proportionally to the number of photons intercepted by each photodiode.
• the switch that connects reset voltage V ref to column-output lines 242, 244, and 246 is opened so that the pixels can drive the lines.
• Each photodiode in sensor 240 is connected to the input of a source-follower amplifier. The rows in the sensor are read out by driving the row-enable line high, thus connecting the pixel source-follower amplifier outputs to the column-output lines.
• VCF pixel sensor 240 Another advantage of VCF pixel sensor 240 is that the red, green, and blue photodiodes can be charged up to different voltages without having three reset voltage V ref lines, since there are three V ref /column-output lines instead of only one reset voltage V ref line. This is useful since the photodiodes might respond differently to light or their leakage currents may be different.
• FIG. 10 illustrates two pixel sensors 250 having a row-enable line from one row connected to a reset voltage V ref line to another row as shown in U.S. patent 5,083,016.
• FIG. 11 illustrates how the reset voltage V ref line from one row can be combined with the row-enable line of a different row on lines 270, 272 in VCF pixel sensor array 260.
• VCF pixel sensor array 260 includes reset-signal/row-enable line 270 associated with the row (m) of array 260, and a reset- signal/row-enable line 272 associated with a row (m+1) of array 260.
• VCF pixel sensor array 260 also includes source-follower-drain-voltage line 274, column-output/reference- voltage lines 276, 278, and 280, each associated with column (n) of array 260.
• Reset transistor 282 is coupled between the first detector layer and column-output/reference- voltage line 276 and has a gate coupled to reset-signal/row-enable line 272 associated with row (m+1) of array 260.
• Reset transistor 284 is coupled between the second detector layer and column- output/reference-voltage line 278, and has a gate coupled to reset-signal/row-enable line 272 associated with row (m+1) of array 260.
• Source-follower transistor 286 has a gate coupled to the first detector layer, a drain coupled to source-follower-drain-voltage line 274, and a source.
• Source-follower transistor 288 has a gate coupled to the second detector layer, a drain coupled to source-follower- drain-voltage line 274, and a source.
• Output-enable transistor 290 has a gate coupled to reset-signal/row-enable line 270, a drain coupled to the source of source-follower transistor 286, and a source coupled to column-output/reference-voltage line 276.
• Output-enable transistor 292 has a gate coupled to reset-signal/row-enable line 270, a drain coupled to the source of source-follower transistor 288, and a source coupled to column-output/reference-voltage line 278.
• a third reset transistor 294 can be coupled between a third detector layer and column-output/reference-voltage line 280.
• Reset transistor 294 has a gate coupled to reset-signal/row-enable line 272 associated with row (m+1) of array 260.
• Source-follower transistor 296 has a gate coupled to the third detector layer, a drain coupled to source-follower-drain-voltage line 274, and a source.
• Output- enable transistor 298 has a gate coupled to reset-signal/row -enable line 270, a drain coupled to the source of source-follower transistor 296, and a source coupled to column- output/reference-voltage line 280.
• FIG. 12 shows array 300 of VCF pixel sensor that are similar to VCF pixel sensor 260 except that the photodiodes are cross-connected to the adjacent row instead of the Reset/Row-enable line. This allows for a very compact layout of the six transistors that connect to the Reset/Row-enable line and also to the three column-output lines.
• Array 300 includes a plurality of rows and columns of active VCF pixel sensors formed on a semiconductor substrate, an array column (n), including column- output/reference-voltage line 302 and column-output reference-voltage line 304.
• Column (n) has a plurality of rows. Each row includes reset-signal/row-enable line 306, source- follower-drain-voltage line 308, and a pixel sensor.
• the pixel sensors include first and second detector layers disposed substantially in vertical alignment with each other, having different spectral sensitivities as a function of their different depths in the semiconductor substrate, and configured to collect photo-generated carriers of a first polarity.
• the first and second detector layers are separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• Reset transistor 310 is coupled between the first detector layer and column- output/reference-voltage line 302, and has a gate coupled to reset-signal/row-enable line 306-1.
• Reset transistor 312 is coupled between the second detector layer and second column-output/reference-voltage line 304, and has a gate coupled to reset-signal/row-enable line 306-1.
• Source-follower transistor 314 has a gate, a drain coupled to source-follower- drain- voltage line 308-1, and a source.
• Source-follower transistor 316 has a gate, a drain coupled to source-follower-drain- voltage line 308-1, and a source.
• Output-enable transistor 318 has a gate coupled to reset- signal/row-enable line 306-1, a drain coupled to the source of source-follower transistor 314, and a source coupled to column-output/reference-voltage line 302.
• Output-enable transistor 320 has a gate coupled to reset-signal/row-enable line 306- 1, a drain coupled to the source of source-follower transistor 316, and a source coupled to column-output/reference-voltage line 304.
• the gate of source-follower transistor 314 in each pixel sensor in each row (m) in the column (n) is coupled to the first detector layer of the pixel sensor in row (m+1) in column (n), and the gate of source-follower transistor 316 in each pixel sensor in each row (m) in column (n) is coupled to the second detector layer of the pixel sensor in row (m+1) in column (n).
• the first and the last rows are different because there is no previous or next row respectively to interconnect.
• the detector layers For the first row of the sensor there is nothing to connect the detector layers to and there are no detector layers to connect to the source-followers in the last row. There are a number of different ways to connect up the first and last rows.
• One possible implementation is to connect the detector layers from the first row to the source-followers in the last row. This however adds two or more signal lines from the top of the array to the bottom for each column in the array. Also since these signals will be long, they will pick up a lot of noise and resistive drop across the array will be large so the performance of the first row photo detectors would be poor.
• Another possible solution is to leave the photo detector layers in the first row unconnected and connect some other signal to the source-followers in the last row.
• column (n) includes column- output/reference-voltage line 324.
• Each row further includes a third detector layer configured to collect photo-generated carriers of a first polarity.
• the third detector layer is separated from the first and second detector layers by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity, and is disposed substantially in vertical alignment with the first and second detector layers and having a spectral sensitivity as a function of its depth in the semiconductor substrate.
• Reset transistor 322 is coupled between the third detector layer and column- output/reference-voltage line 324, and has a gate coupled to reset-signal/row-enable line 306-1.
• Source-follower transistor 326 has a gate, a drain coupled to source-follower-drain- voltage line 308-1, and a source.
• Output-enable transistor 328 has a gate coupled to reset- signal/row-enable line 306-1, a drain coupled to the source of source-follower transistor 326, and a source coupled to column-output/reference-voltage line 324;
• the gate of source-follower transistor 326 in each pixel sensor in each row (m) in the column (n) is coupled to the third detector layer of the pixel sensor in row (m+1) in column (n).
• the first and the last rows are different because there is no previous or next row respectively to interconnect. For the first row of the sensor there is nothing to connect the detector layers to and there are no detector layers to connect to the source-followers in the last row. There are a number of different ways to connect up the first and last rows.
• One possible implementation is to connect the detector layers from the first row to the source- followers in the last row. This however adds two or more signal lines from the top of the array to the bottom for each column in the array. Also since these signals will be long, they will pick up a lot of noise and resistive drop across the array will be large so the performance of the first row photo detectors would be poor.
• Another possible solution is to leave the photo detector layers in the first row unconnected and connect some other signal to the source-followers in the last row.
• Another solution is to leave out the photo detector layers and reset transistors from the first row and leave out the row-enable and source follower transistors from the last row. In most of these solutions no useful information is obtained from reading the last row so it should either not be read or the values should be ignored.
• FIG. 13 illustrates a rolling shutter mode in which pixel sensor arrays of the present invention can be used for video, very fast-exposure time photos, or long-exposure time photos, where the exposure time is longer than the time it would normally take to deplete the available charge on the photodiode, can still be implemented with this wiring simplification.
• a sequence of rolling shutter images each shorter then the time to deplete the photodiodes, can be added together to create a long exposure image.
• the row-enable for row n is connected to the reset for row n-1 with the row-enable line for the first row resetting the last row.
• An integration time interval is defined as the time difference between when a row is reset and when it is read out. The integration time interval is equal to the amount of time that the shutter is open, or the time interval where photons that are collected are counted.
• FIG. 13 shows the case where row 900 was just reset and row 2 is being read out, followed by resetting row 901 and reading row 3.
• FIG. 14 shows a time line where the integration time interval is the same for each row and the integration time for each row being different.
• the integration interval may be modified, depending on the amount of light to which the sensor is exposed.
• the integration interval can be changed by varying the number of rows between the reset and read operations.
• the integration time interval can also be increased by adding delays between each reset/read operation.
• the rolling shutter window can be most of the sensor except two rows, the ones with interconnected row reset and row-enable. Therefore in rolling shutter mode, for most of the time during a long-exposure photo the photons intercepted are counted by the pixel sensor and only during a very short time while the pixel sensor is being reset and read out are the photons that are intercepted not counted. As shown in FIG. 14, row n is read as row n-1 is reset. The reset operation is acceptable because row n-1 is in the inactive sensor area.
• the only limitation for connecting the row-enable line for row n to the reset voltage line for row n- 1 is that the reset/read out operation can only occur in one direction, from top to bottom.
• the reset voltage for this pixel sensor configuration can either be connected to the column-output lines as it is in pixel sensors illustrated in FIG. 13 or the V SFD line can accommodate the reset voltage as shown in VCF pixel sensors illustrated in FIG. 15.
• the advantage of using the column-output lines as shown in FIG. 13 is that the reset voltage for each of the different photodiodes in a pixel sensor can be different. This requires coordination between reset and read out since the column-output lines are used for both operations.
• FIG. 15 illustrates array 350 including a plurality of rows and columns of active vertical-color-filter pixel sensors formed on a semiconductor substrate, an array column (n), including column-output line 352 and column-output line 354.
• Column (n) includes a plurality of rows, each row having reset-signal/row-enable line 356, source-follower-drain- voltage/reference-voltage line 358, and a pixel sensor.
• Each pixel sensor includes first and second detector layers disposed substantially in vertical alignment with each other, having different spectral sensitivities as a function of their different depths in the semiconductor substrate, and configured to collect photo-generated carriers of a first polarity. The first and second detector layers separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• Reset transistor 364-1 is coupled between the first detector layer and source- follower-drain- voltage/reference- voltage line 358, and has a gate.
• Reset transistor 366-1 is coupled between the second detector layer and source-follower-drain-voltage/reference- voltage line 358, and has a gate.
• Source-follower transistor 360-1 has a gate coupled to the first detector layer, a drain coupled to source-follower-drain-voltage/reference-voltage line 358, and a source.
• Source-follower transistor 362-1 has a gate coupled to the second detector layer, a drain coupled to source-follower-drain-voltage/reference-voltage line 358, and a source.
• Output-enable transistor 368-1 has a gate coupled to reset-signal/row-enable line 356-1, a drain coupled to the source of source-follower transistor 360-1, and a source coupled to column-output/reference-voltage line 352.
• Output-enable transistor 370-1 has a gate coupled to reset-signal/row-enable line 356-1, a drain coupled to the source of source- follower transistor 362-1, and a source coupled to column-output/reference-voltage line 354;
• the gates of reset transistors 364-1, 366-1 in each pixel sensor in each row (m) in column (n) are coupled to reset-signal/row-enable line 356-2 of the pixel sensor in row (m+1) in column (n).
• array 350 includes a third column-output line 372.
• Each row also includes a third detector layer configured to collect photo-generated carriers of a first polarity.
• the third detector layer is separated from the first and second detector layers by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• the third detector layer is disposed substantially in vertical alignment with the first and second detector layers and has a spectral sensitivity as a function of its depth in the semiconductor substrate.
• Reset transistor 376-1 is coupled between the third detector layer and source- follower-drain-voltage/reference-voltage line 358 and has a gate.
• Source-follower transistor 374- 1 has gate coupled to the third detector layer, a drain coupled to source-follower-drain- voltage/reference- voltage line 358, and a source.
• Output-enable transistor 378-1 has a gate coupled to reset-signal/row-enable line 356-1, a drain coupled to the source of source- follower transistor 374-1, and a source coupled to column-output/reference-voltage line 372.
• the gate of reset transistor 376-1 in each pixel sensor in each row (m) in the column (n) is coupled to reset-signal/row-enable line 356-2 of the pixel sensor in row (m+1) in column (n). There is no signal to drive the reset transistors in the last row since normally this signal come from the next row. There are a number of different ways to deal with this. One way is to connect the reset transistors in the last row to the row enable signal 356-1 from the first row.
• FIG. 16 illustrates a pixel sensor 375 having a shared line for row-enable, V ref and V SFD as shown in U.S patent 5, 949, 061. Row-enable signals, V ref and V SFD can also share a line in a VCF pixel sensor 400 as illustrated in FIG. 17.
• FIG. 17 illustrates active VCF pixel sensor 400 formed on a semiconductor substrate that has first and second detector layers configured to collect photo-generated carriers of a first polarity.
• the first and second detector layers are separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• the first and second detector layers are disposed substantially in vertical alignment with each other and have different spectral sensitivities as a function of their different depths in the semiconductor substrate.
• Reset transistor 414 is coupled between the first detector layer and source-follower- drain-voltage/reference-voltage/row-enable line 404, and has a gate coupled to reset-signal line 402.
• Reset transistor 416 is coupled between the second detector layer and source- follower-drain-voltage/reference-voltage/row-enable line 404, and has a gate coupled to reset-signal line 402.
• Source-follower transistor 410 has a gate coupled to the first detector layer, a drain coupled to source-follower-drain-voltage/reference-voltage/row-enable line 404, and a source.
• Source-follower transistor 412 has a gate coupled to the second detector layer, a drain coupled to source-follower-drain-voltage/reference-voltage/row-enable line 404, and a source.
• Output-enable transistor 418 has a gate coupled to source-follower-drain- voltage/reference-voltage/row-enable line 404, a drain coupled to the source of source- follower transistor 410, and a source coupled to column-output line 406.
• Output-enable transistor 420 has a gate coupled to source-follower-drain- voltage/reference-voltage/row-enable line 404, a drain coupled to the source of source- follower transistor 412, and a source coupled to column-output line 408.
• a third detector layer is configured to collect photo-generated carriers of a first polarity.
• the third detector layer is separated from the first and second detector layers by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• the third detector layer is disposed substantially in vertical alignment with the first and second detector layers and has a spectral sensitivity as a function of its depth in the semiconductor substrate.
• reset transistor 426 coupled between the third detector layer and source-follower-drain-voltage/reference-voltage/row- enable line 404.
• Reset transistor 426 has a gate coupled to reset-signal line 402.
• Source- follower transistor 424 has a gate coupled to the third detector layer, a drain coupled to source-follower-drain-voltage/reference-voltage/row-enable line 404, and a source.
• Output- enable transistor 428 has a gate coupled to source-follower-drain-voltage/reference- voltage/row-enable line 404, a drain coupled to the source of source-follower transistor 424, and a source coupled to column-output line 422.
• VCF pixel sensor 400 The operation of VCF pixel sensor 400 is as follows. First the V ref V SFD /row-enable signal is driven to the level required to reset the pixel sensor to the desired voltage. The reset signal is also driven high. The row-reset signal can then be driven low followed by V re /V SFD /Row_en. After an integration period, the voltage on the photodiodes decreases proportionally to the number of photons intercepted by each photodiode. To read out the pixel sensor, the V ref V SFD /row-enable signal is driven high which makes the source-follower amplifier operational as well as enables the row-enable transistor so that the pixel sensor can drive the column-output lines.
• VCF pixel sensor array 450 It is also possible to combine the three pixel wiring simplifications into one VCF pixel sensor array 450, as shown in FIG. 18.
• the reset voltage V ref line is shared with column-output lines 452, 454, and 470. This allows different pixel reset voltages for the different photodiodes in each pixel. Again this can be useful if the different photodiodes' responses are different.
• VCF pixel sensors in array 450 also share the reset line for row n with the row-enable line with row n+1.
• Another simplification in the VCF pixel sensors in array 450 is that the source-follower-voltage V SFD and row-enable signals also are shared. This signal also happens to be shared with the reset for a different row in the pixel sensor array.
• Array 450 includes a plurality of rows and columns of active vertical-color-filter pixel sensors formed on a semiconductor substrate, an array column (n), including column- output/reference-voltage line 452 and column-output/reference-voltage line 454.
• the column (n) includes a plurality of rows, each row having a reset-signal/row-enable/source- follower-drain-voltage line 456.
• Each pixel sensor includes first and second detector layers disposed substantially in vertical alignment with each other that have different spectral sensitivities as a function of their different depths in the semiconductor substrate, and are configured to collect photo-generated carriers of a first polarity.
• the first and second detector layers are separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• Reset transistor 458 is coupled between the first detector layer and column- output/reference-voltage line 452, and has a gate.
• Reset transistor 460 is coupled between the second detector layer and column-output/reference-voltage line 454, and has a gate.
• Source-follower transistor 462 has a gate coupled to the first detector layer, a drain coupled to reset-signal/row-enable/source-follower-drain-voltage line 456, and a source.
• Source- follower transistor 464 has a gate coupled to the second detector layer, a drain coupled to reset-signal/row-enable/source-follower-drain-voltage line 456, and a source.
• Output-enable transistor 466 has a gate coupled to reset-signal/row-enable/source-follower-drain-voltage line 456, a drain coupled to the source of source-follower transistor 462, and a source coupled to column-output/reference-voltage line 452.
• Output-enable transistor 468 has a gate coupled to reset-signal/row-enable/source-follower-drain-voltage line 456, a drain coupled to the source of source-follower transistor 464, and a source coupled to column- output/reference-voltage line 454.
• the gates of reset transistors 458, 460 in each pixel sensor in each row (m) in the column (n) are coupled to reset-signal/row-enable/source- follower-drain-voltage line 456-2 of the pixel sensor in row (m+1) in column (n). There is no signal to drive the reset transistors in the last row since normally this signal come from the next row. There are a number of different ways to deal with this.
• Array 450 can also be implemented to accommodate three detector layers.
• column (n) further includes a third column-output/reference- voltage line 470.
• Each row of array 450 further includes a third detector layer configured to collect photo-generated carriers of a first polarity.
• the third detector layer is separated from the0 first and second detector layers by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• the third detector layer is disposed substantially in vertical alignment with the first and second detector layers and has a spectral sensitivity as a function of its depth in the semiconductor substrate.
• Reset transistor 472 is coupled between the third detector layer and source-follower-5 drain-voltage/reference- voltage line 456, and has a gate.
• Source-follower transistor 474 has a gate coupled to the third detector layer, a drain coupled to reset-signal/row-enable/source- follower-drain-voltage line 456, and a source.
• Output-enable transistor 476 has a gate coupled to reset-signal/row-enable/source-follower-drain-voltage line 456, a drain coupled to the source of source-follower transistor 474, and a source coupled to third column-0 output/reference- voltage line 470.
• the gate of third reset transistor 472 in each pixel sensor in each row (m) in the column (n) is coupled to reset-signal/row-enable/source-follower- drain- voltage line 456-2 of the pixel sensor in row (m+1) in column (n). There is no signal to drive the reset transistors in the last row since normally this signal come from the next row. There are a number of different ways to deal with this.
• One way is to connect the reset5 transistors in the last row to the V SFD /Reset/row enable signal 456-1 from the first row. Another solution would be to create another signal, which is the logic equivalent of the V SFD /Reset/Row_en signal 456-1 for the first row in the array, which is routed after the last row in the array and connected to the reset transistors in the last row of the array. Another solution is to tie the reset transistors in the last row to a static value and not use the values i0 from the last row since the reset will not operate properly.
• the first step in operating the pixel sensors in array 450 is to charge up the photodiodes to a known voltage.
• V SFD /reset/row-enable signal For a row or the whole array high while at the same time driving the V ref voltages for each color on the column-output lines. Then the V SFD /reset/row-enable signal can be de-asserted. After a given integration period, the voltage on each of the photodiodes will have decreased proportional to the number of photons intercepted by each of the photodiode.
• Array 450 can then be read out one row at a time by asserting V SFD /reset/row-enable signal for a row that is also the V SFD voltage for the source-follower amplifiers.
• the V SFD reset/row-enable signal will also turn on the row-enable gates for one row.
• the pixel values can then be read out for one row.
• the photodiode in the row that shares the reset/row-enable signal and uses it for the reset function is reset to a value proportional to the values being read from the row that uses the reset/row-enable signal for row-enable.
• the order that the rows are read out is performed such that the row being reset has already been read out. This works for every row except for the first row unless the pixel sensor is constructed such that it does not share its row-enable line with the reset voltage V ref line of another row.
• reset/row-enable signal can be driven low and a different reset/row-enable can be driven high to read out that row.
• the array is reset a row at a time in the same order as it is read out, usually from the top to the bottom, by driving the V ref voltage for each of the colors on the column-output lines and asserting the V SFD /reset/row- enable signal for each of the rows.
• Sequential rows are reset one at a time. When the bottom of the array is reached the first row is reset again. This is repeated over and over again. After the integration interval time from when the first row was reset, the readout can begin with the first row and continue sequentially through the array.
• the column-output lines are driven with the reset voltage V ref , for each of the colors when a row is being reset and are not driven with reset voltage V ref when a row is being read out.
• the readout of this row is performed as before.
• a different V SFD /Reset/Row-en signal is asserted to reset a row and then another row is read.
• the pixel sensor alternates between reading a row and resetting a row. This must be coordinated since the column-output lines are used for reading out rows as well as providing the reset voltage, V ref .
• the integration interval is the time difference between when a row is reset and when it is read out.
• Each row in array 450 has a different integration period since each row is reset and read out at different times.
• FIG. 19 illustrates array 500 of active VCF pixel sensors formed on a semiconductor substrate.
• Array 500 includes an array column (n), and a column-output/reference-voltage V ref line 502.
• Column (n) includes a plurality of rows, each including reset-signal/row- enable/source-follower-drain-voltage line 504, color-enable line 506, color-enable line 508; and a pixel sensor.
• Each pixel sensor includes first and second detector layers disposed substantially in vertical alignment with each other, having different spectral sensitivities as a function of their different depths in the semiconductor substrate are configured to collect photo-generated carriers of a first polarity. The first and second detector layers are separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity. Also included is photocharge-output-signal node 512.
• Color-enable transistor 514 is coupled between the first detector layer and photocharge-output-signal node 512, and has a gate coupled to color-enable line 506.
• Color- enable transistor 516 is coupled between the second detector layer and photocharge-output- signal node 512, and has a gate coupled to color-enable line 508.
• Reset transistor 518 is coupled between photocharge-output-signal node 512 and column-output/reference-voltage line 502, and has a gate.
• Source-follower transistor 520 has a gate coupled to photocharge-output-signal node 512, a drain coupled to reset- signal/row-enable/source-follower-drain-voltage line 504, and a source.
• Output-enable transistor 522 has a gate coupled to reset-signal/row-enable/source-follower-drain-voltage line 504, a drain coupled to the source of source-follower transistor 520, and a source coupled to column-output/reference-voltage line 502.
• the gate of reset transistor 518 in each pixel sensor in each row (m) in the column (n) is coupled to the reset-signal/row-enable/source-follower-drain-voltage line 504-2 of the pixel sensor in row (m+1) in column (n). There is no signal to drive the reset transistors in the last row since normally this signal come from the next row. There are a number of different ways to deal with this.
• Array 500 can also be implemented to accommodate three detector layers.
• column (n) further includes color-enable line 530.
• a third detector layer configured to collect photo-generated carriers of a first polarity, which is separated from the first and second detector layers by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• the third detector layer is disposed substantially in vertical alignment with the first and second detector layers and has a spectral sensitivity as a function of its depth in the semiconductor substrate.
• Color-enable transistor 532 is coupled between the third detector layer and photocharge-output-signal node 512, and has a gate coupled to color-enable line 530.
• the operation of pixel sensors in array 500 requires control of the enable lines 506, 508, 530, one per color that needs to be controlled.
• Column-output line 502 is also used for the reset voltage V ref line.
• column-output line 502 is driven by the V ref value and the reset/row-enable signal is asserted.
• Signals on the three color-enable lines 506, 508, 530 can be asserted if all of the photodiodes are to be charged up to the same value or they can be enabled in sequence, changing the reset voltage V ref voltage being driven on column-output line 502 for each color.
• the pixel sensor is exposed to light for a given integration time. After the integration time the photodiodes' voltage will have dropped proportionally to the number of photons that were intercepted by each of the photodiodes.
• the gate of the source-follower amplifier needs to be set to a known voltage before the pixel values are read out.
• Column-output line 502 should be sampled while the V SFD Reset/row-enable signal is still asserted and not count on the charge stored in column-output line 502 to hold its value since a slow falling transition on the VSFD/Reset/row-enable line will cause uncertainty in the value stored on column- output line 502.
• the gate of the source-follower amplifier should again be set to a known voltage as described above. Then the next photodiode can be read out.
• Pixel sensors in array 500 may also be operated in rolling shutter mode but the photodiodes need to be read out in sequence instead of in parallel since the pixel is connected to only one column-output line.
• a pixel could contain one red and one blue detector and 4 green detectors. Usually the area of the smaller detectors (green) together would approximately equal the area of the larger detector areas (red and blue). This would provide higher resolution in luminance while reducing the number of transistors for the chrominance.
• This structure may be combined with the sequential readout circuit of the invention to create a particularly compact pixel.
• each detector of the pixel has a single color-enable transistor whose output couples to the photocharge-output-signal node of the pixel.
• Several smaller detectors on one color may be included in a single source- follower and row enable transistor pixel output structure with proportionally fewer detectors of another color. For example, if the red and blue sensors from a two by two array of sensor groups were shorted together, the four reds shorted to one another and the four blues shorted to one another, they could be combined with the four green sensors into a single output cell. This cell would have six color-enables, one for red, one for blue and four for green.
• the pixel sensor is reset by driving the V re V SFD to the pixel reset voltage and driving high the reset and transfer signals. This will charge up the photodiode to a known voltage.
• the transfer gate and reset signal and V rej V SFD are driven low. After a set integration time the voltage on the photodiode will have decreased proportionally to the number of photons intercepted by the photodiode.
• To read out the pixel the gates on all of the source-follower amplifiers must be reset to zero, or slightly below zero, to prevent them from turning on while other rows are being read out. This is done by driving V ref /V SFD low and reset high while the transfer signal is low.
• reset can be driven low and then row by row the V ref V SFD and transfer signal for a row can be driven high which will make the source-followers for that row operational and a voltage proportional to the photodiode voltage is driven onto the column-output lines.
• the source-follower gate must again be discharged. This is done by driving V ref /V SFD to ground and asserting the reset signal for the row just read. Then reset can be de-asserted and the next row can be read. While the operation is slightly more complicated, it does eliminate another transistor from the pixel sensor. It is also possible to remove the row-enable gate from a VCF pixel sensor shown in VCF pixel sensor 550 in FIG. 21.
• VCF pixel sensor 550 has only five transistors and six wires, with four of the wires (the three enable lines and the reset voltage V ref line) carrying low impedance signals.
• One advantage of this is that low impedance lines are less sensitive to some process defects than high impedance lines, improving yield.
• Array 550 includes a plurality of rows and columns of active vertical-color-filter pixel sensors formed on a semiconductor substrate, an array column (n), and column-output line 552.
• the column has a plurality of rows. Each row includes reset-signal line 554, reference-voltage/source-follower-drain-voltage line 556, color-enable line 558, color-enable line 560, and a pixel sensor.
• the pixel sensor includes first and second detector layers disposed substantially in vertical alignment with each other, having different spectral sensitivities as a function of their different depths in the semiconductor substrate, and are configured to collect photo- generated carriers of a first polarity.
• the first and second detector layers are separated by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• photocharge-output-signal node 562 Also included is photocharge-output-signal node 562.
• Color-enable transistor 564 is coupled between first detector layer and photocharge- output-signal node 562, and has a gate coupled to color-enable line 558.
• Color-enable transistor 566 is coupled between the second detector layer and photocharge-output-signal node 562, and has a gate coupled to color-enable line 560.
• Reset transistor 568 is coupled between photocharge-output-signal node 562 and reference-voltage/source-follower-drain- voltage line 556, and has a gate coupled to reset-signal line 554.
• Source-follower transistor 570 has a gate coupled to photocharge-output-signal node 562, a drain coupled to reference- voltage/source-follower-drain-voltage line 556, and a source coupled to column-output line 552.
• Array 550 can also be implemented to accommodate three detector layers.
• column (n) further includes a third color-enable line 572.
• a third detector layer is configured to collect photo-generated carriers of a first polarity and is separated from the first and second detector layers by additional intervening layers configured to collect and conduct away photo-generated carriers of the opposite polarity.
• the third detector layer disposed substantially in vertical alignment with the first and second detector layers and has a spectral sensitivity as a function of its depth in the semiconductor substrate.
• Color-enable transistor 574 is coupled between the third detector and photocharge-output-signal node 562, and has a gate coupled to color-enable line 572.
• a pixel could contain one red and one blue detector and 4 green detectors. Usually the area of the smaller detectors (green) together would approximately equal the area of the larger detector areas (red and blue). This would provide higher resolution in luminance while reducing the number of transistors for the chrominance.
• This structure may be combined with the sequential readout circuit of the invention to create a particularly compact pixel. In this arrangement each detector of the pixel has a single color-enable transistor whose output couples to the photocharge-output-signal node of the pixel. Several smaller detectors on one color may be included in a single source- follower and row enable transistor pixel output structure with proportionally fewer detectors of another color.
• FIG. 22 illustrates the timing operation of VCF pixel sensor 550. To operate pixel sensor 550 it is first necessary to charge up the photodiode to a known voltage.
• V ref /V SFD line 556 Before reading any rows out it is necessary to discharge the gate on the source-follower by driving the V ref /V SFD line 556 to ground and asserting the reset signal. This discharges the gate on the source-follower amplifier to make sure it is turned off when other rows in array 550 are being read.
• the V re V SFD line 556 is asserted while the reset voltage V ref line is still asserted which will charge up the gate of the source-follower amplifier.
• the reset signal for the row being read is deasserted and one of the color-enable lines is asserted. Then a signal proportional to the voltage at the photodiode that is selected is driven onto column-output line 552.
• the color-enable signal is deasserted and the reset signal is again asserted to set the voltage on the source-follower to a known value. Then reset is deasserted and the next color-enable is asserted.
• the source-follower gate is reset to a known voltage and the last photodiode can be read. The gate of the source-follower should then be reset to ground as before so that other rows can be read.

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• 2004
  • 2004-05-27 JP JP2007515014A patent/JP4542138B2/ja not_active Expired - Lifetime
  • 2004-05-27 WO PCT/US2004/016805 patent/WO2005120048A1/en active Application Filing
  • 2004-05-27 CN CN2004800431666A patent/CN1957599B/zh not_active Expired - Lifetime

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