WO2005119686A2 - Procede pour augmenter la largeur de bande d'une memoire ddr dans des modules sdram ddr - Google Patents

Procede pour augmenter la largeur de bande d'une memoire ddr dans des modules sdram ddr Download PDF

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Publication number
WO2005119686A2
WO2005119686A2 PCT/US2005/018679 US2005018679W WO2005119686A2 WO 2005119686 A2 WO2005119686 A2 WO 2005119686A2 US 2005018679 W US2005018679 W US 2005018679W WO 2005119686 A2 WO2005119686 A2 WO 2005119686A2
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WO
WIPO (PCT)
Prior art keywords
cas
precharge
memory
page
ras
Prior art date
Application number
PCT/US2005/018679
Other languages
English (en)
Other versions
WO2005119686A3 (fr
Inventor
Ryan M. Petersen
Franz Michael Shuette
Original Assignee
Ocz Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ocz Technology filed Critical Ocz Technology
Priority to EP05760508.1A priority Critical patent/EP1776641B1/fr
Priority to AU2005251173A priority patent/AU2005251173B2/en
Publication of WO2005119686A2 publication Critical patent/WO2005119686A2/fr
Publication of WO2005119686A3 publication Critical patent/WO2005119686A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Definitions

  • the present invention generally relates to memory devices, and more particularly relates to increasing the bandwidth of DDR (double data rate) SDRAM (synchronous dynamic random access memory) modules.
  • DDR double data rate
  • SDRAM synchronous dynamic random access memory
  • the present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules.
  • DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the end of an ongoing transfer.
  • the Variable Early Read command the effect of the CAS latency is minimized in terms of the effect on bandwidth.
  • the enhanced bandwidth technology achieved with this invention optimizes the remaining two access latencies (t RP and t co) for optimal bandwidth.
  • Figure 1 is a schematic overview of an internal bank of a memory device: After a row has been selected and activated (highlighted area on left), the Column Address Strobe (CAS) can select a block of logically coherent addresses within this row (right). The number of page hits is limited among other factors by the limited number of column addresses within each page. Note that, per DRAM convention, rows are running vertically and columns horizontally.
  • Figure 2 is a timing diagram for two modules, one running at t RCD -4.
  • the effective bandwidth is the ratio between data transfers (diamonds): NoOps (arrows) which, in the case of EB is 8:7 without EB, this ratio is 8:10, meaning that every transfer of 16 bits is penalized with either 7 or 10 subsequent bus idle cycles (Abbreviations used: t RC D; RAS-to-CAS delay; CL: CAS latency; t R P : precharge-to-activate delay; Clk: clock; Act: row activate command; Rd: read command; Pr: Precharge command, NoOp: No Operation).
  • Figure 3 shows the effect of issuing an Early Read Command on back-to-back transactions of consecutively requested data blocks within the same page. Following one Row Activate Command, three Read commands are given at a CAS Latency of either 2, 2.5 or 3. The squares are the data transfers that belong to the square-shaped Read Command. The graph shows that the net effect of increasing the CAS latency is a single cycle delay within a string of (in this case) 12 consecutive transfers but no degradation of bandwidth. The double-arrows indicate the CAS latency which is amended by moving the read command further to the left (relative to the end of the previous b ⁇ ist). (Abbreviations used: Clk: clock; Act: row activate command; Rd: read command; Pr: Precharge command, CL: CAS Latency).
  • Figure 4 illustrates an alternate embodiment of the present invention.
  • Tjie present, invention provides enhanced bandwidth (EB) technology as a means of increasing memory bandwidth through the optimization of memory latencies for the best possible interaction between the system memory and the chipset and memory controller.
  • EB enhanced bandwidth
  • Memory bandwidth is influenced by two major factors; frequencies and latencies.
  • Transfer frequency is important since the theoretical peak bandwidth is defined by the bus width (in number of bits) multiplied by the frequency.
  • Theoretical peak bandwidth is defined as the physical limit of the number of bytes that can be transferred from sender to receiver without counting idle bus period.
  • the total theoretical peak bandwidth is a factor of the operating frequency alone. In real life, however, this equation is not adequate.
  • No computer system regardless of how well it is optimized, is able to achieve peak transfer rates in a sustained fashion since only a limited number of back-to-back transactions can be carried out.
  • Initial access latencies, along with memory-internal parameters such as page boundaries within the memory devices, pose an effective barrier to the actual peak bandwidth.
  • Each page hit specifies a block of 64 column addresses that results in an output of eight transfers of eight bits each (in the case of an x8 memory device).
  • subsequent blocks do not need to follow a contiguous column address pattern as long as the sequence is predetermined. This is important for the understanding how, within a given page, the Column Address Strobe (CAS) can jump back and forth between higher and lower addresses without missing the page.
  • CAS Column Address Strobe
  • a read command is issued.
  • the time taken for this entire process is the RAS-to-CAS delay (t C D ) ⁇
  • Both t RP and t RC D are the two main factors that cause a reduction in effective memory bandwidth.
  • the CAS latency (CL) determines the number of penalty cycles incurred between the read command and the start of data output to the bus.
  • a read command can be issued concurrent with an ongoing data burst. This means that the read command for the next data burst can be issued before an ongoing data transfer is exhausted with the result that the latency cycles are hidden behind the previous transfer.
  • CAS latency therefore plays a much smaller role in limiting bandwidth than RAS-to-CAS Delay or Precharge latency.
  • CL CAS latency
  • EB technology further capitalizes on another feature possible in DDR through the Variable Early Read Command. Early Read Command compensates for higher CAS latencies by changing the time at which a read command is issued relative to an ongoing transfer.
  • the 2.5-2-3 (CL-t R P -t R C D )will deliver bandwidth that is indistinguishable from CL-2 modules, and t R P and t R D latencies that are both lower than the CAS latency CL, such as 2.5,-2,-2 (CL-t P -t RCD ), will work even better.
  • Current computer technology uses a dedicated memory controller that is either part of the chipset or else integrated directly on the CPU itself, This memory controller genprates the addresses and commands at pre-specified timing intervals.
  • one embodiment of the current .t ⁇ y ti$n,it ⁇ usjjr ⁇ ted in Figure 4 uses a mejnpry cqnttoller integrated on the mernory module 400' that includes a data buffer 410 and is fanning out to the individual memory ,; integrated chips 420 to generate the addresses and commands at the specified latencies.
  • a fully buffered module connected to the core logic 500 via a high-speed serial bus 510 will see the same or better improvement of bandwidth according to the method of the invention.

Abstract

La présente invention concerne un procédé destiné à augmenter la largeur de bande d'une mémoire DDR dans des modules SDRAM DDR. La mémoire DDR comprend une fonction intégrée, appelée commande de prélecture variable, délivrée en fonction d'un temps d'attente CAS avant la fin d'une rafale de données en cours de traitement. L'utilisation de la commande de prélecture variable permet de réduire au minimum l'effet du temps d'attente CAS sur la largeur de bande. La technique d'amélioration de la largeur de bande mise en oeuvre optimise les deux temps d'attente d'accès ( tRP and tRCD) restants pour une largeur de bande optimale. Ces optimisations dans le SPD produisent des largeurs de bande considérablement meilleures dans des applications réelles.
PCT/US2005/018679 2004-05-26 2005-05-26 Procede pour augmenter la largeur de bande d'une memoire ddr dans des modules sdram ddr WO2005119686A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05760508.1A EP1776641B1 (fr) 2004-05-26 2005-05-26 Procede pour augmenter la largeur de bande d'une memoire ddr dans des modules sdram ddr
AU2005251173A AU2005251173B2 (en) 2004-05-26 2005-05-26 Method of increasing DDR memory bandwidth in DDR SDRAM modules

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52157004P 2004-05-26 2004-05-26
US60/521,570 2004-05-26

Publications (2)

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WO2005119686A2 true WO2005119686A2 (fr) 2005-12-15
WO2005119686A3 WO2005119686A3 (fr) 2007-01-11

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US (1) US8151030B2 (fr)
EP (1) EP1776641B1 (fr)
AU (1) AU2005251173B2 (fr)
TW (1) TWI380314B (fr)
WO (1) WO2005119686A2 (fr)

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See also references of EP1776641A4

Also Published As

Publication number Publication date
EP1776641A2 (fr) 2007-04-25
AU2005251173A1 (en) 2005-12-15
US8151030B2 (en) 2012-04-03
WO2005119686A3 (fr) 2007-01-11
TWI380314B (en) 2012-12-21
EP1776641B1 (fr) 2013-05-01
TW200614256A (en) 2006-05-01
US20050278474A1 (en) 2005-12-15
AU2005251173B2 (en) 2009-09-03
EP1776641A4 (fr) 2007-12-05

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