WO2005117263A3 - High speed clock distribution transmission line network - Google Patents

High speed clock distribution transmission line network Download PDF

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Publication number
WO2005117263A3
WO2005117263A3 PCT/US2005/018176 US2005018176W WO2005117263A3 WO 2005117263 A3 WO2005117263 A3 WO 2005117263A3 US 2005018176 W US2005018176 W US 2005018176W WO 2005117263 A3 WO2005117263 A3 WO 2005117263A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock
tree
clock distribution
transmission line
transmission lines
Prior art date
Application number
PCT/US2005/018176
Other languages
French (fr)
Other versions
WO2005117263A2 (en
Inventor
Chung-Kuan Cheng
Hongyu Chen
Original Assignee
Univ California
Chung-Kuan Cheng
Hongyu Chen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ California, Chung-Kuan Cheng, Hongyu Chen filed Critical Univ California
Priority to EP05764271A priority Critical patent/EP1751865A4/en
Priority to KR1020067026839A priority patent/KR101178990B1/en
Priority to US11/596,968 priority patent/US7679416B2/en
Priority to JP2007515257A priority patent/JP5097542B2/en
Priority to CN200580020428A priority patent/CN100594678C/en
Publication of WO2005117263A2 publication Critical patent/WO2005117263A2/en
Publication of WO2005117263A3 publication Critical patent/WO2005117263A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention is directed to a method for clock distribution and VLSI circuits include a clock distribution network. In a method of the invention, a transmission lines (18) are patterned as to connect a clock tree and a periodic waveform clock, preferably a sine waveform, is used to control clock skew, even at frequencies extending into the gigahertz range. In an exemplary embodiment of the invention, an overlay includes differential pairs of transmission lines that connect the drivers (20) of a clock distribution tree (16). In preferred embodiments of the invention, an H-tree clock distribution scheme (16) is overlaid with a spiral of transmission lines (18), each realized by a differential conductors and driven using a sinusoidal standing wave to distribute global clock signals into local regions of the chip. Each transmission line (18) connects drivers (20) in the H-tree (16) that are at the same level of the H-tree (16). In a VLSI chip according to an embodiment of the invention, the transmission line overlay delivers sinusoidal clock signals to local areas that are locally converted into digital clock signals. The invention thus presents a passive technique for clock distribution.
PCT/US2005/018176 2004-05-24 2005-05-23 High speed clock distribution transmission line network WO2005117263A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP05764271A EP1751865A4 (en) 2004-05-24 2005-05-23 High speed clock distribution transmission line network
KR1020067026839A KR101178990B1 (en) 2004-05-24 2005-05-23 High speed clock distribution transmission line network
US11/596,968 US7679416B2 (en) 2004-05-24 2005-05-23 High speed clock distribution transmission line network
JP2007515257A JP5097542B2 (en) 2004-05-24 2005-05-23 High-speed clock distribution transmission line network
CN200580020428A CN100594678C (en) 2004-05-24 2005-05-23 High speed clock distribution transmission line network

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57392204P 2004-05-24 2004-05-24
US60/573,922 2004-05-24

Publications (2)

Publication Number Publication Date
WO2005117263A2 WO2005117263A2 (en) 2005-12-08
WO2005117263A3 true WO2005117263A3 (en) 2006-04-20

Family

ID=35451564

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/018176 WO2005117263A2 (en) 2004-05-24 2005-05-23 High speed clock distribution transmission line network

Country Status (6)

Country Link
US (1) US7679416B2 (en)
EP (1) EP1751865A4 (en)
JP (1) JP5097542B2 (en)
KR (1) KR101178990B1 (en)
CN (1) CN100594678C (en)
WO (1) WO2005117263A2 (en)

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US20070127922A1 (en) * 2005-12-06 2007-06-07 Applied Materials, Inc. Eliminating clock skew by using bidirectional signaling
US20070127615A1 (en) * 2005-12-06 2007-06-07 Applied Materials, Inc. DC technique for eliminating phase ambiguity in clocking signals
US20070126490A1 (en) * 2005-12-06 2007-06-07 Applied Materials, Inc. Patent Counsel, Legal Affairs Dept. Average time extraction circuit for eliminating clock skew
US20070127930A1 (en) * 2005-12-06 2007-06-07 Applied Materials, Inc. Skew correction system eliminating phase ambiguity by using reference multiplication
US20070127921A1 (en) * 2005-12-06 2007-06-07 Applied Materials, Inc. Average time extraction by multiplication
US20080209038A1 (en) * 2007-02-23 2008-08-28 Raza Microelectronics, Inc. Methods and systems for optimizing placement on a clock signal distribution network
CN101803267B (en) * 2007-07-20 2013-03-13 蓝色多瑙河实验室公司 Method and system for multi-point signal generation with phase synchronized local carriers
US8018950B2 (en) 2008-03-17 2011-09-13 Wi-Lan, Inc. Systems and methods for distributing GPS clock to communications devices
US9459651B2 (en) * 2011-11-04 2016-10-04 Freescale Semiconductor, Inc. Multi-level clock signal distribution network and integrated circuit
US9030253B1 (en) 2012-05-30 2015-05-12 Altera Corporation Integrated circuit package with distributed clock network
KR102012904B1 (en) 2012-11-30 2019-08-21 삼성전자주식회사 Semiconductor integrated chip and operating method thereof
US9312813B2 (en) 2012-12-18 2016-04-12 Continental Automotive Systems, Inc. Instrument panel cluster
WO2014108736A1 (en) 2013-01-08 2014-07-17 Freescale Semiconductor, Inc. Clock source, method for distributing a clock signal and integrated circuit
US20150033050A1 (en) * 2013-07-25 2015-01-29 Samsung Electronics Co., Ltd Semiconductor integrated circuit and computing device including the same
US9543965B1 (en) 2013-10-04 2017-01-10 Altera Corporation Interposer with embedded clock network circuitry
US9349682B2 (en) * 2014-02-27 2016-05-24 Mediatek Inc. Semiconductor chip and semiconductor chip package each having signal paths that balance clock skews
US9602125B1 (en) 2014-10-01 2017-03-21 Northrup Grumman Systems Corporation Wideband InP digital-to-analog converter integrated with a SiGe clock distribution network
US10418939B2 (en) 2014-10-30 2019-09-17 The Regents Of The University Of California LC resonant clock resource minimization using compensation capacitance
GB2532284A (en) 2014-11-17 2016-05-18 Ibm Method to reduce dynamic clock skew and/or slew in an electronic circuit
US9582028B1 (en) * 2015-03-26 2017-02-28 Liming Xiu Circuits and methods of TAF-DPS based chip level global clock signal distribution
TWI562448B (en) * 2015-06-03 2016-12-11 Univ Nat Yunlin Sci & Tech Transmitting structure and terahertz wave supply system
CN204830986U (en) 2015-07-10 2015-12-02 杭州三花微通道换热器有限公司 Heat exchanger
US20180006653A1 (en) * 2016-06-29 2018-01-04 Altera Corporation Integrated circuits with hybrid fixed/configurable clock networks
KR20220011904A (en) * 2020-07-22 2022-02-03 에스케이하이닉스 주식회사 Clock distribution network, a semiconductor appratus and a semiconductor system using the same
US11579649B1 (en) 2021-12-30 2023-02-14 Analog Devices, Inc. Apparatus and methods for clock duty cycle correction and deskew
CN114883772B (en) * 2022-07-07 2022-09-23 香港中文大学（深圳） Transmission line module for rotary traveling wave oscillator and design method thereof

Citations (2)

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US6037820A (en) * 1997-12-12 2000-03-14 Fujitsu Limited Clock distribution circuit in a semiconductor integrated circuit
US6208702B1 (en) * 1998-01-23 2001-03-27 International Business Machines Corporation High frequency clock signal distribution utilizing CMOS negative impedance terminations

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GB9217679D0 (en) 1992-08-20 1992-09-30 Marconi Gec Ltd Combiners for r.f.power amplifiers
JP2806166B2 (en) * 1992-09-01 1998-09-30 日本電気株式会社 Semiconductor integrated circuit
JPH06244282A (en) * 1993-02-15 1994-09-02 Nec Corp Semiconductor integrated circuit device
JP3112784B2 (en) * 1993-09-24 2000-11-27 日本電気株式会社 Clock signal distribution circuit
US5656963A (en) * 1995-09-08 1997-08-12 International Business Machines Corporation Clock distribution network for reducing clock skew
US6098176A (en) * 1998-01-30 2000-08-01 International Business Machines Corporation Sinusoidal clock signal distribution using resonant transmission lines
US6205571B1 (en) 1998-12-29 2001-03-20 International Business Machines Corporation X-Y grid tree tuning method
JP2000200114A (en) * 1999-01-07 2000-07-18 Nec Corp Clock distribution circuit
JP2002132377A (en) * 2000-10-25 2002-05-10 Nec Microsystems Ltd Clock signal distributor circuit and distribution signal method
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JP3599017B2 (en) * 2001-11-20 2004-12-08 日本電気株式会社 Adjustment method of clock propagation delay time
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Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037820A (en) * 1997-12-12 2000-03-14 Fujitsu Limited Clock distribution circuit in a semiconductor integrated circuit
US6208702B1 (en) * 1998-01-23 2001-03-27 International Business Machines Corporation High frequency clock signal distribution utilizing CMOS negative impedance terminations

Non-Patent Citations (1)

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Title
See also references of EP1751865A4 *

Also Published As

Publication number Publication date
US20080030252A1 (en) 2008-02-07
JP5097542B2 (en) 2012-12-12
JP2008504720A (en) 2008-02-14
EP1751865A4 (en) 2009-10-21
US7679416B2 (en) 2010-03-16
WO2005117263A2 (en) 2005-12-08
KR101178990B1 (en) 2012-09-03
KR20070020082A (en) 2007-02-16
EP1751865A2 (en) 2007-02-14
CN100594678C (en) 2010-03-17
CN1998138A (en) 2007-07-11

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