Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
  • G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
  • G01T1/29—Measurement performed on radiation beams, e.g. position or section of the beam; Measurement of spatial distribution of radiation
  • G01T1/2914—Measurement of spatial distribution of radiation
  • G01T1/2985—In depth localisation, e.g. using positron emitters; Tomographic imaging (longitudinal and transverse section imaging; apparatus for radiation diagnosis sequentially in different planes, steroscopic radiation diagnosis)
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B6/00—Apparatus or devices for radiation diagnosis; Apparatus or devices for radiation diagnosis combined with radiation therapy equipment
  • A61B6/02—Arrangements for diagnosis sequentially in different planes; Stereoscopic radiation diagnosis
  • A61B6/03—Computed tomography [CT]
  • A61B6/037—Emission tomography
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T1/00—General purpose image data processing
  • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Definitions

• the present invention pertains to the field of Positron Emission
• Tomography More particularly, this invention is directed to a dedicated memory device for extremely flexible and general purpose support of on-line event- by-event normalization, real-time physiological gating, unity (+/-) histogramming, and weighted histogramming.
• positron-emitting isotopes In PET, short-lived positron-emitting isotopes, referred to as radiopharmaceuticals, are injected into a patient. When these radioactive drugs are administered to a patient, they distribute within the body according to the physiologic pathways associated with their stable counterparts. As the radiopharmaceutical isotopes decay in the body, they discharge positively charged particles called positrons. Upon discharge, the positrons encounter electrons, and both are annihilated. As a result of each annihilation event, gamma rays are generated in the form of a pair of diametrically opposed photons approximately 180 degrees (angular) apart.
• PET images (often in conjunction with an assumed physiologic model) are used to evaluate a variety of physiologic parameters such as glucose metabolic rate, cerebral blood flow, tissue viability, oxygen metabolism, and in vivo brain neuron activity.
• the present invention is a device for improved on-line histogramming of data acquired in a Positron Emission Tomography (PET) scan.
• PET Positron Emission Tomography
• the device of the present invention permits very fast read-modify- write (RMW, +/- unity and weighted) histogramming memory cycles, and permits very large amounts of RMW memory to be effectively controlled from a single PC motherboard running a single operating system (OS).
• OS operating system
• the present invention also is configurable for on-line buffering of the coincidence packet stream, i.e., "gating buffer” which allows "bad beat” rejection and real-time phase-driven segmentation as needed for physiological cycles such as cardiac and respiratory.
• the Gating Buffer card alternately stores an arriving PET data packet stream into two dedicated DRAM banks.
• the two DRAM banks store and retransmit the packet stream in the order of arrival for an entire physiological cycle. This buffering enables on-line rejection of "bad-beat" cycles and serves the more complex needs of real-time cardiac/ respiratory gating.
• the SD RMW PCI cards provide a very high rate of histogramming.
• the present invention is further applicable to rapid dynamic, dynamic-gated, continuous bed motion, time-of-flight (TOF), gated-TOF, and correction for patient motion, and all in an on-line manner while the patient remains in the tomograph.
• TOF time-of-flight
• the present invention further supports both list-mode-only data acquisition as well as for rapid replay in post-acquisition histogramming of previously collected list-mode data.
• the offset-control tag- packet mechanism is an effective means to instantly direct bin-address activity into any part of the RMW daisy chain via minimal PCI interaction.
• the component architecture internal to each SD RMW PCI card includes a single field programmable gate array (FPGA) in communication with RAM and with the input/ output (I/O) flow, including I/O via at least one Fibre Channel (FC) and a PCI interface.
• FPGA field programmable gate array
• Each of a plurality of DRAM modules is independently in communication with the FPGA to permit independent and simultaneous direct memory access (DMA) to each bank, thus optimizing throughput.
• the FPGA is in communication with each local Fibre Channel port.
• Each port consists of a transceiver, typically fiber' optic, and a serializer/ deserializer (SERDES) chip.
• SERDES serializer/ deserializer
• Also provided in communication with the FPGA is a first in, first out (FIFO) memory chip.
• the FPGA architecture includes independent DRAM Controllers for actively accessing dedicated DRAM modules for read-modify-write (RMW) transactions.
• RMW transactions take two forms. For +/- unity RMW, the transactions involve adding unity to or subtracting unity from individual bins in the DRAM memory.
• These Unity RMW bins are 2's complement integer values stored as either 8-bit or 16-bit.
• Weighted RMW the transactions involve adding a correction factor to or . subtracting a correction factor from individual bins in the DRAM memory.
• These Weighted RMW bins are 2's complement "block floating" values and. are typically stored as 32-bit only.
• the DRAM bin- address space is quad-interleaved with the assistance of an FPGA-resident Interleave Router.
• This Router supports quad-interleaving by distributing, according to address-value content, bin-address data packets to each of the four FPGA-resident FIFO blocks and their associated DRAM modules.
• These FPGA-resident FIFO blocks are provided to greatly reduce the chance of packet pile-up and loss.
• FPGA-resident bin-address offset control is applied to assist in real-time control of multiple-frame dynamic or multiple-phase-segment gated studies.
• the FPGA After histogramming is completed for a DRAM-resident projection space and as the projection-space data is read, the FPGA automatically reorders the internal quad-interleaved organization during DMA transfer out to PCI bus, eliminating the need for subsequent user reassembly of the final projection data set.
• the FPGA and DIMMs are applied without interleaving or histogramming.
• the Gating SD PCI card is provided primarily to buffer packets in the order of arrival into one of two DRAM banks. While one bank . is loading with data packets arriving in real time via FC input port, the other bank is unloading via FC output port. Data packet output is controlled by operating system-resident application code which drives autonomous FPGA-reside ⁇ t DMA controllers.
• the PET packet stream arriving at the Gating Buffer is interspersed with both LOR (event) packets and other non-event (tag) packets.
• Tag packet content includes elapsed milliseconds, cardiac R-wave, and respiratory phase data.
• a PET normalization correction matrix which is an array of scalar values which reflect the reciprocal of the varied gamma detection efficiencies as pre-determined for each detector pair.
• a PET normalization correction matrix which is an array of scalar values which reflect the reciprocal of the varied gamma detection efficiencies as pre-determined for each detector pair.
• each respective scalar correction value in block-floating format, is extracted from the local DRAM content.
• the index into the local DRAM is formed by the FPGA from the detector-pair packet content, namely, the crystal-pair indexes.
• An extracted correction factor value is loaded, ie., inserted, into a designated field within the detector-pair packet.
• This modified packet with correction value which is potentially larger than its original size, is then transmitted for further processing via the out-going FC port.
• each DRAM-resident RMW bin is a 32-bit 2's complement block-floating value.
• the event packets input via the FC port are intermixed with conventional tag packets. These event (non-tag) packets are called weighted bin-address event packets.
• These weighted bin-address event packets contain not only the traditional Prompt/ Delayed (P/D) bit but also a bin-address field and the correction-value field. A correction value is added/ subtracted to/from the respective bin in DRAM memory, depending on the P/D bit.
• the bin-address value is applied as a quad-byte index into local DRAM. Because both the correction value and the bin content are treated as block floating, the FPGA performs only signed-integer arithmetic for the RMW memory cycles.
• FIG. 1 is a schematic illustration of a PC-based acquisition architecture incorporating four Smart DRAM (SD) peripheral component interconnect (PCI) cards incorporating various features of the present invention, one SD PCI card being shown for on-line gating, i.e., SD Gating Buffer, and three SD PCI cards being shown for on-line unity histogramming, i e., SD Unity RMW;
• SD Smart DRAM
• PCI peripheral component interconnect
• FIG. 2 is a schematic illustration of the component architecture internal to the Smart DRAM PCI card incorporated in the architecture illustrated in FIG. 1;
• FIG. 3 is a schematic illustration of an FPGA architecture as applied to histogramming
• FIG. 4 is a schematic illustration of the FPGA architecture as applied to the Gating Buffer function.
• FIG. 5 is a schematic illustration of a PC-based acquisition architecture . incorporating five Smart DRAM (SD) peripheral component interconnect (PCI) cards incorporating various features of the present invention, one SD PCI card being shown for on-line normalization, ie., SD CF LUT, one SD card being shown for on- line gating, i.e., SD Gating Buffer, and three SD PCI cards shown for on-line weighted Wstogramming, ie., SD Weighted RMW.
• SD Smart DRAM
• PCI peripheral component interconnect
• a device for improved on-line histogramming of data acquired in a Positron Emission Tomography (PET) scan is disclosed.
• the device of the present invention permits very fast read-modify- write (RMW, +/- unity and weighted) histogramming memory cycles, and permits very large amounts of RMW memory to be effectively controlled from a single PC motherboard running a single operating system (OS).
• OS operating system
• FIG. 1 is a schematic illustration of a PC-based acquisition architecture incorporating four Smart DRAM (SD) peripheral component interconnect (PCI) cards of the present invention, illustrated generally at 10.
• SD Smart DRAM
• PCI peripheral component interconnect
• the SD PCI card 10 is applied in two ways.
• One of the four SD PCI cards 10A is used as a Gating Buffer, while the remaining three SD PCI cards 10B are used for unity RMW histograrnming.
• This embodiment principally supports on-line gated PET data acquisition. Histogramming rates in the range from 14 to 19 M events/ sec are supported. It will be understood, however, that other rates outside this range may be accomplished using architectures within the scope of the present invention.
• With an extendible daisy-chain very large projection data sets are supportable, for example, 10 12 bins.
• the Gating Buffer card 10A alternately stores an arriving PET data
• the extendible daisy- chain of SD RMW PCI cards 10B supports large memory banks, limited to ⁇ 10* 2 bins (1-4 Terabytes) across potentially hundreds of SD RMW PCI cards 10B in the chain, as required. Under a single PC, a multiple PCI Expansion chassis 16 is provided such that a large number of SD RMW PCI cards 10B are supported.
• the SD RMW PCI design effectively solves the problem of limited address space found in current PC systems.
• a moveable 4 Mbyte PCI DMA window is defined for fast and effective DMA transfers into the PC motherboard of the huge, ie., not conventionally addressable, sets of projection data.
• flow control signaling (not fully illustrated) may be sent upstream between the full- duplex FC links 18.
• FIG. 1 While the architecture in FIG. 1 is significant for on-line gated studies, it is also effective for many other, even more demanding on-line acquisition types. These include, but are not limited to, rapid dynamic, dynamic-gated, continuous bed motion, time-of-flight (TOF), gated-TOF, and correction for patient motion.
• the present invention further supports both list-mode-only data acquisition as well as for rapid replay in post- acquisition histogramming of previously collected list-mode data.
• frame-offset tag packets are used.
• these offset- control tag packets are input to the Gating Buffer card 10A under control of PC- OS-based application software.
• the offset tag packets are intermixed with bin- address event packets. These packets are all output from the Gating Buffer FC port for reception by the down-stream SD RMW PCI cards 10B.
• the bin-offset values in these tag packets are received and used by the FPGA 12B on each of the down-stream SD RMW PCI cards 10B to instantly direct histogramming into the designated projection frame, ie., some portion of the memory space across all the histogramming SD RMW PCI cards 10.
• the use of the Fibre Channel daisy chain to distribute the frame-offset value to all SD RMW PCI cards 10 minimizes the application code interaction with PCI-accessed FPGA-resident control registers, ie., one frame-offset register access into the SD Gating Buffer card with FC daisy chain distribution of the value avoids the need for multiple and more time-critical PCI registers accessed across multiple SD RMW PCI cards 10.
• the FPGA 10B on each of SD RMW PCI cards 10B in the chain is directed from the PC operating system via FPGA-resident PCI-loaded registers to respond to only a designated card-size (for example, 4 Gbyte) portion of the available 40-bit projection-data bin space. This bin space is spread across all the SD RMW PCI cards 10B in the chain and is limited to 40-bit indexing.
• the offset-control tag-packet mechanism is an effective means to instantly direct bin-address activity into any part of the RMW daisy chain via minimal PCI interaction.
• FIG. 2 is a schematic illustration of the component architecture internal to each SD RMW PCI card 10 of the present invention.
• Each box in the diagram represents a chip or component on the card 10.
• a single field programmable gate array (FPGA) 12A, 12B is in communication with the RAM 14 and with the input/ output (I/O) flow, including I/O via at least one Fibre Channel (FC) 18 and a PCI interface 20.
• FPGA field programmable gate array
• FC Fibre Channel
• This architecture achieves maximum flexibility and permits a single board design to service multiple applications.
• four DRAM dual in-line memory modules (DIMMs) 14 are each independently in communication with the FPGA 12A, 12B to permit independent and simultaneous direct memory access (DMA) to each bank, thus optimizing throughput.
• DIMMs dual in-line memory modules
• the FPGA 12A, 12B is in communication with each Fibre Channel port 18 via a transceiver 22 and a serializer/ deserializer (SERDES) chip 24. Also provided in communication with the FPGA 12A 12B is a first in, first out (FIFO) memory chip 26.
• SERDES serializer/ deserializer
• FIG. 3 is a schematic illustration of the FPGA architecture as applied to histogramming. This embodiment assists in accomplishing a primary method for achieving fast histograrnming throughput through the use of quad-interleaving.
• each independent DRAM Controller 26 is actively accessing its own DRAM DIMM 14 for read-modify-write (RMW, +/- Unity and Weighted) transactions into either 8-bit or 16-bit 2's-complement integer bins or 32-bit 2's- complement block-floating bins.
• RMW read-modify-write
• the DRAM address space is "quad-interleaved" with a 4 M byte “granularity.”
• An Interleave Router 28 distributes the first four data packets A-B-C-D in order between DIMM1, DIMM2, DIMM3 and DIMM4.
• This interleaving helps ensure that the normal distribution of LOR-to-bin mapping across the projection data space will load all four DRAM controllers 26 with nearly equal RMW rates, largely independent of the distribution of activity in the PET FOV.
• Typical whole-body PET projection data spaces are much larger than 4 M bytes.
• the FPGA 12B automatically "re-orders" the internal quad-interleaved 4 M byte organization upon DMA transfer of projection data out onto the PCI bus, thereby eliminating any user re-assembly burden.
• the set-of-4 "FIFO 8 Deep" blocks 30 in FIG. 3 serve to greatly reduce the chance of packet pile-up and loss.
• the SD RMW card 10B design also supports control methods, ie., frame-offset tag packet, to quickly offset the arriving bin-address into most any arbitrary portion of the local DRAM space and even across multiple cards in the daisy chain.
• This bin-address offset control is applied in the "Bin Address Offset" block 32 of FIG. 3 and is critically important for realtime control of multiple-frame dynamic or multiple-phase-segment gated studies.
• the SD RMW PCI card 10B of the present invention has demonstrated RMW (+/- unity) histogramming of real PET data at sustained rates in excess of 14 M events/sec.
• RMW (+/- unity histogramming of real PET data at sustained rates in excess of 14 M events/sec.
• over 14 billion (10 ⁇ ) PET 32- bit bin-address list-mode packets were successfully replayed for histogramming in 17 minutes. In this case histogramming speed was primarily limited by the PC disk system.
• Early observations show that data transfers of DRAM contents from the SD RMW PCI card via PCI bus to PC-motherboard DRAM . are roughly 117 M bytes/sec for 32/33 PCI slot installations and 146 M bytes/sec for 64/66 PCI slot installation.
• FIG. 4 is a schematic illustration of the FPGA 12A architecture as applied to the Gating Buffer function.
• the FPGA 12A and DIMMs 14 are applied without interleaving or histogramming.
• the Gating SD RMW PCI card 10A is provided primarily to store, or buffer, packets in the order of arrival into one of two DRAM 14 banks. While one bank is loading with data packets arriving in real time via FC input port 18, the other bankis typically unloading via FC output port. Data packet output is controlled by operating system-resident application code which drives autonomous FPGA-resident DMA controllers.
• the PET packet stream arriving at the Gating Buffer is interspersed with both LOR (event) packets and other non-event (tag) packets.
• Tag packet content includes elapsed milliseconds, cardiac R-wave, and respiratory phase data. Because the buffered event-and-tag-packet data stream is temporarily stored in local DRAM, more time is available for operating system control of how this data is handled. For example, packets may be directed for down-stream histograrnming into specific frames. In one embodiment, the LOR bin-address packet data is histogrammed into different projection-data frames depending on the cardiac phase. This phase may be determined by the elapsed-time tag packet content found in the Gating Buffer relative to any cardiac R-wave tag packets present. The control of which phase-segment frame is targeted for each designated section of the event stream is provided by the afore-mentioned bin-address offset tag control.
• FIG 5. is a schematic illustration of a second PC-based acquisition architecture incorporating five SD PCI cards 10 of the present invention.
• the SD PCI card 10 is applied in three ways.
• One of the five SD PCI cards 10 is used as. a normalization (correction factor, CF) look-up table (LUT).
• Another SD PCI card ie., SD Gating Buffer, is used in a manner similar to that in FIG 1., with the exception that the event packets received via the Fibre Channel, processed, and then retransmitted via the Fibre Channel, are each 64-bit weighted bin-address packets.
• each event packet contains an extra field, the 16-bit CF value as added by the SD CF LUT PCI card.
• the remaining 3 SD PCI cards are all configured to support weighted histogramming, namely, SD Weighted RMW, with each event packet transmitted down the Fibre Channel daisy chain, being of the type, 64-bit weighted bin-address.
• the SD CF LUT PCI card 10 of the present invention is useful for on-line event-by-event normalization.
• On-line normalization processing is useful in supporting, for example, continuous bed motion and correction of inadvertent patient motion.
• Event-by-event normalization includes at ⁇ least the steps of correction value look-up in look up tables (LUTs) resident in . memory and weighted histogramming.
• LUTs look up tables
• the local DRAM is loaded prior to the start of the acquisition with a PET normalization correction matrix, which is an array of scalar values which reflect the reciprocal of the varied gamma detection efficiencies as pre-determined for each detector pair.
• a PET normalization correction matrix which is an array of scalar values which reflect the reciprocal of the varied gamma detection efficiencies as pre-determined for each detector pair.
• each respective 16-bit scalar correction value in block-floating format, is extracted from the local DRAM content.
• the index into the local DRAM is formed by the FPGA from the detector- pair packet content, namely, the crystal-pair indexes.
• Each extracted value is loaded into a designated field within each detector-pair packet.
• This modified packet with correction value which is potentially larger than its original size, is then transmitted for further processing via the out-going 'FC port.
• the FC output is, in one embodiment, connected to a custom PCI card for next-stage on-line processing such as nearest-neighbor rebinning such as in the PETLINKtm DMA Rebinner (PDR) card illustrated in both FIGS. 1 and 5.
• PDR PETLINKtm DMA Rebinner
• the SD RMW PCI card 10 performs histogramming in much the same mariner as previously described.
• the daisy-chain of SD RMW PCI cards are FPGA-configured for weighted histograrnming.
• each DRAM-resident RMW bin is a 32-bit 2's block-floating complement value.
• the event packets input via the FC port are intermixed with conventional tag. packets. These event packets are called 64-bit weighted bin-address event packets.
• the new packets contain not only the traditional Prompt/ Delayed (P/D) bit but also a bin-address field and the correction-value field.
• the more traditional PET histogramming without the complexity of weighted histogramming, merely employs +/- unity RMW cycles into . 8-bit or 16-bit bins in memory.
• the . correction value is added/ subtracted to/from the respective bin in DRAM memory, depending on the P/D bit.
• the bin-address value is applied as a quad-byte index into local DRAM. Because both the correction value and the bin content are treated as block floating, the FPGA performs only signed- integer arithmetic for the RMW memory cycles.
• the result of on-line weighted istogramming is that all projection-data sets resident in local DRAM are inherently corrected for pre-normalized detector efficiency variations during the entirety of the acquisition.
• the block-floating format has an implied decimal point between bits 10 & 11. This implied decimal location applies uniformly to both a 16-bit correction value and a 32-bit bin value.
• This assumption provides for normalization values - for example, an unsigned block-floating 16-bit correction value - to range from zero to values as high as 31.00 (5 bits to left of decimal), with a precision limit of +/- 0.00024 (11 bits to right of decimal).
• a zero correction value may be used to effectively force a bad LOR to be ignored, i.e., a case where a pre- measured correction value is judged too extreme to be desirable.
• the signed block-floating 32-bit bin values range as +/- 1048575 (20-bits plus sign bit to left of decimal).
• the 32-bit bin precision limit is the same (+/- 0.00024) as the prior example.
• Other correction factors supported by this specific choice for the location of the implied decimal include: zero, 0.04883, 0.04916, 1.0, 1.0005, 30.0, 30.0005, etc.
• Other trade-offs between range and precision, ie., by selecting an alternate location for the implied decimal point are within the scope of the present invention and may also find application. In this context, the chosen location for the implied decimal point is not determined or limited by the FPGA configuration.
• the device includes ⁇ a plurality of Smart DRAM peripheral component interconnect (SD RMW PCI) cards adapted to permit very fast read-modify- write (RMW, +/- Unity and Weighted) histogramming memory cycles, and to permit large amounts of RMW memory to be effectively controlled from a single PC motherboard running a single operating system (OS).
• SD RMW PCI cards are individually adapted to be used either as a Gating Buffer, for normalization look up, or for histogramming.
• the present invention supports on-line gated PET data acquisition.

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• 2005
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