WO2005107091A1

WO2005107091A1 - Method for the rapid synchronisation of a device for receiving scrambled data, using an optimised calculation of a synchronisation value

Info

Publication number: WO2005107091A1
Application number: PCT/FR2005/000580
Authority: WO
Inventors: Maarten De Vries; Samir Dechicha
Original assignee: Wavecom
Priority date: 2004-03-31
Filing date: 2005-03-10
Publication date: 2005-11-10
Also published as: FR2868635B1; US8270551B2; US20090010431A1; FR2868635A1; EP1730848A1

Abstract

The invention relates to a method of synchronising a device for receiving scrambled data, using at least one periodic scrambling sequence which is divided into K time intervals (20, 22), each interval comprising N bit periods (21) known as symbols. In particular, one such method comprises a step consisting in calculating a synchronisation value of at least one polynomial that generates the aforementioned scrambling sequence within a pre-determined synchronisation time interval and synchronisation bit period. The invention is advantageously characterised in that, during the calculation step, the sequence is progressed through at increments of at least one time interval and at least one bit period, using a matrix calculation of the synchronisation value.

Description

Field of the invention The present invention relates to the minimization of the synchronization time required for a receiver, content in particular. Method of rapid synchronization of a device for receiving scrambled data by means of an optimized calculation of a synchronization value in a terminal of a mobile telephony system of the UMTS type (for "Universal Mobile Telecommunication System" in English, or universal mobile telecommunication system in French), to recover synchronism, between the sequences it produces and the sequences transmitted by the base station. Indeed, any message received by a mobile terminal is scrambled on transmission and must therefore be descrambled by means of the same sequence of sequences as that initially generated by the transmitting base station. In addition, this descrambling must be carried out in synchronism with the scrambling carried out by the base station. In the context of WCDMA, for "Wideband Code-Division

Multiple-Access "in English (or" Multiple broadband code division access "in French), that is to say for one of the essential technologies necessary for the implementation of the new generation (3 G) of the cellular system, all the data received is broadcast and scrambled in the form of ONSF scrambling sequences (for “Orthogonal Variable Spreading Factor” in English or “Facteur de Diffusion Variable Orthogonal” in French) and scrambling sequences (“scrambling sequences” " in English). Each OVSF sequence is periodic at the level of the symbols (or bit period) which compose it, just as each scrambling sequence is also periodic at the time intervals (frame) which segment it. To recover the message transmitted in the form of a signal at the level of the receiving terminal, it is therefore necessary to recover the synchronism, between the sequences produced by the receiving terminal and the OVSF and jamming sequences, transmitted by the base station. If this synchronism is not achieved, the received signal is reduced to noise. All the aforementioned synchronization constraints are all the more present at the level of mobile telecommunications terminals of the UMTS type, and more precisely at the level of the following two essential elements included in such a mobile terminal: - the RAKE receiver, or “Rake receiver” in English, which includes among other things the technical body responsible for controlling the synchronization, and in particular that relating to the CPICH pilot channel (for "Common Pilot Indicator Channel", in English or "Common pilot indicator channel" in French) ; - the cell detector, better known under the name of “cell searcher” in English, which operates according to at least the following three main steps: o step 1: search for the primary channel or “Primary Synchronization Channel” (P-SCH) in English; o step 2: synchronization carried out on the secondary channel, or “Secondary Synchronization Channel” (S-SCH) in English; o step 3: correlation measurement on the common pilot indicator channel or CPICH. Here we consider the assumption that the timing of the received signal is known, which means that the start of the scrambling sequence is known. This information is in particular available thanks to the "cell searcher" which delivers in its operating steps one and two the sequences of synchronization of the frame time intervals ("frame" in English) and of slot for the received signal, completed by the detector multiple paths (or “Multi-path searcher” in English) which delivers phase synchronization for each echo. To demodulate the received signal data, it is therefore necessary to initialize the scrambling code sequences and the OVSF sequences in a predetermined state, at a precise instant. When the scrambling sequence is known, the OVSF sequence to be used is provided by other protocol channels. The problem that arises, however, is how to load the right value and at the right time into the polynomial generating the scrambling sequences. However, the operation of these two elements, "Rake receiver" and "Cell searcher" being relatively greedy in electrical consumption, during the use of the terminal, they are alternately on or off depending on the reception of messages, which requires find the correct synchronization value for the initialization of the generator polynomial, at the right time, each time it is re-lit. However, these successive extinctions and re-ignitions imply a significant convergence time to bring back the generator polynomials "x" and "y" in the state they occupied at the moment of extinction, which confirms the interest of '' provide an effective solution to the above problems. 2. Solutions of the Prior Art Among the solutions of the state of the art known to date, the most commonly used to try to optimize the convergence time to bring the polynomials "x" and "y" into a state specific determined is the "slewing" technique. This technique is based on the fact that the receiver of a mobile telecommunications terminal comprises two periodic generators of bit sequences, identical to those of the base station. Thus, this terminal must first load the interference value into the generator of the phase path, then recover the synchronism ("slewing" in English). Two cases can then arise depending on the value of the known time difference between the sequences it produces and those transmitted by the base station: - if it is late, that is to say if the sequences leaving its generators precede the corresponding sequences of the scrambled message in the sequence of sequences, the receiver will have to clock the two generators at a frequency higher than the reception frequency (equal to 3.84 Mchips / s) of the sequence to catch up with the correct phase; - if it is ahead, that is to say if the sequences leaving its generators appear after the corresponding sequences of the scrambled message in the following sequences, the receiver must freeze the two generators (no clock signal), until it has reached the correct phase. The “slewing” technique therefore amounts to accelerating or slowing down (see freeze) the generator polynomial to reach the desired state corresponding to an alignment of the data received. Naturally, during the synchronization delay necessary for the terminal to recover the synchronism, this terminal cannot descramble the received message, so that it loses information and it spends energy unnecessarily. It is therefore important to shorten as much as possible this synchronization delay which depends on the processing time imposed by the technique of

"Slewing", which is generally of the order of a time interval of 2560 bits. Periodic generators of very long period are generally employed to produce pseudo-random bit sequences. Such a generator is generally produced by means of a linear feedback shift register (“Linear Feedback Shift Register”) clocked at the rate of a clock signal. The bits of the generated sequences correspond to the outputs of the flip-flops of the register. A typical application of the periodic generator is scrambling. To fix the ideas, we can refer to the transmission mode adopted in the UMTS mobile communications system (for "Universal Mobile Telecommunication System" in English). At a base station, a message to be transmitted is modulated on two channels, the phase I channel and the quadrature channel Q. Each of the I and Q channels is scrambled by means of a system of two generators (" x "and" y "), except that the state of generator X is offset from the state of Y by an interference value characterizing the base station. This scrambling code corresponds to a predetermined number of strokes clock. When the terminal is late, it is possible to play on the frequency of the clock signal, which then makes it possible to perform clock jumps and thus make up for the delay observed. Consequently, each time the demodulator is turned on, it is rotated at no load until it converges, before starting to demodulate. It then becomes necessary, either to freeze, or to accelerate the pseudo-random generators to compensate for their advance or their delay compared to the frame of the received signal and thus allow their positioning on the state which they occupied at the time of the extinction. . An important problem associated with this operating mode however concerns the excessively high convergence time, which generally borders on the duration of a synchronization time interval (frame). However, it currently seems impossible to do without such pseudo-random generators to initialize the registers at the correct values and thus recover the synchronism between the bit sequences produced by the receiver terminal demodulator and the sequences transmitted by the base station. A second known solution of the prior art for reducing this waiting time consists in making a jump of a predetermined number of sequences (generally called "immediate shift") to the periodic generators. However, this solution, known as “by memorizing masks”, significantly increases the complexity of the generators and the cost price of such devices, not necessarily justified for a mobile telephone terminal of the UMTS type. 3. Disadvantages of the Prior Art A first disadvantage of these techniques of the prior art is that they impose a synchronization delay which is sometimes significant but necessary for the terminal to recover the synchronism, this terminal not being able to directly descramble the received message, resulting in possible loss of information and unnecessary energy expenditure. A second major drawback associated with these prior art techniques is that they significantly increase the complexity of the generators to be implemented, which most of the time use hardware solutions (or “hardware” in English), which can oppose the constraints of miniaturization of mobile radiocommunication terminals and of the components that they integrate. 4. Objectives of the invention The object of the invention is in particular to overcome these drawbacks of the prior art. The present invention aims to overcome these drawbacks of the state of the art. More specifically, a first objective of the invention is to provide a generator making it possible to obtain very quickly, almost instantaneously see the desired synchronization or convergence value at the level of the generator polynomial, while guaranteeing very low consumption, during the slewing process at the Rake UMTS receiver. A second objective of the invention is to allow the elimination of the delay, sometimes significant, usually encountered in the processing of step 3 of the UMTS "Cell Searcher" and thus eliminate any risk of loss of a frame. Another objective of the invention is to provide such a generator, which is of reduced complexity, in terms of number of logic gates implemented in particular, compared to known techniques, and / or in terms of possibilities of using treatments. algorithmic and / or software. In other words, the invention aims to present an alternative of much less complexity to reduce the waiting time, in particular when the generators are late and thus favor the convergence of the pseudo-random generators in a given state d a predetermined position to be reached, which corresponds to the association of predetermined synchronization time intervals and of a synchronization symbol. An additional objective of the invention is therefore to propose a technique which can be applied both to a Rake UMTS receiver to give it instant synchronization capacity, and to the optimization of step 3 of operation of the “Cell searcher”, so that there is no longer any loss of time intervals during the correlation processing on the CPICH channel, nor any possible loss of frame. 5. Essential characteristics of the invention These objectives, as well as others which will appear subsequently, are achieved using a method of synchronization of a device for receiving scrambled data by means of at least one sequence. periodic interference organized in K time intervals each comprising N bit periods called symbols. Such a method comprises a step of calculating a synchronization value of at least one pseudo-random generator of the scrambling sequence, in a synchronization time interval and in a period of predetermined synchronization bits. It allows in particular and advantageously, during the calculation step, to progress in the scrambling sequence by hopping of at least one time interval and at least one bit period, by implementing a matrix calculation of the synchronization value. Preferably, the matrix calculation implements a multiplication of an initialization value of the pseudo-random generator by at least one predetermined passage matrix. This technique is based on the fact that the pseudo-random generators of the receiver of a mobile telecommunications terminal, and in particular of the UMTS type, are periodic and composed of bit sequences, identical to those of the base station. Aiiisi, this terminal must first load the interference value into the generator "x", before it can recover synchronism. Advantageously, the method according to the invention makes it possible to progress in the sequence of bits by hopping at least one time interval, by calculating the value of the generator polynomial at the boundaries of the intervals, until the synchronization time interval is determined. . Also advantageously, the value of the pseudo-random generator at the boundaries of the time intervals is determined, from the value initialization, by successive multiplications by a time interval passage matrix. Preferably, within the synchronization time interval, one advances in the sequence by hopping of at least one period of N bits, by calculating the value of the pseudo-random generator at the borders of the bit periods, until obtaining the value of the synchronization bit period. Advantageously, the value of the pseudo-random generator at the boundaries of the bit periods is determined, from the value of the generator at the boundaries of the intervals, by successive multiplications by a bit period transition matrix. The advantage of such an approach advantageously lies in its ability to promote the very rapid convergence of the pseudo-random generator (s) towards the synchronization value. It is indeed a question of optimizing the convergence time by first performing a first cutting of the scrambling sequences by time intervals and a second cutting of these time intervals into bit or symbol periods, then carrying out the following steps leading to the synchronization value: - as many jumps of time intervals are made as necessary until being positioned on the predetermined time interval, component of the synchronization value; - then as many hops of bit periods (or symbols) are made as necessary, so as to reach or position on the symbol value.

Thanks to this approach, it then becomes possible to switch the demodulator on and off by eliminating any risk of electrical overconsumption, any risk of loss of frame, or even any constraint linked to the convergence time usually encountered with the solutions of prior art. Frame loss is reduced to a maximum of two CPICH symbols. Preferably, the data is scrambled according to at least two scrambling sequences X and Y, and the initialization value for the sequence Y is fixed. The initialization value for the sequence X is characteristic of a device for transmitting scrambled data.

The scrambling sequences X and Y are respectively obtained from the generator polynomials "x" and "y". Advantageously, the periodic scrambling sequence being organized in K time intervals each comprising N bit periods, the symbol passing matrix for the sequence X is the matrix (M _χ ) ^N and the interval passing matrix of time for said sequence X is the matrix M. Preferably, the periodic jamming sequence being organized in

K time intervals each comprising N bit periods, the symbol passing matrix for the sequence Y is the matrix My and in that the value of the generator polynomial at the boundaries of the intervals for the sequence Y is determined from a table vectors associated with the polynomial generator of the sequence Y. Also, advantageously, to reach the phase vector of index (β + μ) from the phase vector of index β of the scrambling sequence by successive jumps of value i , at least the following successive steps of: decomposition of the index value μ are carried out in the form of a sum of the quotient and of the remainder r of the Euclidean division of μ by i, the quotient then being expressed in the form a product of an integer j with the jump value i; raising to full power j the time interval passing matrix of sequence X, the time interval comprising ranges of i bit periods; multiplication of the phase vector of index β by the time interval passage matrix (M ') ^] , so as to obtain the value of the phase vector of index (β + ixj), then; multiplication of the phase vector of index (β + ixj) by the matrix of passage of bit periods (M _x ^r ), so as to position on the correct bit period value; The succession of these different stages advantageously makes it possible to limit to a value of (j + r) the number of clock strokes to be applied in order to reach the desired phase vector, which is also particularly advantageous in the context of an application to "Accelerated slewing". Preferably, the successive jumps of bit period have a value expressed in the form of a power of two, these bits being able to take only two values: zero or one. The Euclidean division of μ by i then becomes very simple to perform. Preferably, the synchronization method implements the UMTS standard ("Universal Mobile Telecommunications System" for "Universal mobile telecommunications system"), the bit periods then being CPICH symbols (for "Common Pilot Indicator Channel", in English or "Common Pilot Indicator Channel" in French). Advantageously, the reception device comprises at least one RAKE receiver and cell search means of the Cell Searcher type. Within the framework of a UMTS network, the Rake receiver comprises the organ of the mobile terminal responsible for the servo relating to synchronization. Upon awakening, it receives in particular a starting or initialization point, from which it performs the servo-control of the schedule for receiving the data received. The Rake receiver therefore has a dual function, a first one for synchronization control relative to the CPICH pilot channel, and a second one for synchronizing the data received.

The cell searcher of a UMTS mobile terminal, when switched on, performs the following three steps: step 1: search for the strongest transmitting station; step 2: determination of the primary channel or P-SCH (for “Primary Synchronization Channel” in English); step 3: synchronization on the secondary channel or S-SCH (for “Secondary Synchronization Channel” in English). It is from these last two steps in particular that the Cell Searcher is capable of delivering the coordinates for the start of the frame and slot time interval corresponding to the strongest transmitting station. Advantageously, the bit periods being CPICH symbols, each of the time intervals comprises K = 10 periods of N = 256 bits, so as to obtain a finer granularity. Thus, and advantageously, the bit period passing matrix for the sequence X is the matrix:

which can still be written in the form X0, n + 1 - X _{3 n} ^Λ X _{4> n} ^Λ X _{7 n} ^Λ X _{S n} X17, n + 1 - X _{2 n} ^Λ X _{3 n} ^Λ X _{6> n} ^Λ X _{7 n} ^Λ X _{9 n} ^Λ X _{10 n} ^Λ X _{13 n} ^Λ X _{14 n}

Also advantageously, the time interval passage matrix for the sequence X is the matrix:

which can still be written in the form: xo, n + ι = x ^Λ x _{2) n} - x _{3> n} - x _4; „- x _{5> n} - x _{6> n} - x ^ - x _n - x _{10> n} - x _12; „- x _{13> n} - x _{16> n} - X _n to ^X17 > ^{n + 1} = ^X 2, n ^{Λ X} 3, n ^{Λ X} 6, n ^{Λ X} 8, n ^{Λ X} 10, n ^{Λ X} ll, n ^{Λ X} 12, n ^{Λ X} 13, n said bit period passing matrix for said sequence Y then being the matrix: X17, n + 1 ^Λ Xl0, n ^Λ Xl3, n ^Λ Xl4, n

which can still be written in the form: X0, n + 1 = X _{0> n} ^Λ X _{1> n} - X _2jn - X _4jn - X _6; „- X _{7> n} - ₈₎ „ - X _14; „- X _{16> n} - X _{17> n} to ^X17 ' ^{n + 1} = ^X 0, n ^Λ Xl, n ^Λ X4, n ^Λ X _7j n ^{Λ X} 9, n ^{Λ X} ll, n ^{Λ X} 12, n ^{Λ X} 13, n ^{Λ X} 14, n ^{Λ X} l _5j n ^{Λ X} 17, „.

The invention also preferably relates to a device for receiving scrambled data by means of at least one periodic scrambling sequence, and organized in time intervals each comprising at least one bit period called symbol. Such a device according to the invention thus advantageously comprises means for synchronizing the device themselves comprising means for calculating a synchronization value of at least one polynomial generating the scrambling sequence, by progression in the sequence, by jumps of at least one bit period. The calculation means preferably implement a matrix calculation of the synchronization value. Advantageously, the calculation means comprise a first register comprising flip-flops outputting the bits of the sequence making it possible to obtain the synchronization value. Preferably, the input of each flip-flop is connected to the output of a multiplexer controlled by a selection signal (SEL). Also preferably, when the selection signal selects the input at the bottom of the multiplexer, the passage matrix M _x is applied and when the selection signal selects the input at the top of the multiplexer, the passage matrix M is applied. Advantageously, the reception device according to the invention applies to fields belonging to the group comprising: the optimization of step 3 of the UMTS cell searcher; speeding up the slewing process of a UMTS rake receiver; optimizing the operation of a UMTS equalizer; - the pre-calculation of the initial value (or “seed” in English) of a linear feedback shift register (or “LFSR: Linear Feedback Shift Register” in English). The application of the methods and device according to the invention is detailed below. The invention also relates to a mobile radiocommunication terminal comprising means for receiving scrambled data by means of at least one periodic scrambling sequence, and organized in time intervals each comprising at least one bit period called symbol. Such a terminal thus preferably comprises means for synchronizing said reception means comprising means for calculating a synchronization value of at least one polynomial generating the scrambling sequence, by progression in the sequence by hopping at least minus one bit period, the calculation means implementing a matrix calculation of the synchronization value. Thus, the invention is based on a completely new and inventive approach for almost direct determination of the synchronization value ("scrambling" code) - given by a predetermined synchronization time interval and a synchronization symbol - of at least minus a polynomial generating a scrambling sequence, synchronization value, and with a minimum of processing. The invention applies in particular and not exclusively both to the synchronization of a UMTS “Rake” receiver and to the optimization of step three of processing of the UMTS “cell searcher”, both contained in a mobile terminal. of the same type. 6. List of Figures Other characteristics and advantages of the invention will appear more clearly on reading the following description of a preferred embodiment, given by way of simple illustrative and nonlimiting example, and of the appended drawings, among which: - Figure 1 shows a block diagram of the data propagation and scrambling operation; FIG. 2 illustrates the general implementation mechanism of “Turbo scrambling” (in English) or “scrambling turbo” in French, according to the invention; - Figure 3 shows a linear feedback shift register (or "LFSR: Linear Feedback Shift Register" in English) simple to 7 states; FIG. 4 illustrates the modifications made to the LFSR of FIG. 3 to accelerate the traversal in the sequence of its possible successive states; FIG. 5 gives an example of an optimized sequence allowing a faster browsing of the states of the sequence of the LFSR of FIG. 3, following the modifications made in FIG. 4; FIG. 6 presents an example of modification made on an LFSR-X downlink descrambler making it possible to perform jumps of four states; - Figure 7 gives an example of hardware modification made on an LFSR-Y descrambler to be able to make jumps of four states; FIG. 8 gives an illustration of an LFSR-X defined in the 3G TS25.213 standard with eighteen flip-flops D all clocked by the same clock; FIG. 9 illustrates the results of the application of the mechanism according to the invention for the “accelerated slewing”. These different figures are described in detail in the remainder of this document, as a description support for the various embodiments and applications proposed.

7. Description of an embodiment of the invention 7.1 General In this section, we first present a description of an embodiment of the invention in the form of a matrix approach, applied to the step three ("step 3" in English) of "cell searcher". Other variants are also described in this section in the form of an example of application of the methods and device according to the invention. A more succinct description of a variant of this embodiment will also be proposed, in a second step, in as part of a Rake UMTS receiver. Finally, a description of a possible technique for implementing the invention will also be offered. 7.1 Reminder of the principle of modulation / demodulation of a UMTS signal The code sequence consists of N elements or symbols of the scrambling sequence, called "chips"). It is recalled here that this sequence of the code (consisting of N “chips”) is unique for a given user and that it constitutes the coding key of the received signal; it is kept if the data symbol was 1, inverted otherwise. In addition, if L is the length of the code and each symbol has a duration denoted Tb, then there is a chip every Tb / N seconds and the new modulated signal has a bit rate N times greater than the signal initially sent by l user and will therefore use a frequency band N times wider. It is also recalled that to recover the information contained in the received signal, the receiver must perform the same operation, that is to say generate the same spreading sequence and multiply it with the received signal; the data encoded by this sequence are then restored. The application of such a technique makes it possible in particular to reduce the noise level for the baseband signal: the greater the spread, the more the interference is eliminated. Thus, it can be seen that during decoding, the synchronization consumes a lot of resources at the level of the receiver and imposes a non-negligible processing time during which the received message cannot be processed. 7.2 Description of an embodiment of the invention in the context of its application to the UMTS "Cell Searcher" Here it is a question of optimizing step 3 of operation of the "Cell Searcher" corresponding to the correlation of the CPICH channel . As illustrated in FIG. 1, each transmitted message is received in the form of a scrambling sequence (10) composed of a set (11) of data sequences of the same size (Data ₀ ... Data _N ). Each of the data sequences (11) Data ₀ ... Data _N can be divided into the form of regular time intervals (12) themselves composed of N bit periods (13) (or symbols) S ₀ to S _m . Within the framework of UMTS, each sequence (11) of the scrambling code is made up of 38400 time intervals (12) to which the polynomial generating the scrambling code is applied to obtain the values of the scrambling code (14) X ₀ ... X _N , which then make it possible to recover the good values of the scrambled data transmitted R ₀ ... R ^ (15), by application of the following formula: R _; ≈ Datai XOR S _t XOR X,. Thus, by applying the same scrambling sequences to transmission and to reception, it is possible to avoid recovering noise, which is made possible once we know the initial start time in the received sequence and when we reset the sequence of all symbols received. However, because of the 38,400 time intervals to be managed in the context of UMTS and the Cell Searcher, this is made much more complex and therefore justifies the implementation of the method according to the invention. Thanks to the method according to the invention, also called “Turbo scrambling code” in English, for “turbo-scrambling code” in French, it is indeed possible to load the correct value of the “scrambling code”, at the right time, at level of the pseudo-random generator, and this, with a maximum processing delay not exceeding 4 time intervals. Such a method is based on a matrix calculation making it possible to jump the generator polynomial, directly from a first known position, to a second position also known and characteristic of the synchronization value. This approach is illustrated in FIG. 2 which makes it possible to better visualize the principle according to the invention consisting on the one hand in a succession of jumps over the time intervals until positioning on the desired time interval, then performing as many symbol jumps as necessary in this time interval, until positioning itself on the correct symbol value, the time interval and the symbol thus obtained being representative of the synchronization value desired to initiate descrambling of the sequence of data received. However, the synchronization value given by the association of a time interval reference and a symbol reference, requires in the context of the treatments applied to the “Cell Searcher” and to the UMTS “Rake” receiver, to determine with accuracy the references of the CPICH time intervals and symbols corresponding to this value. This determination is carried out according to the following technique in the context of the Cell Searcher: 1) the generator polynomial is awakened; 2) the cell searcher having its own time counter (or "timer" in English), you never know where it is, especially since the time reference it uses is not the same as shared on the network. Therefore, during this second step, the cell searcher is left to determine the information concerning the synchronization value from its steps 1 (search for the strongest transmitting station and determination of the PCH channel). ) and 2 (determination of synchronization on the SCH) of operation, which is then correlated with its own internal synchronization. Following the above-mentioned steps, step 3 of the cell searcher is launched so as to obtain the measurements on the CPICH channel. The Cell searcher is the first block activated when the mobile terminal is switched on. It therefore retrieves the strongest transmitting station before carrying out its own synchronization. In the context of the invention, to make the cell searcher converge more quickly, instead of rotating the generator polynomial point to point, the scrambling sequence is cut first by time intervals or frames, then by symbol. For the Cell Searcher of the example of FIG. 2 for example, each time interval (20) or frame is divided into ten periods of 256 bits (21). This division results in the form of a frozen passage matrix which we denote by M _x and M _x , which correspond respectively to the symbol passage matrix and time interval passage matrix. The implementation of “turbo scrambling” can therefore be carried out easily using an XOR table for each of the above-mentioned fixed matrixes. The correct desired time interval value is then obtained by performing an iterative calculation from the starting interval (22) denoted “slot0,0”, by multiplication of each time interval by the time interval passage matrix M _x : ^Λ YS / ort, 0 - ^{- i} M ^vΛ X ²⁵⁶⁰ * ^Λ YS / o.0,0 '" ^• ' ^Δ YSto / (i + l), 0 -" ^J M ^M X ²⁵⁶⁰ * ^Λ YSlot { ifiY

Once the correct time interval value has been obtained, the correct symbol value desired to recover the synchronization of the transmitted sequence is calculated from the starting symbol of the correct time interval obtained, by iterative multiplication with the passage matrix of symbols M _x , as follows: _Y _- M ²⁵⁶ * YY - M ²⁵⁶ * y

^Λ Slot (i, symbol \) ~ ^IV1 X ^Λ Slot {i, symbol0) ' ^{• • •} ' ^Λ Slot (i, symbol j + l) ~ ^lrÂ X ^Λ Slot (i, symbol j) - Thanks to this new approach matrix according to the invention, we converge more quickly without having to rotate the generator polynomial time interval by time interval and symbol by symbol on each time interval. For the UMTS Cell Searcher, each of the eighteen possible bits of output from the registers are represented in the form of vectors forming the lines of the passage matrix of the time intervals M _x and symbols M _x for each time interval. The initial value is given by the value of SEED UMTS. Thus, each subsequent vector calculated gives the temporary offset of the received sequence. For example, if there are 10 periods of 256 bits to be traversed per time interval as in the case of the Cell Searcher, we will find the correct value desired by applying the following calculations: X _Shnfi = M _x ^ω * X _S ι _0t o _, o _> ••• ”^ S _{lot (} i _{+ l)} , ₀ ⁼ M _χ X sio _t ( _, i, 0)> PUI S XS _l ot (, i, symbo _l e _l ) ⁼ M- _χ X sio _t ( _, i, sym _b ok _O ) ι • • •> Xsi _o "i _{, symbo} i _ej *" = ^ _x ²⁵⁶ * X _{slota symbol J) t} to find the correct symbol. 7.3 Example of application of the invention to pre-calculation of the initial value of a simple linear feedback shift register with 7 states FIG. 3 shows a very simple linear feedback shift register or LFSR, producing the 7 successive states following given by the flip-flops Q ₀ , Q _γ and Q ₂ , which output the bits of said sequence making it possible to obtain said desired synchronization value. We assume here that the initial state is given by Q ₂ Q _l <2 ₀ = 001:

Let us call this sequence S _j in which following state 7 “011” we loop back to the initial state “001”. In this example, we seek to traverse the sequence S _: more quickly by skipping states and therefore to produce a sequence S ₂ while being able however to return to the sequence S _l at any time. In this configuration of the LFSR, one progresses in the sequence by successive jumps from a first state to a second state, until positioning oneself on the desired state. In the example of Figure 3, the transition from a state (n) to a state (n + 1) is carried out by application of the formula: Q (n + 1) ≈ MQ (n) with M the matrix of passage from a state first state to a second state, M written here:

To achieve this objective, the LFSR is modified to 7 states in FIG. 3 by adding three multiplexers (40, 41, 42) having a common SEL signal which can choose to connect the respective inputs of flip-flops Q ₀ , Q _γ and Q ₂ , or at the top input, or at the bottom input of said multiplexers, as illustrated in FIG. 4. The inputs (43, 44, 45) of each flip-flop Q ₀ , Q _x and Q ₂ are therefore connected respectively to the output of one of the multiplexers (40, 41, 42) and controlled by a selection signal (SEL). Thus, if the signal SEL chooses the inputs at the bottom of the flip-flops, we find ourselves in the configuration of FIG. 3, without optimizing the path of the sequence S _x . Conversely, if the top input is chosen, the new sequence S ₂ is described and characterized by the following 7 new states:

We then observe that the states of S ₂ are obtained by traversing those of S _j by skipping every other state, as illustrated in FIG. 5 which offers a view of the successive sequence in the sequence of the possible successive states of the LFSR, continued to the modifications of FIG. 4. In this FIG. 5, we can see that if we wish to reach the state 7 '= "111", rather than using the LFSR of FIG. 3 in which it is necessary to apply five clock strokes, it is now possible according to the invention to use the architecture of the LFSR of FIG. 4 as follows: 1) SEL = "select the inputs from the top", and reach state 3 '= "110" in two clock strokes, then 2) return to SEL = "select the bottom inputs", then reach state 7' = "111" in a single additional clock stroke; which allows to reach the state 7 '= "111" in just 3 clock ticks. In terms of result, the method according to the invention thus makes it possible to reach a given state in a time twice as short. It is also important to emphasize the fact that the principle exemplified above can be easily generalized to make jumps of greater step, and thus to reach an even faster state, up to three, four, see N times quickly. It is simply a question of then assessing the relationship between the interest of gaining speed and the additional cost of doors and multiplexer to add to the architecture to be implemented. 7.4 Application of the invention to the LFSRs of the descrambler descrambler of a UMTS receiver It is recalled that the two UFS LFSRs “X” and “Y” used in a mobile terminal of the type are called descrambler (or “downlink” in English) UMTS, to descramble the sequences of symbols received. The reader can refer to the 3G-TS 25.213 standard, paragraph 5.2.2, page 21 for more details on these descramblers. 7.4.1 Case of the LFSR-X descrambler In the case of the LFSR-X descrambler, we seek to optimize the number of clock strokes to apply to reach the synchronization value of the LFSR more quickly and with a minimum of jumps between the possible states of the LFSR. The same approach is therefore applied as that exemplified in paragraph 7.3, so as to allow jumps between the states of the descrambling sequence, in a step of four states (for example). To achieve this objective, the hardware architecture of FIG. 6 is proposed, in which eighteen multiplexers (610) to (628) are implemented, the outputs of which being connected to the inputs of the eighteen flip-flops referenced (0 ) to (17) in FIG. 6. Thus, according to the architecture proposed in FIG. 6, if a selection signal Sel = "0" selects the inputs of the bottom of the eighteen (610) to (628) multiplexers of Figure 6, we then find the original architecture of the LFSR-X defined in paragraph §.5.2.2 (page 21) of the 3G-TS 25.213 standard.

Conversely, according to the new architecture proposed in FIG. 6, if a selection signal Sel = "1" selects the inputs "1" from the top of the eighteen multiplexers (610) to (628), we then obtain new paths enabling the original sequence to be traversed in steps of 4, thanks to the new equivalence thus obtained between a selection signal at "1" requiring only one clock stroke and a selection signal at "0 Requiring four clock strokes. In the intermediate conclusion of this paragraph, we note that there is an additional cost of eighteen multiplexers (610) to (628) and three XOR (630), (631) and 632), we enrich the initial structure of the LFSR with an equivalent of "18 MUX + 3 XOR = (18 * 4 + 3 * 4) = 84" NAND2 gates, which thus make it possible to browse the (2 ¹⁸ -1) states possible of the descrambling sequence four times faster than with the architecture usually implemented by the techniques of the prior art. It is also very interesting to note that the method described below can, of course, be generalized to downlink LFSR-X UMTS, which advantageously allows the following results to be obtained:

The advantage of the method according to the invention is multiple when it is applied to the LFSR: it allows first of all to precalculate in hardware or “hardware” in English, an initial SEED value, that is to say a starting value of the calculations corresponding to a scrambling code given by a base station), without having to provide multiplexers for preloading the 18 D-FFs. The 18 multiplexers implemented in the new architecture of FIG. 6, according to the invention, make it possible to replace the eighteen preloading multiplexers usually implemented specially for preloading the LFSR. it also makes it possible, during a process of sequencing by group or “slewing” in English, to reach a predetermined state starting from a starting point (value of SEED for example), much more quickly and at frequency d identical clock. The gains and advantages thus obtained thanks to the method according to the invention, and in particular in terms of material implementation are all the more important and interesting when compared with the method according to the prior art, called a mask. Indeed, in the mask method, if one wishes to divide by a factor of four the jumps necessary to access a predetermined state of a scrambling sequence, it is necessary to very significantly increase the complexity of setting work of material architecture. Indeed, it will be necessary to increase by four the speed of recovery of a synchronization value, to enrich the hardware architecture of 102 NAND2 gates obtained in the following way most often:

"17 XOR + 17 AND = (17 * 4 + 17 * 2) NAND2 = 17 * 6 = 102 doors NAND2". In addition, the additional logic necessary to implement to allow the loading of the optimal value of the mask and memorize the three or four different masks will have a significant cost in number of NAND2 gates. Finally, another important advantage of the architecture proposed in FIG. 6, which offers a proposal for implementing the method and device according to the invention in the context of a descrambler, in particular but not limited to the downlink UMTS type, relates to the possibility of being able to return immediately and at any time to the architecture and operation of the original LFSR. It suffices simply to replace the selection signal Sel = "0", the 18-bit register then being already loaded with the desired state. It is important to underline to mark the difference of the invention with the methods of the prior art and in particular that by mask, that this result is also much more expensive. Indeed, the mask method only allowing to extract a single bit for each state, this means that on the one hand it is necessary to count eighteen clock strokes to output the state of the LFSR with a time interval offset (or “shift” given), and therefore on the other hand, to save these eighteen bits so that they can be loaded into the eighteen D-FFs. However, such a last step alone would require providing eighteen multiplexers at the input of the eighteen DFFs, only to load the eighteen bits into the LFSR. 7.4.2 Case of the LFSR-Y descrambler FIG. 7 illustrates the modifications made to the architecture of an LFSR-Y descrambler for which it is also sought to optimize the number of clock strokes to be applied so as to also be able to make jumps of four states and thus access the synchronization value, faster. To achieve the above-mentioned objective, an additional cost of 18 multiplexers (710) to (727) and three XOR (730), (731) and (732) of XOR4 type, is necessary and sufficient to obtain an operation equivalent to that of : "(18MUX + 3 * 3XOR) = (18 + 9) * 4 = 27 * 4 = 108 doors NAND2". The same advantages of the invention as those mentioned in the previous paragraph for the LFSR-X descrambler are obtained here for the LFSR-Y descrambler of FIG. 7. 7.4.3 Explanation of the construction of the hardware architectures used according to the invention by matrix calculation applied to the structure of the descrambler. or “scrambler” in English The objective of this section is to explain how the hardware or “hardware” architectures according to the invention are constructed, of FIGS. 6 and 7 from a matrix calculation. Let A be the LFSR-X transition matrix such that

. We then obtain:

This matrix A corresponds to the LFSR-X defined in the 3G TS.25.213 standard, section 5.2.2. It is implemented materially by means of the architecture of FIG. 8 which integrates eighteen flip-flops (810) to (827), all clocked by the same clock. The i ^th component of the vector x _k , namely: x (i) _k represents the state value of the i th th flip-flop (FIG. 8), obtained following the execution of a number k of clock ^ticks . Each coordinate of this vector therefore has the value of either "0" or "1". Finally, the vector x ₀ is defined as:

This means that the eighteen flip-flops (510) to (827) in Figure 8

are initialized from left to right so that

Thus, the principle of "jumps of N" implemented according to the invention is explained in a matrix manner by the following formula: XN = A ^N Xk, which is obtained by induction from the generic formula: Xk + i = A.Xk.

If one calculates for example the matrix A ⁴ , which corresponds to the example of jump of a step four, proposed in the paragraphs §.7.4.1 in the case of LFSR-X and illustrated by figure 6, one obtains the matrix next :

AT

We therefore deduce from reading, line by line, this passage matrix and by placing x _{k + 4} to the left of this matrix and x _k to the right, that: x (0) _{k + 4} = x (4) _k x (l) _{k + 4} = x (5) _k .... x (13) _{k + 4} = x (L7) _k x (14) _{k + 4} = x (0) _k + x (7) _k mod 2 (corresponding to XOR-0 (629) in Figure 6 and identical to XOR (729) in Figure 7). x (15) _{k + 4} = x (l) _k + x (8) _k mod 2 (it is the XOR-1 (630) of figure 6). x (16) _{k + 4} = x (2) _k + x (9) _k mod 2 (this is the XOR-2 (631) of figure 6). x (17) _k44 = x (3) _k + x (10) _k mod 2 (this is the XOR-3 (632) of figure 6). The signs “=” in these equations correspond to the multiplexers (610) to (627) of FIG. 6, for which the top input is selected by the selection signal Sel = “1”. It is thus possible to conclude that to reach a certain predetermined state, or a certain phase, of index P from another phase of index k, it is now sufficient to simply apply the formula: Xk + p = A ^p .Xk. With the original LFSR, i.e. the LFSR whose multiplexers would select the bottom entry in the architecture of Figure 6, for example, it would cost P clock strokes from the state k to reach the desired state P + k. If one implements the hardware architecture applying the method according to the invention, that is to say that in which the selection signal Sel≈ "1" chooses the input from the top of the flip-flops, one can write: P = jN + r, where r is the remainder in the - »-> Euclidean division of P by N, from where: Xk ₊ p = A ^J ' ^{N + r} Xk, which is still equivalent to: X + p = A ^N ) .A ^r .Xk, which formula can still be broken down into:

Xk + p = A ^r .Xk + Nj (2) The formula (1) means that we first execute j clock ticks with the multiplexers whose top input is selected (Sel = "1") , then r clock ticks with the multiplexers whose bottom input (Sel = "0") is selected, which therefore amounts to executing only a total of j + r clock ticks instead of N.j + r. One can also note here that if one wishes to make jumps of a step N, of the form N = 2 ^m , the counting of the clock ticks can be done advantageously by shifting the sequence P by m bits to the right . The above results can be applied identically for the LFSR-Y descrambler, by adapting the transition matrix. 7.5 Other application of the method and device according to the invention 7.5.1 Pre-calculation of SEED in LFSR Taking into account the 3GTS25.213 standard, the utility of performing jumps of value N> 1 in the sequences produced from LFSR concerns mainly LFSR-X descramblers. Indeed, knowing the primary scrambling code ("scrambling code" in English) of a base transmitting station, which is an integer between 0 and 511 and which can be noted here "i", we must take the LFSR-X on the phase: n = 16 * i by therefore executing 16 * i clock ticks usually on the LFSR-X, starting from the known and predetermined initial state.

Thanks to the mechanism according to the invention, it is now possible to carry out accelerated jumps defined by N changes of state of the LFSR-X in a single clock stroke. Such an operation is carried out in only: (n / N + r) clock ticks where (n / N) is the quotient of the Euclidean division of n by N and r the rest of this division. Thus, for example, if N = 16, it suffices to make 16 * i / 16 = i clock strokes to reach the desired state. We can also emphasize the fact that such a calculation of the value of SEED for the LFSR-X can be applied in one direction or the other to reach a shift corresponding to the alternative scrambling codes. or right defined by the 3GTS25.213 standard. 7.5.2 Accelerated slewing Figure 9 illustrates the advantage of the invention for implementing an accelerated slewing process. In this figure, the line 91 represents the evolution of the states of the LFSR used at the level of the transmitting base station. Its evolution takes place in time Te (“Chips” time). Each transmitted data frame "traverses" the line 91 from a state S ₀ referenced 92 to a state S _n referenced 93 in FIG. 9, then returns to S ₀ after S _n .

The straight line 91 therefore represents the evolution of the phase of the signal received at each instant. Thus, in to (94) we want to start descrambling the received signal, which is not normally possible since it would be necessary in this case to take the phase of the two LFSR X and Y of the modem, instantly in their states respective S _t . The slewing mechanism usually known and used by the solutions of the prior art thus attempts to catch the straight line 91 of FIG. 9 via the straight line 95, but this by accelerating the timing of the two LFSR X and Y, for example by multiplying by eight the time “chip” Te. According to the usual slewing technique, this approach then makes it possible to reach the straight line 91 at time t ₃ (96) and to be in phase at this time with the received signal. Thanks to the LFSR X and Y according to the invention, which can switch to perform jumps of N states by clock strokes, it is now possible to catch the phase of the signal received at time t (97) situated well in advance. on t ₃ (96), in the following way: - the LFSR-X is first of all initialize with the value of SEED corresponding to the scrambling code (“scrambling code” in English) of the transmitting base station of which one wishes demodulate the signal using the SEED pre-calculation method described for example in paragraph §.7.5.1; - the two LFSR X and Y then switch their multiplexers by toggling the selection signal Sel = "1" on the inputs of the top of the flip-flops, which makes it possible to reach the state S ₂ (98) of FIG. 9 by jumps of N time intervals. The number of clock strokes “j” to be applied next is then determined as follows: let n _{0 be} the value of the time interval counter to be traveled (which performs modulo counts 38399 in the context of UMTS) corresponding to time t ₀ (94). It then suffices to choose “j” such that j * N is greater than (n ₀ + j) and that (jl) * N is less than (n ₀ + j). By developing and solving these two inequalities, we determine the choice of the value of "j" such that: - - <j <-. ^J N - l N - l Thus, having taken care to wire the LFSR so that jumps of a step Nl = 2 ^m , the determination of "j" is carried out by simple shift, as follows: we shift n ₀ by m bits to the right, then we add 1. Thus, from time t ^ (99) in Figure 9, the two LFSR X and Y are switched back to their original configuration in which the selection signal Sel = "0". These two LFSRs are then frozen (that is to say that the D flip-flops of the LFSRs are not clocked) during: “N * j - (n ₀ + j) = (Nl) * j - n ₀ »Clock strokes necessarily strictly positive (case of a slewing by waiting). In addition, once the number of clock strokes has been executed, we then find ourselves at point (t ,, S ₂ ) - references 98 and 99 in FIG. 9. The two LFSR X and Y are then always in a characterized configuration by a selection signal Sel = "0". They are again clocked and will generate the descrambling sequence in phase with the received signal (synchronization), thus making it possible to start the demodulation of the received signal much faster than with the solutions envisaged according to the known prior art. It is specified here that the choice of step jumps Nl = 2 in no way contradicts the value of step jump N = 2 ^m , need expressed in paragraph §7.5.1 in the case of the SEED pre-calculation. Indeed, the SEED calculation is not necessarily performed in the same LFSR as that used for the slewing. We can therefore perfectly imagine that the SEED calculation of the example cited in paragraph §7.5.1 is carried out in a block of the Cell-Searcher type of a UMTS receiver for the jump value of step jumps of a step N = 2 ^m , and that the second calculation mentioned above (jumps of one step Nl = 2 ^m ) applies to the RAKE of a UMTS receiver. It is simply a matter of making a judicious choice making it possible to simplify the embodiment according to the invention, by taking for N or Nl pitch values of the form 2 ^m , depending on whether the precalculation of SEED or slewing. Finally, it will be specified, by way of conclusion, that the methods and device according to the invention, as well as their software and / or hardware implementation methods previously described through several examples of applications, have numerous advantages, in particular in comparison with the mask method of prior art solutions. All these elements according to the invention make it possible on the one hand and in all cases to accelerate the front course by group of frames (or "slewing forward" in English) by a factor N, and on the other hand, to allow to pre-calculate SEED values corresponding to given scrambling codes, without having to pre-load them beforehand and therefore having to plan and implement all the logic necessary for the execution of a such operation.

Claims

1. Method for synchronizing a device for receiving scrambled data by means of at least one periodic scrambling sequence organized in K time intervals each comprising N bit periods called symbols, said method comprising a step of calculating a synchronization value of at least one polynomial generating said scrambling sequence, in a synchronization time interval and in a period of predetermined synchronization bits, characterized in that, during said calculation step, progress is made in said sequence by hopping at least one time interval and at least one bit period, by implementing a matrix calculation of said synchronization value.

2. synchronization method according to claim 1, characterized in that said matrix calculation implements a multiplication of an initialization value of said generator polynomial by at least one predetermined passage matrix.

3. synchronization method according to any one of claims 1 and 2, characterized in that one progresses in said sequence by jumps of at least one time interval, by calculating the value of said generator polynomial at the borders of said intervals, up to 'said synchronization time interval.

4. synchronization method according to claims 2 and 3, characterized in that said value of said generator polynomial at the borders of said time intervals is determined, from said initialization value, by successive multiplications by an interval passage matrix of time.

5. Synchronization method according to any one of claims 3 and 4, characterized in that, within said synchronization time interval, progress is made in said sequence by hopping of at least one period of N bits, by calculating the value of said generator polynomial at the borders of said bit periods, until the value of said synchronization bit period is obtained.

6. synchronization method according to any one of claims 3 and 4 and according to claim 5, characterized in that said value of said polynomial generator at the borders of said bit periods is determined, from said value of said generator polynomial at the borders of said intervals, by successive multiplications by a bit period passage matrix.

7. synchronization method according to any one of claims 1 to 6, characterized in that said data are scrambled according to at least two scrambling sequences X and Y, in that said initialization value for said sequence Y is fixed, and in that said initialization value for said sequence X is characteristic of a device for transmitting said scrambled data.

8. synchronization method according to claim 7, characterized in that, said periodic scrambling sequence being organized in K time intervals each comprising N bit periods, said symbol passing matrix for said sequence X is the matrix (M ^K ) ^N and said time interval passage matrix for said sequence X is the matrix M _x .

9. A synchronization method according to any one of claims 7 and

8, characterized in that, said periodic scrambling sequence being organized in K time intervals each comprising N bit periods, said symbol passing matrix for said sequence Y is the matrix My and in that said value of said generator polynomial boundaries of said intervals for said sequence Y is determined from a table of vectors associated with said polynomial generating said sequence Y.

10. Synchronization method according to any one of claims 7 to

9, characterized in that to reach the phase vector of index (β + μ) from the phase vector of index β of said scrambling sequence by successive jumps of value i, at least the following successive steps are carried out of: decomposition of the index value μ in the form of a sum of the quotient and of the remainder r of the Euclidean division of μ by i, said quotient being expressed in the form of a product of an integer j with said jump value i; raising to full power j of said time interval passing matrix of said sequence X, said time interval comprising ranges of i bit periods; multiplication of said phase vector with index β by said time interval passage matrix (M _X ') ^J , so as to obtain the value of said phase vector with index (β + ixj), then; multiplication of said index phase vector (β + ixj) by said bit period passing matrix (M _x ), so as to position itself on the correct bit period value; so that the number of clock strokes to be applied to reach said desired phase vector is limited to a value of (j + r).

11. A synchronization method according to any one of claims 1 to

10, characterized in that said successive hops of bit period have a value expressed in the form of a power of two.

12. Synchronization method according to any one of claims 1 to

11, characterized in that said synchronization method implements the UMTS standard ("Universal Mobile Telecommunications System" for "Universal mobile telecommunications system"), and in that said bit periods are CPICH symbols.

13. A synchronization method according to claim 12, characterized in that said reception device comprises at least one RAKE receiver and cell search means of Cell Searcher type.

14. Synchronization method according to any one of claims 12 and 13, characterized in that said bit periods being CPICH symbols, each of said time intervals comprises K = 10 periods of N = 256 bits, so as to obtain a finer granularity.

15. Synchronization method according to claim 14, characterized in that said bit period passage matrix for said sequence X is the matrix:

which can still be written in the form xo, n + i = x _{3 n} ^Λ x _{4 n} ^Λ x _{7 n} ^Λ x ₈ _to ^χ 17> n + l = X ₂ , _n ^Λ X ₃ , _n ^Λ X _{6, n} ^Λ X ₇ , _n ^Λ X ₉ , _n ^Λ X _10> „ ^Λ Xι _3; n ^Λ Xl4, n and said time interval passage matrix for said sequence X is the matrix

which can still be written in the form: X0, n + 1 = X _{1> n} X _{2 n} - X ^ Λ X _{4> n} Λ χ _{5 n} Λ χ _6jn Λ x ^ Λ χ _{9 n} Λ ^ Λ ^ Λ JJ ^ Λ J ^ Λ J ^ to ^X17 ' ^{n + 1 = X} 2, n ^{Λ X} 3, n ^AX 6, n ^{Λ X} 8, n ^{Λ X} 10, n ^AX ll, n ^{Λ X} 12, n ^Λ 13, n said bit period passing matrix for said sequence Y then being the matrix: _{χi7jn + 1} ^ Λ χ _{3 n} Λ χ _{6 n} Λ _{x?> n} Λ _χ ^ Λ _{Xl0 n} Λ _{Xl3 n} Λ _{Xl4 n}

which can still be written in the form: X0, n + 1 = X _{0 n} X _ljn AX _{2 n} Λ χ _{4; n} Λ X ^ Λ χ _7jn Λ χ _{8 n} Λ ^ Λ ^ Λ ^ to ¹⁷ > ^{n + 1} = ^X 0, n ^{Λ X} l, n " ^X 4, n ^{Λ X} 7, n ^{Λ X} 9, n ^{Λ X} ll, n ^{Λ X} 12, n ^{Λ X} 13, n ^Λ 14, n ^{Λ X} 15, n ^{Λ X} 17, n.

16. Device for receiving scrambled data by means of at least one periodic scrambling sequence, and organized in time intervals each comprising at least one bit period called symbol, characterized in that it comprises means for synchronizing said device comprising means for calculating a synchronization value of at least one polynomial generating said scrambling sequence, by progression in said sequence by hopping at least one bit period, said calculation means implementing a matrix calculation of said synchronization value.

17. Reception device according to claim 16, characterized in that said calculation means comprise a first register comprising flip-flops outputting the bits of said sequence making it possible to obtain said synchronization value.

18. Reception device according to any one of claims 16 and 17, characterized in that the input of each flip-flop is connected to the output of a multiplexer controlled by a selection signal (SEL).

19. Reception device according to claim 18, characterized in that when said selection signal selects the bottom input of said multiplexer, said passage matrix M _x is applied and when said selection signal selects the top input of said multiplexer , we apply said matrix of passage M _x .

20. Reception device according to any one of claims 16 to 19, characterized in that it applies to fields belonging to the group comprising: - optimization of step 3 of the cell scanner ("Cell Searcher") in English) UMTS; speeding up the slewing process of a UMTS rake receiver; optimizing the operation of a UMTS equalizer; the pre-calculation of the initial value (or “seed” in English) of a linear feedback shift register (or “LFSR: Linear Feedback Shift Register”).

21. Mobile radio terminal comprising means for receiving scrambled data by means of at least one periodic scrambling sequence, and organized into time intervals (frames) each comprising at least one bit period called symbol, characterized in that '' it comprises means for synchronizing said receiving means comprising means for calculating a synchronization value of at least one polynomial generating said scrambling sequence, by progression in said sequence by hopping of at least one bit period , said calculation means implementing a matrix calculation of said synchronization value.