WO2005101480A3 - Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung - Google Patents

Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung Download PDF

Info

Publication number
WO2005101480A3
WO2005101480A3 PCT/EP2005/051618 EP2005051618W WO2005101480A3 WO 2005101480 A3 WO2005101480 A3 WO 2005101480A3 EP 2005051618 W EP2005051618 W EP 2005051618W WO 2005101480 A3 WO2005101480 A3 WO 2005101480A3
Authority
WO
WIPO (PCT)
Prior art keywords
component
circuit mounted
electroconductive substrate
connection technique
planar connection
Prior art date
Application number
PCT/EP2005/051618
Other languages
English (en)
French (fr)
Other versions
WO2005101480A2 (de
Inventor
Eric Baudelot
Original Assignee
Siemens Ag
Eric Baudelot
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Eric Baudelot filed Critical Siemens Ag
Publication of WO2005101480A2 publication Critical patent/WO2005101480A2/de
Publication of WO2005101480A3 publication Critical patent/WO2005101480A3/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401Structure
    • H01L2224/2402Laminated, e.g. MCM-L type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405Shape
    • H01L2224/24051Conformal with the semiconductor or solid-state device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)

Abstract

Eine Vorrichtung weist ein über eine Isolationsschicht auf einem Substrat angeordnetes Bauelement und eine Verbindung des Bauelements mit dem Substrat und/oder einem weiteren Bauelement auf. Die Verbindung enthält eine Schicht aus elektrisch isolierendem Material, die an dem Bauelement sowie dem Substrat und/oder dem weiteren Bauelement angeordnet ist, und eine Schicht aus elektrisch leitendem Material, die an der Schicht aus elektrisch isolierendem Material angeordnet ist und das Bauelement mit dem Substrat und/oder dem weiteren Bauelement elektrisch verbindet.
PCT/EP2005/051618 2004-04-19 2005-04-13 Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung WO2005101480A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004019445.9 2004-04-19
DE200410019445 DE102004019445A1 (de) 2004-04-19 2004-04-19 Mit planarer Verbindungstechnik auf einem insbesondere elektrischleitendem Substrat aufgebaute Schaltung

Publications (2)

Publication Number Publication Date
WO2005101480A2 WO2005101480A2 (de) 2005-10-27
WO2005101480A3 true WO2005101480A3 (de) 2006-01-05

Family

ID=34967484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/051618 WO2005101480A2 (de) 2004-04-19 2005-04-13 Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung

Country Status (2)

Country Link
DE (1) DE102004019445A1 (de)
WO (1) WO2005101480A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006015117A1 (de) * 2006-03-31 2007-10-04 Osram Opto Semiconductors Gmbh Optoelektronischer Scheinwerfer, Verfahren zum Herstellen eines optoelektronischen Scheinwerfers und Lumineszenzdiodenchip
US7799614B2 (en) 2007-12-21 2010-09-21 Infineon Technologies Ag Method of fabricating a power electronic device
DE102015015699A1 (de) 2015-12-04 2017-06-08 Abb Schweiz Ag Elektronisches Leistungsmodul

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037338A2 (de) * 1999-11-16 2001-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Verfahren zum integrieren eines chips innerhalb einer leiterplatte und integrierte schaltung
US20020053720A1 (en) * 2000-09-15 2002-05-09 Alstom Substrate for an electronic circuit, and an electronic module using such a substrate
WO2003030247A2 (de) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Verfahren zum kontaktieren elektrischer kontaktflächen eines substrats und vorrichtung aus einem substrat mit elektrischen kontaktflächen

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI946015A (fi) * 1994-07-08 1996-01-09 Picopak Oy Electroless-kontaktinystynmuodostusmenetelmä

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037338A2 (de) * 1999-11-16 2001-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Verfahren zum integrieren eines chips innerhalb einer leiterplatte und integrierte schaltung
US20020053720A1 (en) * 2000-09-15 2002-05-09 Alstom Substrate for an electronic circuit, and an electronic module using such a substrate
WO2003030247A2 (de) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Verfahren zum kontaktieren elektrischer kontaktflächen eines substrats und vorrichtung aus einem substrat mit elektrischen kontaktflächen

Also Published As

Publication number Publication date
WO2005101480A2 (de) 2005-10-27
DE102004019445A1 (de) 2005-11-03

Similar Documents

Publication Publication Date Title
WO2008057671A3 (en) Electronic device including a conductive structure extending through a buried insulating layer
WO2009021741A3 (de) Organische elektronische bauelemente
WO2006056648A3 (en) Electronics module and method for manufacturing the same
WO2008021982A3 (en) Surface mountable chip
TW200802790A (en) Electronic substrate, semiconductor device, and electronic device
EP1926145A3 (de) Selbstausgerichtete Durchgangswege zur Chipstapelung
EP1753277A3 (de) Leiterplatte
TW200721337A (en) Coreless substrate and manufacturing method thereof
TW200701264A (en) Inductor
TW200629998A (en) Printed circuit board and forming method thereof
WO2007004115A3 (en) Organic electronic device and method for manufacture thereof
HK1086434A1 (en) Method and device for electrolytically increasing the thickness of an electrically conductive pattern on a dielectric substrate, as well as a dielectric substrate
WO2006094025A3 (en) Fabricated adhesive microstructures for making an electrical connection
TW200620502A (en) Semiconductor device, circuit board, electro-optic device, electronic device
TW200607083A (en) Display device and method of manufacturing the same
TW200631059A (en) Semiconducor device and manufacturing method thereof
TW200704582A (en) Semiconductor composite device and method of manufacturing the same
WO2009038950A3 (en) Flexible circuit board, manufacturing method thereof, and electronic device using the same
WO2008003287A3 (de) Elektrisches bauelement mit einem sensorelement, verfahren zur verkapselung eines sensorelements und verfahren zur herstellung einer plattenanordnung
WO2009158551A3 (en) Integrated circuit with ribtan interconnects
EP1868422A3 (de) Einbausubstrat für elektronische Bauteile und Herstellungsverfahren dafür
WO2009075079A1 (ja) 回路板、回路板の製造方法およびカバーレイフィルム
WO2007043972A8 (en) Device carrying an integrated circuit/components and method of producing the same
WO2012085472A3 (fr) Circuit imprime a substrat metallique isole
TW200509746A (en) Organic electronic device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

122 Ep: pct application non-entry in european phase