WO2005101480A3 - Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung - Google Patents

Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung Download PDF

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Publication number
WO2005101480A3
WO2005101480A3 PCT/EP2005/051618 EP2005051618W WO2005101480A3 WO 2005101480 A3 WO2005101480 A3 WO 2005101480A3 EP 2005051618 W EP2005051618 W EP 2005051618W WO 2005101480 A3 WO2005101480 A3 WO 2005101480A3
Authority
WO
WIPO (PCT)
Prior art keywords
component
circuit mounted
electroconductive substrate
connection technique
planar connection
Prior art date
Application number
PCT/EP2005/051618
Other languages
English (en)
French (fr)
Other versions
WO2005101480A2 (de
Inventor
Eric Baudelot
Original Assignee
Siemens Ag
Eric Baudelot
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Eric Baudelot filed Critical Siemens Ag
Publication of WO2005101480A2 publication Critical patent/WO2005101480A2/de
Publication of WO2005101480A3 publication Critical patent/WO2005101480A3/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
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    • H01L2924/01032—Germanium [Ge]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)

Abstract

Eine Vorrichtung weist ein über eine Isolationsschicht auf einem Substrat angeordnetes Bauelement und eine Verbindung des Bauelements mit dem Substrat und/oder einem weiteren Bauelement auf. Die Verbindung enthält eine Schicht aus elektrisch isolierendem Material, die an dem Bauelement sowie dem Substrat und/oder dem weiteren Bauelement angeordnet ist, und eine Schicht aus elektrisch leitendem Material, die an der Schicht aus elektrisch isolierendem Material angeordnet ist und das Bauelement mit dem Substrat und/oder dem weiteren Bauelement elektrisch verbindet.
PCT/EP2005/051618 2004-04-19 2005-04-13 Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung WO2005101480A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004019445.9 2004-04-19
DE200410019445 DE102004019445A1 (de) 2004-04-19 2004-04-19 Mit planarer Verbindungstechnik auf einem insbesondere elektrischleitendem Substrat aufgebaute Schaltung

Publications (2)

Publication Number Publication Date
WO2005101480A2 WO2005101480A2 (de) 2005-10-27
WO2005101480A3 true WO2005101480A3 (de) 2006-01-05

Family

ID=34967484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/051618 WO2005101480A2 (de) 2004-04-19 2005-04-13 Mit planarer verbindungstechnik auf einem insbesondere elektrisch leitendem substrat aufgebaute schaltung

Country Status (2)

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DE (1) DE102004019445A1 (de)
WO (1) WO2005101480A2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006015117A1 (de) * 2006-03-31 2007-10-04 Osram Opto Semiconductors Gmbh Optoelektronischer Scheinwerfer, Verfahren zum Herstellen eines optoelektronischen Scheinwerfers und Lumineszenzdiodenchip
US7799614B2 (en) 2007-12-21 2010-09-21 Infineon Technologies Ag Method of fabricating a power electronic device
DE102015015699A1 (de) 2015-12-04 2017-06-08 Abb Schweiz Ag Elektronisches Leistungsmodul

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037338A2 (de) * 1999-11-16 2001-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Verfahren zum integrieren eines chips innerhalb einer leiterplatte und integrierte schaltung
US20020053720A1 (en) * 2000-09-15 2002-05-09 Alstom Substrate for an electronic circuit, and an electronic module using such a substrate
WO2003030247A2 (de) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Verfahren zum kontaktieren elektrischer kontaktflächen eines substrats und vorrichtung aus einem substrat mit elektrischen kontaktflächen

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI946015A (fi) * 1994-07-08 1996-01-09 Picopak Oy Electroless-kontaktinystynmuodostusmenetelmä

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037338A2 (de) * 1999-11-16 2001-05-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e. V. Verfahren zum integrieren eines chips innerhalb einer leiterplatte und integrierte schaltung
US20020053720A1 (en) * 2000-09-15 2002-05-09 Alstom Substrate for an electronic circuit, and an electronic module using such a substrate
WO2003030247A2 (de) * 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Verfahren zum kontaktieren elektrischer kontaktflächen eines substrats und vorrichtung aus einem substrat mit elektrischen kontaktflächen

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Publication number Publication date
WO2005101480A2 (de) 2005-10-27
DE102004019445A1 (de) 2005-11-03

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