WO2005099095A1

WO2005099095A1 - Half-step phase-locked loop

Info

Publication number: WO2005099095A1
Application number: PCT/EP2005/004317
Authority: WO
Inventors: Michel Robbe
Original assignee: Eads Secure Networks
Priority date: 2004-04-08
Filing date: 2005-04-06
Publication date: 2005-10-20
Also published as: FR2868891A1; FR2868891B1

Abstract

An oscillator supplies a high frequency signal fvco to a frequency divider. A phase comparator produces a signal measuring the phase difference between the divided frequency signal (QA) and a reference signal at a comparison frequency fref. A low-pass filter controls the oscillator from the measurement signal. To enable a high frequency signal to be synthesized such that fvco = P x fref, where P is the sum of an integer value (Po) and of a deviation value (ΔP) relative to said integer value which corresponds to a modulo 0.5 number, a digital frequency divider is constructed to generate a measurement window (&num;n-l, &num;n, &num;n+l) on each cycle of the divided frequency signal, the duration of which corresponds alternately to an even number then to an odd number of cycles of the high frequency signal.

Description

HALF-STEP PHASE-LOCKED LOOP

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to phase-locked loops (PLL) , and in particular their application to digital modulation synthesis (DMS) .

2. Related Art

A PLL conventionally comprises a voltage controlled oscillator (VCO) delivering a high frequency output signal f_Vco a digital frequency divider converting the high frequency signal into a divided frequency signal, a phase/frequency comparator (phase/frequency detector, PFD) producing a signal measuring a phase/frequency difference between the divided frequency signal and a reference signal at a comparison frequency f_ref, and a low-pass filter (LPF) to which the measurement signal is applied and the output of which controls the VCO.

In its application to digital modulation, instantaneous variations of the division factor applied by the digital frequency divider are introduced to obtain corresponding variations in the frequency or phase of the VCO output signal.

This application is particularly sensitive to disturbances, however weak, introduced into the components of the loop, because the modulation corresponds to very low relative variations of frequency relative to the comparison frequency. A typical order of magnitude of these variations is a thousandth of the comparison frequency. In these conditions, subtle phenomena, difficult to identify, can- provoke noise or spurious lines at the output of the VCO, and a careful optimization of the PLL is required. In particular, it is known that the phase comparator introduces noise into the loop when it activates the measurement signal, this noise being reflected in a phase noise in the high frequency signal.

This is why the phase comparator can be built to activate the measurement signal only during a measurement window in response to each active edge of one of the PFD input signals. Activation of the measurement signal comprises, when an active edge of the other input signal of the phase comparator, possibly delayed by a predefined time, falls within the measurement window, a first pulse between the start of the measurement window and this active edge and a second pulse opposite to the first pulse between the active edge and the end of the measurement window. A phase drift of the loop relative to its operating point is reflected in an imbalance between the two pulses, that the low-pass filter assimilates to apply a compensation to the control input of the VCO.

Figures 1 to 3 illustrate the behaviour of the loop in the case where the phase comparator is conventionally of "backlash" type. It is assumed, for example, that the active edges of the high frequency signal S and of the reference signal FREF are falling edges.

Figure 1 shows how the VCO is controlled when the PLL is in balance. On each cycle of the reference signal FREF, the PFD generates two consecutive pulses of the same duration on respective components INVP and INVN of the measurement signal. The current delivered by the charge pump, which is proportional to INVP - INVN, appears as represented on the third line of the figure, and it gives rise to a voltage V0 at the control input of the VCO.- This analogue voltage presents a pulse on each cycle of the signal FREF, or comparison cycle, with a voltage ramp-up followed by a ramp-down which, when the PLL is balanced, returns the voltage VO to its value prior to the pulse.

The diagram of Figure 2 corresponds to the case where the phase error is positive. In this case, one of the two pulses, INVN, is shortened to dφ relative to its duration in balance, such that the voltage pulse VI at the input of the VCO (fourth line of Figure 2) is incomplete and allows a residual voltage to remain, the effect of which is to compensate for the detected phase error. The fifth and last line of Figure 2 shows the difference between the voltage VI observed when the error is positive and the voltage VO in balance. The change of value of this deviation VI - VO takes place over a duration dφ equal in absolute value to the detected phase shift.

Symmetrically, when the phase error is negative (Figure 3), the pulse INVN is lengthened by the duration dφ. Here, too, this duration dφ is reflected in the command V2 received by the VCO.

In the application of the PLL to D S, the instantaneous variations of the division factor P of the frequency divider constantly give rise to phase differences dφ that the PLL makes up to produce the required modulation.

To limit the contribution of the PFD to loop noise, it is desirable to have a measurement window that is as narrow as possible. Moreover, it is desirable to have a reference signal at the frequency f_ref as high as possible.

In practice, the noise floor of the loop, in other words the noise in the absence of modulation, below which the^" value must not fall, is proportional to log P. However, if the comparison frequency f_ref of the reference signal FREF increases, the division factor P decreases since:

Nevertheless, increasing the frequency f_ref amounts to increasing the frequency of the measurement windows, and therefore the contribution of the PFD to the loop noise.

Furthermore, since the division by P is performed by counting down by an integer number P of periods of the output signal S, the step (or quantum) of the PLL is equal to the frequency f_ref of the reference signal. Stated otherwise, the frequencies of the high frequency signal that can be generated correspond to integer multiples of the frequency f_ref of the reference signal. In the transmitters of the mobile terminals and base stations of a narrowband radio communication system, when the frequency f_ref of the signal FREF is, for example, equal to 6.5 MHz, the frequency f_vco of the signal generated in the 380-430 MHz band can have the value 383.5 MHz (for P=59) , 390 MHz (for P=60) , 396.5 MHZ (for P=61), 403 MHz (for P=62), and so on. It follows that increasing the frequency f_ref raises the problem of increasing the step of the PLL.

Patent US 6,392,493 discloses a PLL in which the frequency divider presents respective values of the division factor having an incrementation step of 0.5, for example 34, 34.5 and 35. Stated otherwise, the division factor takes half-integer values (or modulo 1/2 values) . The term "half-step" can be used in the sense that the step of the PLL is equal to 1/2 x f_ref. This document does not, however, describe how the locking of the PLL is achieved. What can be considered is to take account of both the rising edges and the falling edges of the high frequency signal in the digital divider . ^"This solution is, however, not possible to implement in cases of instability of the duty cycle of the high frequency signal, which would cause a prohibitive phase jitter.

SUMMARY OF THE INVENTION The present invention reduces the loop noise of the PLL, in particular by enabling the comparison frequency to be increased without increasing the step of the PLL.

A first aspect of the invention thus proposes a phase- locked loop, comprising an oscillator controlled to deliver a high frequency signal, a digital frequency divider with a variable division factor for converting the high frequency signal into a divided frequency signal, a phase comparator for receiving the divided frequency signal and a reference signal and producing a signal measuring a phase difference between the divided frequency signal and the reference signal, and a low- pass filter for controlling the oscillator from the measurement signal. The division factor of the frequency divider can take at least one value corresponding to a modulo 1/2 number.

The expression modulo 1/2 number is used to mean any number of decimal value equal to a multiple of 0.5, for example 0.5, 1.5, 2.5, etc.

The loop also comprises means for generating, for each active edge of the divided frequency signal, a measurement window of duration defined by counting cycles of the high frequency signal.

The phase comparator is also configured to activate the measurement signal so that, when the loop is in balance, each active edge of the reference signal falls roughly (that is, to within the response times of the PFD) in the middle of the measurement window.

Finally, when a current value of the^' division factor of the frequency divider is a modulo 1/2 number, the duration of the measurement window for a corresponding cycle of the reference signal corresponds to a given number Y of cycles of the high frequency signal which has a given parity, even or odd, whereas the duration of the measurement window for a preceding cycle or following cycle of the reference signal corresponds to a given number Z of cycles of the high frequency signal which has an opposite parity, respectively odd or even.

Stated otherwise, the duration of the measurement window corresponds alternately, that is, from one comparison cycle to the next, to an even number then to an odd number of high frequency signal cycles. A half- step PLL can then be obtained. In _one embodiment, the phase comparator is constructed to activate the measurement signal on each active edge of the divided frequency signal, such that, when an active edge of the reference signal falls within the measurement window, a first component of the measurement signal comprises a positive charge pulse between the start of the measurement window and said active edge of the reference signal and a second component of the measurement signal comprises a negative charge pulse between the active edge of the reference signal and the end of the measurement window.

The expression positive charge pulse is used to mean a pulse for increasing the frequency of the high frequency signal. Conversely, a negative-charge pulse is a pulse for reducing the frequency of the high frequency signal.

Preferably, the frequency divider comprises a pre- divider with a variable pre-division factor for converting the high frequency signal into a pre-divided frequency signal by counting a number of cycles of the high ^"frequency signal which is selectively equal to Y or to Z, and a programmable divider for generating the divided frequency signal by counting cycles of said pre-divided frequency signal.

This pre-divider is used to reduce the phase jitter, because dividers with a variable division factor operating at very high frequency cannot be constructed.

In an embodiment, the programmable divider can comprise a first programmable counter of predefined capacity M_n and a second programmable counter of predefined capacity N_n operating by counting cycles of the pre- divided frequency signal, where M_n and N_n are integer numbers such that M_n ≥ 2 and N_n > M_n which are programmed for each measurement window such that:

Pn ^X Ln

where P_n denotes the current value of the division factor of the digital frequency divider, L_n denotes the duration of the corresponding measurement window, and Ln-i denotes the duration of the preceding measurement window.

In one embodiment, there is provided, , in the programmable divider for example, an algorithmic logic for producing, for each measurement window, the values L_n, M_n and N_n according to the value P_n and the stored value L_n_ι.

To generate a frequency f_vco of the order of 400 MHz, Y is for example equal to 4 and Z is for example equal to 3.

In one embodiment, the means for generating the measurement window comprise means of producing a replica of the divided frequency signal, reproducing each active edge of the divided frequency signal with a delay of a number of cycles of the high frequency signal which corresponds to the duration of the measurement window. A second aspect of the invention relates to a digital modulation frequency synthesizer comprising:

- a phase-locked loop according to the first aspect, and, - a sigma-delta modulator for generating deviation values of the division factor of the digital frequency divider relative to a predefined value, according to a stream of modulation data.

Finally, a third aspect of the invention relates to a mobile terminal of a radio communication system comprising a digital modulation frequency synthesizer according to the second aspect.

._ _ BRIEF DESCRIPTION OF THE DRAWINGS

Other specific features and advantages of the present invention will become apparent from the description that follows of non-limiting exemplary embodiments, with reference to the appended drawings, in which: - Figures 1 to 3 are timing diagrams illustrating the operation of a PLL according to the prior art;

- Figure 4 is a block diagram of a PLL according to an embodiment of the invention;

- Figure 5 is a diagram of a PFD which can be used in the PLL of Figure 4;

- Figure 6 is a diagram of a nine-gate comparator which can be used as phase-difference detection logic in the PFD of Figure 5;

- Figures 7 to 9 are timing diagrams illustrating the operation of the PFD according to Figure 5;

- Figure 10 shows timing diagrams illustrating the principle of operation of a PLL according to the invention;

- Figure 11 is a block diagram of an embodiment of a digital frequency divider with variable division factor which can be used in a PLL according to the invention;

- Figure 12 is a block diagram of an embodiment of a shift register which can be used in the frequency divider of Figure 11;

- Figure 13 is a block diagram of a programmable divider which can be used in a frequency divider according to Figure 11; - Figure 14 is a timing diagram illustrating the operation of the frequency divider according to Figure 11; and,

- Figures 15 to 17 are timing diagrams illustrating an algorithm implemented in an algorithmic logic of the frequency divider according to Figure 11.

DESCRIPTION OF PREFERRED EMBODIMENTS With reference to Figure 4, a frequency synthesizer according to an embodiment of the invention comprises a PLL with a VCO 30 delivering a high frequency signal S, the frequency f_vco of which is for example of the order of a few hundred MHz. This signal is addressed to a digital frequency divider 31 applying a variable division factor P. A variation in time of this division factor P procures a required modulation of the output signal S.

To this end, the frequency synthesizer also comprises a sigma-delta modulator 35 generating, from a stream of modulation data DATA_STR and, in an example, also from a constant value Pc, values SD which, within the frequency divider 31, are translated into deviation values ΔP of the division factor P relative to a predefined integer value Po. The value Po is such that:

where INT denotes the "integer part" function.

The constant value Pc is such that 0 ≤ Pc < 1, and determines, in conjunction with the value Po, the frequency f_VCo required for a particular radio channel. In practice, the following relation applies: fvco = (Pθ + PC) x fref The synthesizer also comprises an adder 36 receiving the value Pc and the data DATA_STR as input, and the output of which is coupled to the input of the modulator 35. At the divider 31, the following relations apply: ΔP = Pc 4- Pm, and P = Po + ΔP, in which the value Pm reflects the modulation relative to the carrier frequency f_VCo-

In the description that follows, only the cases where Pc is equal to 0 or 0.5 are considered.

The values SD are applied to an input controlling the division factor of the digital divider 31. For a one- bit sigma-delta modulator, the possible values of SD are typically 0, 1 and 2. For a two-bit sigma-delta modulator, these values are typically 0, 1, 2, 3 and 4. Conventionally, Po corresponds to the threshold of the modulator 35.

A first divided frequency signal QA from the frequency divider 31 is addressed to an input of a PFD 32 which also receives a reference signal FREF produced from a crystal oscillator (not represented) . The frequency f_rβf of the signal FREF is, for example, of the order of about 10 MHz. To obtain a predefined frequency f_vco at the output of the VCO 30, P = fvco/fref is taken. By modulating P, a frequency or phase modulation is obtained around a carrier at f_VCo-

The sampling frequency of the modulator 35 is conventionally the frequency f_ref of the reference signal FREF.

In the example considered, the PFD 32 outputs a measurement ^"signal having two binary components INVP, INVN. A charge pump (CP) 33 receives these two components to establish a voltage V2 at an input node of a low-pass filter 34. The filtered voltage produced by this filter 34 is used to control the frequency of the VCO 30.

A second divided frequency signal QB is also produced by the frequency divider 31, and is addressed to another input of the PFD 32. The signal QB is, for example, a replica of the divided frequency signal QA. This replica QB reproduces each active edge of the signal QA with a delay generated from the high frequency signal S derived from the VCO 30.

As an example, the active edges of the signals QA and QB are rising edges, between the logic 0 level and the logic 1 level, and the active edges of the signal FREF are falling edges between the logic 1 level and the logic 0 level.

The time interval between each active edge of the signal QA and the following active edge of the signal QB defines a measurement window for the PFD 32. The frequency divider is constructed such that the duration L of this measurement window corresponds selectively either to a number Y or to a number Z of cycles of the signal S at the frequency f_VCor where Y is, for example, an even number and where Z is an odd number, or vice versa.

In an example, Y=4 and Z=3 for a frequency f_vco of the order of 400 MHz. These values are considered to be the smallest possible values providing for an effective phase comparison. However, the smaller the values of Y and Z, the shorter the time for which the PFD 32 is active, and therefore the smaller its contribution to the loop noise.

There now follows a description of an embodiment of the PFD. The PFD according to this embodiment has the advantage of not presenting what is called a dead zone. In ordinary phase comparators, the dead zone results from the non-zero response times of the logic gates of the comparator: phase differences smaller than these response times are not detected, such that the response of the comparator presents a zero-slope band (dead zone) in the vicinity of the origin point. Such a dead zone affects the accuracy of the PLL and in practical terms, prevents it from being used as a phase or frequency modulator.

With reference to Figure 5, the PFD 32 comprises a pulse signal generator 100 which produces a pulse signal PR activated during the measurement window from the two divided frequency signals QA, QB. The generator 100 comprises .-a NAND . gate 101, one input of which receives the signal QA and the other input of which receives the logical complement of the signal QB, produced by an inverter 102. The pulse signal PR is obtained at the output of the NAND gate 101. Its pulse during the measurement window is a pulse at the logic 0 level as is shown in Figures 7 to 9.

The PFD of Figure 2 comprises a second pulse signal generator 110 receiving the reference signal FREF, the active edges of which are falling edges in the example considered. The pulse signal PV produced by this generator 110 presents a short pulse of logic 0 level after each active edge of the reference signal FREF (see Figures 7 to 9) . The generator 110 comprises four inverters 111-114 mounted in series, the first 111 receiving the signal FREF. The outputs of the inverters 111 and 114 are connected to the two inputs of a NAND gate 115, the output of which supplies the pulse signal PV.

To detect the phase difference between the signals QA and FREF, the PFD 32 includes a logic 10 having a first input signal V sampled at the input of the inverter 112 and a second input signal R corresponding to the logical complement of the signal QA, produced by an inverter 118.

Figure 6 illustrates an example of phase difference detection logic 10, called a nine-gate comparator, which can be used in the PFD 32. The input signals R and V are each applied to an input of a respective two- input NAND gate 2, 12. The output of the gate 12 is linked to an input of a two-input NAND gate 14, to an input of a three-input NAND gate 16, and to another input of the gate 20. The output of the gate 16 supplies a first detection signal D and is linked to the other input of the gate 12. The output of the gate 14 is linked to another input of the gate 16, to another input of the gate 20, and to an input of a two- input NAND gate 18. The output of the gate 20 is also linked to the last input of the gate 16 and to the other input of the gate 18. The output of the gate 18 is linked to the other input of the gate 14. The output of the gate 2 is linked to an input of a two-input NAND gate 4, to an input of a three-input NAND gate 6, and to an input of a four-input NAND gate 20. The output of the gate 6 supplies a second detection signal U and is linked to the other input of the gate 2. The output of the gate 4 is linked to another input of the gate 6, to the last input of the gate 20, and to an input of a two-input NAND gate 8. The last input of the gate 6, and the other input of the gate 8 are linked to the output of the gate 20. The other input of the gate 4 is linked to the output of the gate 8.

The PFD represented in Figure 5 also includes a charge transfer control logic 120 which receives the two detection signals D, U, the two pulse signals PR, PV and a separation signal W which is a replica of the reference signal FREF, obtained at the output of the inverter 114.

The operations performed by the logic 120 are as follows:

INVN = (U AND PR) OR [W AND (PR OR PV ) ] INVP = (PR AND PV AND D) OR [W AND (PR OR PV ) ] where X denotes the logical complement of a signal X.

The charge transfer control logic 20 includes an AND gate 121 having two inputs to which are respectively addressed the pulse signals PR and PV. Two OR gates 122, 123 each have an input connected to the output of the AND gate 121. The separation signal W is addressed to the other input of the OR gate 122. The logical complement of this separation signal, produced by an inverter 124, is addressed to the other input of the OR gate 123. A NOR gate 125 has an input receiving the signal QB and another input linked to the output of the inverter 118 to receive the logical complement of the signal QA. This NOR gate 125 produces the complement PR of the pulse signal PR, which is addressed to an input of an OR gate 126. The detection signal U is addressed to the other input of this OR gate 126. The component INVN of the measurement signal is obtained at the output of a NAND gate 127, the two inputs of which are respectively connected to the outputs of the OR gates 123 and 126. The control logic 120 also includes a NAND gate 128 having three inputs respectively receiving the pulse signals PR and PV and the logical complement of the detection signal D obtained at the output of an inverter 129. The component INVP of the measurement signal is obtained at the output of another NAND gate 130, the two inputs of which are respectively connected to the output of the OR gate 122 and to the output of the NAND gate 128.

The operation of the PFD 32 is illustrated by the timing diagrams of Figures 7 to 9. Figures 7 to 9 correspond to situations where the PLL is not yet frequency locked, the active edge of the reference signal FREF falling outside the measurement window defined between the consecutive active edges of the signals QA and QB.

In the case of Figure 7, the divided frequency signal QA is lagging relative to the reference signal FREF, which gives rise to a pulse of logic 0 level in the detection signal D. The start of this pulse of D activates the component INVP of the output signal. The response times of the logic gates of the PFD are such that the end of the pulse of D falls during the pulse of PR, that is, during the measurement window. Consequently, the component INVP of the output signal remains activated until it is deactivated by the end of the pulse of PR following the rising edge of the signal QB. In this operating band (QA lagging relative to FREF) , the duration,_of activation of the component INVP on each comparison cycle, that is, on each cycle of the signal FREF at the frequency f_ref, increases linearly with the delay of the divided frequency signals relative to FREF, with a slope equal to 1.

In the case of Figure 9, the delayed divided frequency signal QB is leading relative to the reference signal FREF. The rising edge of QA triggers a pulse of logic 0 level in the detection signal U. The response times of the logic gates of the PFD are such that the start of the pulse of the detection signal U falls during the pulse of PR, that is, during the measurement window. The start of the pulse of PR activates the component INVN of the output signal. This component INVN remains activated until it is deactivated by the end of the pulse of U following the falling edge of the signal FREF. In this operating band (QB leading relative to FREF) , the duration of activation of the component INVN on each cycle of frequency f_rβf increases linearly with the delay (negative) of the divided frequency signals relative to FREF, with a slope equal to -1.

In the case of Figure 8, the active edge of the reference signal FREF falls during the measurement window, between the active edges of the two divided frequency signals QA, QB. The PLL is then said to be frequency locked. As in the case of Figure 9, the start of the pulse of PR activates the component INVN of the output signal. This activation of INVN lasts until the logic 120 responds to the falling edge of the separation signal W following that of the signal FREF. At this moment, the logic 120 triggers an active edge of the other component INVP of the output signal. This activation of INVP lasts until it is deactivated by the end of the pulse of PR following the rising edge of the signal QB, as in the case of Figure 7.

The difference between the respective activation durations of the INVP and INVN components of the output signal of the PFD 32 is an increasing function, roughly piecewise linear, of the time offset between the divided frequency signal QA and the reference signal

FREF. The slope of this function is equal to 2 in the band where the active edge of the reference signal FREF falls during the measurement window, and 1 outside this band (PLL not frequency locked) . The above-mentioned response times of the logic gates of the PFD are such that the PFD presents no dead zone. It should be noted that this property is obtained without recourse to resistive or capacitive elements in the PFD.

The role of the charge pump 32 is to generate a positive current when INVP is active, and a negative current when INVN is active. The total charge generated will thus be an increasing function, roughly piecewise linear, of the time offset between the divided frequency signal QA and the reference signal FREF. Accumulated in a capacitor, this charge is reflected in a voltage V3 which can be used to control the VCO 30 to force phase alignment between QA and FREF. In practice, a low-pass filter 34 is inserted between the charge pump 33 and the VCO 30 to eliminate high frequency fluctuations due in particular to switching of the INVP and INVN components.

When the PLL is in balance, the respective durations of activation of the INVP and INVN components of the output signal of the PFD 32 are equal. The PLL is then said to be frequency and phase locked. In this case, the voltage V3 at the input of the low-pass filter 34 appears like the voltage VO of Figure 1. It will be noted that, to within the response times of the logic gates of the PFD, the active edge of the signal FREF then falls in the middle of the measurement window, that is, between the active edges of the signals QA and QB.

The principle of . the invention is illustrated by the timing diagrams of Figure 10, which corresponds to the case of a PLL in balance, that is, frequency and phase locked. In the interests of simplicity, Figure 10 does not take account of the response times of the logic gates of the PFD.

In this figure, the first and second lines show the active edges, in this case, for example, the rising edges, of the divided frequency signals respectively QA and QB. It should be remembered that the time interval between the active edges of QA and those of QB corresponds to the duration of the measurement windows, during which the PFD activates the measurement signal. The third line shows the active edges, in this case, for example, the falling edges, of the reference signal FREF at the comparison frequency f_ref- The fourth line shows the signal INVN-INVP, for three successive measurement windows, respectively #n-2, #n-l and #n. The horizontal arrows each bear an indication of their duration, respectively L_n-₂, L_n_ι, and L_n. The instants corresponding to the active edges of FREF, or comparison instants, are denoted T_n_₂, T_n_ι and T_n. As has already been stated, the comparison instants correspond to the middle of the measurement windows, the PLL being in balance.

The number of cycles of the signal S at high frequency f_vco (not represented) between the start of the measurement window of duration L_n and the end of the preceding measurement window of width L_n_ι is denoted R_n. In an embodiment, the frequency divider is built such that all the numbers R_n are integers. In this way, the delay between the active edge of QA starting a given measurement window and the active edge of QB ending the preceding measurement window can be generated by counting an integer number of cycles of the high frequency signal S.

In the case illustrated by Figure 10, the division factor P_n is a modulo 1/2 number. In other words, the number P_n of cycles of the high frequency signal S between two comparison instants is a modulo 1/2 number. The invention then proposes alternating a measurement window of duration corresponding to an even number Y of cycles of the high frequency signal S, and a measurement window of duration corresponding to an odd number Z of cycles of this signal. In this way, if an active edge of FREF falls on an edge of the signal S for the comparison instant T_n-ι, as in the example represented in Figure 10, the preceding and following active edges of FREF fall between two respective successive edges of the signal S at the comparison instants T_n_₂ and T_n, respectively.

Preferably, Z is equal to Y+l or Y-l. This limits the phase jitter of the signals QA and QB and therefore the risk of loss of frequency locking of the PLL. In the example represented, Y=4 and Z=Y-1=3, the measurement window at the comparison instant T_n_χ is therefore of duration L_n_ι=Y=4, and the measurement windows at the comparison instants T_n_₂ and T_n are of the same duration

L_n-₂ ⁼L_n ⁼Z=3. The following relation is verified for each measurement window: Z Y P„ = - ÷ R. + -

In the example represented, this relation is written: P_n = 1.5 + R_n + 2

Preferably, the sampling frequency of the sigma-delta modulator is equal to the comparison frequency f_ref. In other words, the sigma-delta is driven by the reference signal FREF. Thus, it delivers a value P_n of the division factor for each measurement window. When P_n varies, because of the modulation, the number R_n can vary but remains an integer number. The measurement window has its duration L_n modified from Y to Z, or from Z to Y, relative to the duration L_n-ι of the preceding measurement window provided that P_n is a modulo 1/2 number. When P_n is an integer number, the width L_n of the current measurement window is kept equal to the width L_n-ι of the preceding measurement window.

The diagram in Figure 11 illustrates an exemplary embodiment of the digital frequency divider 31, and the diagrams in Figure 14 illustrate its operation in the case where P=23.5. In this example, the divider 31 comprises a programmable pre-divider 311, a shift register 312, a programmable divider 313, and an algorithmic logic 314.

The programmable pre-divider 311 receives as input the high frequency signal S (first line of Figure 14, in which the vertical arrows denote the rising edges of the signal S, the falling edges of which are not represented) , and delivers as its output a signal QS at the pre-divided frequency (second line of Figure 14) . The division factor of the pre-divider 311 is selectively equal to Y or to Z, depending on the state of a control signal CTRL received from the programmable divider 313. For example, the division factor is equal to Y when CTRL is at 1, and is equal to Z when CTRL is at 0.

The provision of this pre-divider is used as a way to reduce the phase jitter, because digital dividers with variable division factor operating at very high frequencies cannot be constructed.

In practice, the production of the pre-divider 311 as shift register of the signal S, for example, based on D flip-flops, poses no problems. In particular, the output signal QS of the pre-divider is obtained from a D flip-flop which receives the signal S at its clock input and state change conditions at its D input. These conditions are defined in particular by the CTRL command which changes the programming of a state machine. This programming of the pre-division function is dynamic, it takes place before the last division step and, in one example, it changes the duration of the logic 0 level of QS. Advantageously, such a pre- divider does not generate phase noise.

The function of the shift register 312 is to produce the divided frequency signals QA and QB, from the signal QS and an end-of-counting signal FIN_C (seventh line of Figure 14) obtained from the programmable divider 313 and which will be discussed later.

As is shown in Figure 12, which gives an exemplary embodiment of the register 312, the active edges of the signals QA and QB advantageously originate from a shift of the signal FIN_C. The signals QA and QB thus retain roughly the same synchronous delay independently of the division program, which minimizes the phase jitter on the signal S. Ih this embodiment the signal QB is a replica of the signal QA, reproducing each active edge of the signal QA with a delay of a number of cycles of the high frequency signal S which corresponds to the duration L_n of the measurement window. The signals QA and QB are generated, respectively, at the output of a flip-flop 321 receiving the FIN_C signal at its input, and at the output of another flip-flop 322 in series with said flip-flop 321. These are, for example, D flip-flops.

The clock CK_QA_QB from the register 312, which activates the clock inputs of the flip-flops 321 and

322, is obtained from a combination of the signal QS and the signal S in a synchronous logic 323. From the logical point of view, the clock CK_QA_QB (eighth line of Figure 14, on which the vertical arrows denote the rising edges of the clock, the falling edges of which are not represented) roughly corresponds to the falling edges of QS, being synchronized with the signal S.

Thus, no phase jitter affects the synchronism of this clock. Production of the logic 323 is within the scope of a person skilled in the art.

The signal QB remains at the logic 1 level during a window of predefined duration, corresponding, for example, to three cycles of the high frequency signal S. This can be produced simply by providing a shift register (not represented) comprising three D flip- flops in series, the first of which receives the signal QB at the D input, the last of which delivers a signal to reset the flip-flops 321 and 322, and the clock inputs of which receive the signal S.

During the period of activation of QB, that is, during said window in which QB is at the logic 1 level, a pulse of a signal LOAD (eleventh line of Figure 14) is sent from the programmable pre-divider 311 to the programmable divider 313 to reset the sequence. In the example, it is a positive pulse (at the logic 1 level) generated by state decoding on a rising edge of QS. This state decoding performs, for example, the logical operation LOAD=QS+QB, the implementation of which from logic gates (not shown) in the pre-divider 311 is within the scope of a person skilled in the art. In the example, the period of activation of the signal LOAD corresponds to one and a half cycles of the high frequency signal S, which means using a falling edge (not represented) of the high frequency signal S.

The function of the programmable divider 313 is to count the predefined number R_n of cycles of the high frequency signal S between two consecutive measurement windows. In one embodiment, it in fact operates by counting cycles of the pre-divided frequency signal QS, which enables it to operate at a lower frequency. To this end, it receives as input a clock signal CK_R (third line of Figure 14), and delivers as output the above-mentioned end-of-counting signal FIN_C.

The clock signal CK_R corresponds to the result of a logical OR operation between the signals QS and FIN_C, performed in an OR gate 315. In other words, the clock CK_R corresponds to the pre-divided frequency signal QS, inhibited by the end-of-counting signal FIN_C. The programmable divider 31 is therefore inactive during the measurement window. This reduces the power supply noise during the measurement window.

It will be noted that the number R_n of cycles of the high frequency signal S depends on the sum of the cycles of the clock CK_R counted by the programmable divider 313, respectively weighted by the current value Y or Z of the division factor of the pre-divider 311.

It will also be noted that the sequence reset operation takes one cycle of the pre-divided frequency signal QS, following that corresponding to the preceding measurement window. During each of these two cycles, the clock CK_R is inhibited. This is why the period of time between the start of a current measurement window and the end of the preceding measurement window, said period of time corresponding to the number R_n of cycles of the high frequency signal S, can be expressed as the sum of the relevant cycles of the clock CK_R weighted each time by the current value Y or Z of the division factor of the pre-divider 311, and also an additional number of cycles of the signal S corresponding to the value Y or Z of the division factor of the pre-divider 311 immediately after said preceding measurement window.

A number of embodiments of the programmable divider 313 are possible. The one diagrammatically represented in Figure 12 has the advantage of relying on a monotonous cycle count. The cycles counted are. those of the clock signal CK_R. The divider 313 comprises two counters 331 and 332, of programmable capacity respectively M_n and N_n, in which M_n and N_n are integer numbers such that M_n ≥ 2 and N_n > M_n. These counters are each activated by the cycles of the signal CK_R. In an embodiment, they are, in fact, downcounters . In other words, the counter 331 "counts down" from M_n to 0, and the counter 332 "counts down" from N_n to 0.

The values M_n and N_n are delivered by the algorithmic logic 314, such that if the pre-divider 311 begins, for example, by dividing by Z after each measurement window, the following relation applies:

R_n = (M_n + 1) x Z + (N_n - M_n) * Y 1 1 P_n = - * Ln-l + R_n + - x L_n where P_n denotes the current value of the division factor of the frequency divider 31, L_n denotes the duration of the current measurement window, and L_n-ι denotes the duration of the width of the preceding measurement window. In the first relation above giving R_n, the term 1 in the factor before Z corresponds to the cycle of the pre-divided frequency signal QS corresponding to the resetting of the pre-divider 311 and the programmable divider 313, during which the clock CK_R is inhibited.

The values M_n and N_n are loaded into the divider 313, under the control of the LOAD signal from the pre- divider 311, in this case as a programmed starting value of the counters 331 and 332.

In the example represented in Figure 14, the values M_n and N_n are respectively equal to 3 and 5, the values Z and Y are respectively equal to 3 and 4, and the durations L_n_ι and L_n are respectively equal to 3 and 4.

The counters 331 and 332 simultaneously decrement their counting value, .in time with the cycles of CK_R, until they reach the zero value. The fourth and fifth lines of Figure 14 give, for each cycle of the signal CK_R, the counting values respectively Mi and Ni of the counters respectively 331 (which "counts down" from M_n to 0) and 332 (which counts down from N_n to 0) . The end of counting by the counter 331 switches the control signal CTRL to the 1 value. The end of counting by the counter 332 switches the end-of-counting signal FIN_C to the 1 value.

In practice, the programmable divider 313 stores a logical value WIN and reloads the counters 331 and 332 with the values respectively M_n and N_n in response to the signal LOAD. The logical value WIN is 1 to indicate that the next measurement window has a width L equal to Y, in other words 4 in the example. The logical value WIN is 0 to indicate that the next measurement window has a width L equal to Z, in other words 3 in the example. The logical value WIN is received by the programmable divider 313 via a corresponding logic signal (thirteenth line of Figure 14) delivered by the algorithmic logic 314.

If the signal WIN is at 1, the signal CTRL is held at 1 for the period of QS which follows the end-of-counting by the counter 332, then falls to 0, otherwise it falls to 0 at the end of this count.

During each measurement window, the value Y or Z of the division factor of the pre-divider is programmed in the latter, via the signal CTRL, in response to the sampling on the rising edge of QS of the logical product of the signals FIN_C and WIN. It is in this way, in practice, that the duration of the measurement window is controlled.

An advantageous solution for the design of the algorithmic logic consists in using an indexed table. This table describes all the possible states of the frequency divider 31. It has a size that is limited in practice because the number of memory cells is known when a narrow band of frequencies is synthesized. Also, it is very simple to change the content of the table on a large frequency hop.

As an example, the table I below gives, for Z=3 and Y=4, the values of M_n, N_n and L_n for five values P_n of the division factor of the divider 31 respectively equal to 58, 58.5, 59, 59.5 and 60. The value of R_n is given for information. Taking into account the duration L_n-i of the preceding measurement window, the table has five entries for P_n and two entries for L_n_χ. The table can be addressed directly by the output value SD of the sigma-delta modulator 35. In this example, the gain of the sigma-delta modulator is a 1/2.

Table I

There now follows a description of an exemplary program that can be implemented by the algorithmic logic 314 of the frequency divider 31.

It is assumed that the value Po defined above, is known to the program, for example in the form of a predefined table indexed by the possible values of f_vco- These values are, for example, those that the carrier frequency can take according to the chosen radio channel, in an application of the PLL to a digital modulation frequency synthesizer used in a radio

-frequency transmitter.

The deviation values ΔP are determined according to Po and the values SD in the manner illustrated by the flow diagram in Figure 15. If Po is an even number, then 1 1 ΔP - - (SD - 1), otherwise ΔP = - SD. If the 2 2 possible values SD at the output of the sigma-delta modulator are 0, 1 and 2 (in the case of a 1-bit sigma- delta modulator) , then the possible deviation values ΔP are respectively -0.5, 0 and +0.5 in the first case, and 0, +0.5 and +1 in the second case.

The flow diagram of Figure 16 illustrates the steps for determining the duration L_n of the current measurement window according to the duration L_n-ι of the preceding measurement window. If ΔP is an integer number, then L_n=L_n-ι, that is, the measurement windows are of the same duration. Otherwise, L_n is equal to Z if L_n-ι is equal to Y, and vice versa. This means that it is effectively possible to generate a count of a modulo 1/2 number of cycles of the high frequency signal S, with a number R_n which is an integer.

The flow diagram of Figure 17 illustrates the steps for determining the number R_n. It is important to distinguish three cases according to the modulus |ΔP| of the deviation value ΔP. If |ΔP| is zero, then R_n = Po - Ln-i. If 1 ΔP 1 is equal to 1, then R_n = Po - Ln-i + 1. Finally, if |ΔP| is equal to 0.5, it is again important to differentiate a number of cases: if ΔP is negative and if L_n_ι = Z, then R_n = Po - Ln-i - 1; if ΔP is negative and if L_n-ι ≠ Z (therefore if L_n-ι = Y) , or if ΔP is positive and if L_n_ι = Z, then R_n = Po - L_n-ι; finally, if ΔP is positive and L_n-ι ≠ Z (therefore if L_n-ι = Y) , then R_n = Po - Ln-i + 1.

It is possible to check that the algorithm described above with reference to the flow diagrams of Figures 15 to 17 can be used to generate the states described in Table 1, when Z=3 and Y=4.

Claims

1. Phase locked loop, comprising an oscillator (30) controlled to deliver a high frequency signal (S), a digital frequency divider (31) with variable division factor (P) for converting the high frequency signal into a divided frequency signal (QA) , a phase comparator (32) for receiving the divided frequency signal and a reference signal (FREF) and producing a signal (INVP, INVN) measuring a phase difference between the divided frequency signal and the reference signal, and a low-pass filter (34) for controlling the oscillator from the measurement signal, wherein the division factor of the frequency divider can take at least one value corresponding to a modulo 1/2 number, characterized in that it also comprises means (35) for generating, for each active edge of the divided frequency signal, a measurement window of duration (L) defined by counting cycles of the high frequency signal, and in that the phase comparator is configured to activate the measurement signal such that, when the loop is in balance, each active edge of the reference signal falls roughly in the middle of the measurement window, and in that, when a current value of the division factor of the frequency divider is a modulo 1/2 number, the duration of the measurement window for a corresponding cycle (#n-l) of the reference signal corresponds to a given number Y of cycles of the high frequency signal which has a given parity, whereas the duration of the measurement window for a preceding cycle (#n-2) or following cycle (#n) of the reference signal corresponds to a given number Z of cycles of the high frequency signal which has an opposite parity.

2. Phase-locked loop according to Claim 1, wherein the phase comparator is configured to activate the measurement signal on each active edge of the divided frequency signal, such that, when an active edge of the reference signal falls within the measurement window, a first component (INVN) of the measurement signal comprises a positive charge pulse between the start of the measurement window and said active edge of the reference signal and a second component (INVP) of the measurement signal comprises a negative charge pulse between said active edge of the reference signal and the end of the measurement window.

3. Phase-locked loop according to. Claim 1 or Claim 2, wherein the frequency divider comprises a pre- divider with variable pre-division value for converting the high frequency signal into a pre- divided frequency signal (QS) by counting a number of cycles of the high frequency signal which is selectively equal to Y or to Z, and a programmable divider for generating the divided frequency signal by counting cycles of said pre-divided frequency signal.

4. Phase-locked loop according to Claim 3, wherein the programmable divider comprises a first programmable counter of predefined capacity M_n, and a second programmable counter of predefined capacity N_n operating by counting cycles of the pre-divided frequency signal, where M_n and N_n are integer numbers such that M_n ≥ 2 and N_n > M_n which are programmed for each measurement window such that: P_n X L_n

where P_n denotes the current value of the division factor of the frequency divider, L_n denotes the duration of the corresponding measurement window, and L_n-i denotes the duration of the preceding measurement window.

5. Phase-locked loop according to Claim 4, comprising an algorithmic logic for producing, for each measurement window, the values L_n, M_n and N_n according to the value P_n and the stored value L_n_ι.

6. Phase-locked loop according to any one of Claims 1 to 5, wherein Y is equal to 4 and Z is equal to 3.

7. Phase-locked loop according to any one of the preceding claims, wherein the means for generating the measurement window comprise means (312) of producing., a replica (QB) of the divided frequency signal (QA) , reproducing each active edge of the divided frequency signal with a delay of a number of cycles of the high frequency signal which corresponds to the duration of the measurement window.

8. Digital modulation frequency synthesizer comprising: - a phase-locked loop according to any one of Claims 1 to 7; and - a sigma-delta modulator (35) for generating deviation values (ΔP) of the division factor of the digital frequency divider relative to a given integer value (Po) , according to a stream of modulation data (DATA__STR) .

9. Mobile terminal of a radio communications system comprising a digital modulation frequency synthesizer according to Claim 9.