WO2005096486A1

WO2005096486A1 - High-voltage pulse generating circuit

Info

Publication number: WO2005096486A1
Application number: PCT/JP2005/006315
Authority: WO
Inventors: Tatsuhiko Hatano; Takeshi Sakuma
Original assignee: Ngk Insulators, Ltd.
Priority date: 2004-03-31
Filing date: 2005-03-31
Publication date: 2005-10-13
Also published as: JP2005295667A; JP4494066B2

Abstract

A high-voltage pulse generating circuit (10A) comprises an inductor (22) connected in series to both ends (18, 20) of a DC power supply unit (16), a main switch section (24), and a sub-switch (26). The main switch (24) has first parallel-connected three semiconductor switches (28a to 28c), and the sub-switch section (26) has, similarly to the main switch section (24), second parallel-connected three semiconductor switches (30a to 30c). The first semiconductor switches (28a to 28c) are connected to the second semiconductor switches (30a to 30c) in a relation of one-to-one correspondence. A diode section (48) is connected between the gate terminals (42a to 42c) of the first semiconductor switches (28a to 28c) and the other end (46) of the inductor (22). The diode section (48) has parallel-connected three diodes (50a to 50c).

Description

Specification

High voltage pulse generation circuit

Technical field

[0001] The present invention provides a high-voltage, short-pulse and extremely narrow pulse width by releasing electromagnetic energy stored in an inductor from a low-voltage DC power supply with a simple circuit configuration. The present invention relates to a high-voltage pulse generation circuit capable of supplying a pulse. Background art

[0002] Recently, techniques for deodorizing, disinfecting, decomposing harmful gases, and the like have been applied using plasma generated by the discharge of high-voltage pulses. A high-voltage pulse generation circuit that can supply a narrow pulse is required.

[0003] Therefore, conventionally, for example, a high-voltage pulse generation circuit as disclosed in Patent Document 1 has been proposed. As shown in FIG. 21, the high-voltage pulse generating circuit 100 includes an inductor 104, a first semiconductor switch 106, and a second semiconductor switch 108 connected in series at both ends of a DC power supply section 102, and a first semiconductor switch 108. This is a very simple circuit in which a force source is connected to the other end of the inductor 104 whose one end is connected to the anode terminal of the switch 106, and a diode 110 is connected to the gate terminal of the first semiconductor switch 106 so as to be the anode.

[0004] When the second semiconductor switch 108 is turned on, the first semiconductor switch 106 is also turned on, the voltage of the DC power supply unit 102 is applied to the inductor 104, and the induced energy is accumulated in the inductor 104. . After that, when the second semiconductor switch 108 is turned off, the first semiconductor switch 106 is also turned off rapidly, so that the inductor 104 rises very steeply, and has a very narrow width! High voltage pulse Po can be extracted from terminals 112 and 114.

[0005] According to this high-voltage pulse generation circuit 100, a high-voltage pulse having a steep rise time and an extremely narrow pulse width can be obtained with a simple circuit configuration without using a plurality of semiconductor switches to which a high voltage is applied. Po can be supplied.

Patent Document 1: Japanese Patent Application Laid-Open No. 2004-72994

Disclosure of the invention Problems the invention is trying to solve

[0006] However, in the high-voltage pulse generation circuit 100 described above, the output of the high-voltage pulse Po may be limited by the current capacities of the first semiconductor switch 106, the second semiconductor switch 108, and the diode 110. is there.

According to the present invention, by further improving the above-described high-voltage pulse generating circuit, it is possible to supply a high-voltage pulse having a steep rise time and an extremely narrow pulse width with a simple circuit configuration, Further, it is an object of the present invention to provide a high-voltage pulse generation circuit capable of achieving high capacity and increasing the output of high-voltage pulses.

Another object of the present invention is to provide, in addition to the above objects, a high-voltage noise generation circuit capable of achieving high-speed operation and improving power supply performance. It is to do.

Means for solving the problem

[0009] A high-voltage pulse generating circuit according to the present invention has an inductor, a main switch, and a sub-switch connected in series at both ends of a DC power supply, and the main switch includes a plurality of first semiconductors. One end of the inductor is connected to a node terminal of the first semiconductor switch, and the sub-switch portion has at least one second semiconductor switch, and one end of the first semiconductor switch. A diode portion is connected between a gate terminal and the other end of the inductor, the diode portion has an anode terminal connected to the gate terminal of the first semiconductor switch, and a force source terminal connected to the other end of the inductor. It has at least one diode.

[0010] That is, in the present invention, the main switch section has a plurality of first semiconductor switches. Therefore, it is possible to supply a high-voltage pulse having a steep rise time and an extremely narrow pulse width with a simple circuit configuration, use a small-capacity semiconductor element, and increase the output of the high-voltage pulse. Can be.

[0011] In the configuration, the inductor has a plurality of windings, and the first semiconductor switch and the windings have a one-to-one, many-to-one, or a one-to-many, or They may be connected in a combination of these combinations.

[0012] The main switch having a plurality of first semiconductor switches may include an inductor and a first semiconductor switch. There will be a fork between the body switch. Therefore, if there is a resistance variation in the wiring between the branch point and each of the first semiconductor switches, the current flowing through each of the first semiconductor switches may be varied.

However, in the present invention, each first semiconductor switch and each winding are connected in one-to-one, many-to-one, or one-to-many, or a combination, so that the branching is performed. There is no point, and the resistance of each winding is added as the resistance of the wiring. In this case, the resistance value of the wiring from each winding to each first semiconductor switch and the resistance value of each winding are in the relationship of wiring resistance value <<resistance value of the winding wire. Even if there is resistance variation in the wiring from the first semiconductor switch to the first semiconductor switch, the variation has almost no effect, and the current flowing through each first semiconductor switch hardly varies.

[0014] Further, in the above configuration, the first semiconductor switch and the second semiconductor switch may be connected to each other in a force pair, a many-to-one, or a one-to-many relationship, or a combination thereof.

[0015] In this case, one or more second semiconductor switches corresponding to the respective first semiconductor switches are turned off so that the respective off points of the plurality of first semiconductor switches are substantially the same. It is preferable that the timing of the adjustment be adjusted.

[0016] It is difficult to make the characteristics of the first semiconductor switches in the main switch section exactly the same. Therefore, for example, when it is assumed that the charge is extracted after the turn-off is started in each first semiconductor switch, the storage time until each first semiconductor switch is completely turned off is equal to the first semiconductor switch. Differs for semiconductor switches. Therefore, for example, when two first semiconductor switches are considered, if one first semiconductor switch is turned off, current flows only to the remaining first semiconductor switches, resulting in loss or loss. Power of reliability Not desirable.

[0017] Therefore, in the present invention, the timing at which each of the second semiconductor switches is turned off is adjusted so that each of the plurality of first semiconductor switches has substantially the same off time. Such an uneven current flow hardly occurs, and low loss and reliability can be improved. [0018] In the above configuration, the diode section may be configured such that the first semiconductor switch and the diode are in a one-to-one relationship, a many-to-one relationship, a one-to-many relationship, or a combination thereof. You can be connected.

In this case, the first semiconductor switches and one or one corresponding to each of the first semiconductor switches are so set that the off points of the plurality of first semiconductor switches are substantially the same. The wiring between the plurality of diodes is preferably adjusted in impedance.

The impedance is an inductance component or a resistance component between each of the first semiconductor switches and one or a plurality of diodes corresponding to each of the first semiconductor switches, or a combination thereof. May be! / ,.

[0021] Alternatively, the first semiconductor switches and one or more corresponding to each of the first semiconductor switches are so set that the off points of the plurality of first semiconductor switches are substantially the same. It is preferable that the diode has a forward voltage or a forward recovery voltage that is adjusted.

[0022] In the above configuration, the sub-switch portion includes a plurality of the second semiconductor switches, and the main switch portion and the sub-switch portion are connected via a common contact. It may be. Alternatively, the diode section may include a plurality of the diodes, and the main switch section and the diode section may be connected via a common contact. Of course, the sub-switch has a plurality of the second semiconductor switches, the diode has a plurality of the diodes, and the main switch and the sub-switch have a first common contact. And the main switch unit and the diode unit may be connected via a second common contact.

Note that the first semiconductor switch may be an electrostatic induction thyristor! Further, the second semiconductor switch may be a metal oxide semiconductor field effect transistor for power.

As described above, the high voltage pulse generation circuit according to the present invention has the following effects.

[0025] (1) With a simple circuit configuration, a high voltage having a sharp rise time and an extremely narrow pulse width A semiconductor element which can supply a pressure pulse and has a small capacity can be used, and the output of a high-voltage pulse can be increased.

(2) The operating speed can be increased, and the power supply performance can be improved.

Brief Description of Drawings

FIG. 1 is a circuit diagram showing a high-voltage pulse generating circuit according to a first embodiment.

FIG. 2A to FIG. 2C are diagrams illustrating operation waveforms of voltage and current of each unit of the high-voltage pulse generation circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing a high-voltage pulse generating circuit according to a second embodiment.

FIG. 4 is a circuit diagram showing a high-voltage pulse generating circuit according to a third embodiment.

FIG. 5 is a circuit diagram showing a high-voltage pulse generating circuit according to a fourth embodiment.

FIG. 6 is a circuit diagram showing a high-voltage pulse generation circuit according to a fifth embodiment.

FIG. 7 is a circuit diagram showing a high-voltage pulse generation circuit according to a sixth embodiment.

FIG. 8 is a circuit diagram showing a high-voltage pulse generation circuit according to a seventh embodiment.

FIG. 9 is a circuit diagram showing a high-voltage pulse generation circuit according to an eighth embodiment.

FIG. 10 is a diagram for explaining a current balance in a high-voltage pulse generating circuit according to a fourth embodiment.

[FIG. 11] FIG. 11 illustrates a variation in current when two first semiconductor switches are turned on and a variation in extraction current when two first semiconductor switches are turned off. FIG.

FIG. 12 is a diagram for explaining variation in wiring resistance between an inductor and a main switch part.

FIG. 13 is a circuit diagram showing a high-voltage pulse generation circuit according to a first modification.

FIG. 14 is a circuit diagram showing a high-voltage pulse generation circuit according to a second modification.

[FIG. 15] FIG. 15 is a waveform diagram for explaining variation in extraction current when two first semiconductor switches are turned off.

FIG. 16 is a circuit diagram showing a high-voltage pulse generation circuit according to a third modification.

[FIG. 17] FIG. 17 is a waveform diagram for explaining a state in which the turn-off start time of one of the first semiconductor switches is delayed to balance the extraction current. FIG. 18 is a circuit diagram showing a high-voltage pulse generation circuit according to a fourth modification.

FIG. 19 is a circuit diagram showing a high-voltage pulse generation circuit according to a fifth modification.

FIG. 20 is a circuit diagram showing a high-voltage pulse generation circuit according to a sixth modification.

FIG. 21 is a diagram showing a high-voltage pulse generation circuit according to a conventional technique.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of a high-voltage pulse generating circuit according to the present invention will be described with reference to FIGS. 1 to 20.

First, as shown in FIG. 1, the high-voltage pulse generating circuit 10 A according to the first embodiment includes two ends 18 and 18 of a DC power supply unit 16 having a DC power supply 12 and a capacitor 14 for reducing high-frequency impedance. An inductor 22, a main switch 24, and a sub-switch 26 are connected in series to 20.

The main switch section 24 has three first semiconductor switches 28a to 28c arranged in parallel, and the 畐 ij switch section 26 also has three second semiconductor switches arranged in parallel similarly to the main switch section 24. Semiconductor switches 30a to 30c. The three first semiconductor switches 28a to 28c and the three second semiconductor switches 30a to 30c are respectively connected in a one-to-one relationship. When a plurality of first semiconductor switches 28a, 28b,... Are collectively referred to as a first semiconductor switch 28, a plurality of second semiconductor switches 30a, 30b,. Is referred to as a second semiconductor switch 30.

[0031] The inductor 22 has a transformer 36 having a primary winding 32 and a secondary winding 34, and a high-voltage pulse Po is output from both ends 38 and 40 (output terminals) of the secondary winding 34 of the transformer 36. They are being taken out. Although not shown, a resistance load or a capacitive load is connected to the output terminals 38 and 40 of the secondary winding 34. The one end 44 of the inductor 22 (the one end of the primary winding 32) is connected to the anode terminal of each of the first semiconductor switches 28a to 28c.

Further, a diode section 48 is connected between the gate terminals 42 a to 42 c of the first semiconductor switches 28 a to 28 c and the other end 46 of the inductor 22. The diode section 48 has three diodes 50a to 50c arranged in parallel, and three first semiconductor switches 28a to 28c are connected to the three diodes 50a to 50c in a one-to-one relationship. . Multiple diodes 50a, 50b · · · · Is collectively referred to as diode 50.

In the example of FIG. 1, three second semiconductor switches 30a to 30c are provided on the negative terminal 20 side of the DC power supply unit 16, but the same effect can be obtained by providing them on the positive terminal 18 side. Needless to say. Also, the output may be taken out from both ends of the main switch section 24, not from the inductor 22.

[0034] Each of the second semiconductor switches 30a to 30c of the sub-switch section 26 has a force capable of using a self-extinguishing or commutation-extinguishing device. In this example, an avalanche diode is built in antiparallel. And a power metal oxide semiconductor field effect transistor. A common control signal S1 is provided between each gate terminal and a source terminal of the three second semiconductor switches 30a to 30c, and individual control signals Sa to Sc are supplied.

As each of the first semiconductor switches 28a to 28c of the main switch section 24, a current control type device or a self-extinguishing type or a commutation extinguishing type device can be used. In the present embodiment, an SI thyristor having a very high withstand voltage against a voltage rise rate (dvZdt) at turn-off and a high voltage rating is used.

Next, the circuit operation of the high-voltage pulse generating circuit 10A according to the first embodiment will be described with reference to the circuit diagram of FIG. 1 and the waveform diagrams of FIGS. 2A to 2C.

First, at time tO, a control signal is supplied between the gate and the source of each of the second semiconductor switches 30a to 30c, so that each of the second semiconductor switches 30a to 30c is turned on.

At this time, due to the extremely large impedance of the opposite polarity of each of the diodes 50 a to 50 c in the diode section 48, each of the first semiconductor switches 28 a to 28 c is caused by the electric field effect applied between the gate and the force sword. Turn on each one. Since the rise of the anode current of each of the first semiconductor switches 28a to 28c is suppressed by the inductor 22, normal turn-on can be performed only by the electric field effect.

As described above, when each of the second semiconductor switches 30a to 30c and each of the first semiconductor switches 28a to 28c conduct at time tO, a voltage substantially equal to the voltage V of the DC power supply 12 is applied to the transformer 36. Assuming that the primary inductance of the transformer 36 is L, as shown in FIG. 2A, the current II flowing through the primary winding 32 of the transformer 36 has a gradient (VZL) and is linear with time. To increase.

[0040] Then, during a period Ton in which each of the first semiconductor switches 28a to 28c is on, a constant negative voltage (negative pulse Pn) is applied to the output terminals 38 and 40 of the secondary winding 34. Is output. Assuming that the power supply voltage of the DC power supply 12 is V and the turns ratio of the transformer 36 (the number of turns n2Z of the secondary winding 34—the number of turns nl of the next winding 32) is n, the output of the secondary winding 34 The level of the output voltage Vo appearing at the terminals 38 and 40 is nV (Vo = —nV). During this period Ton, the waveform of the current 12 flowing through the secondary winding 34 also has a waveform similar to the negative polarity pulse Pn (see FIG. 2B).

Thereafter, at time tl, the supply of the control signal between the gate and the source of each of the second semiconductor switches 30a to 30c is stopped, so that each of the second semiconductor switches 30a to 30c is turned off, and each of the second semiconductor switches 30a to 30c is turned off. The current from the force switch of the semiconductor switches 28a to 28c is also zero, that is, it is in an open state, so that the current II flowing through the primary winding 32 is cut off, and the primary winding 32 is subjected to the back electromotive force due to the residual electromagnetic energy. Each of the diodes 50a to 50c acts, and the current II of the primary winding 32 changes from the anode terminal of each of the first semiconductor switches 28a to 28c to the gate of each of the first semiconductor switches 28a to 28c. The terminals 42a to 42c → the anodes of the respective diodes 50a to 50c → commutate to the path composed of the power source of the respective diodes 50a to 50c. At this time, the generation of the high voltage pulse Po to the output terminals 38 and 40 starts, and the output voltage Vo rises sharply due to the induced electromotive force generated in the transformer 36. Then, at time t2 when each of the first semiconductor switches 28a to 28c is turned off and the current II becomes zero, the high voltage pulse Po peaks.

[0042] The peak value of the high-voltage pulse Po is represented by n as the turns ratio of the transformer 36, L as the primary inductance of the transformer 36, and (diZdt) as the breaking speed of the current II flowing through the primary winding 32 of the transformer 36. Then, nLl (diZdt). This is the same as the anode-to-sword voltage V of the main switch 24.

AK

The peak value of the high voltage pulse Po becomes nV, and the anode

AK

It becomes a voltage higher than the withstand voltage of the inter-node voltage V. Also, each of the first semiconductor switches 28a to 28c

AK

Assuming that the equivalent capacitance of the total electric capacity of C is C, the pulse width Tp of the high-voltage pulse Po is

[0043] [number 1]

It becomes.

As described above, in the high-voltage pulse generation circuit 10A according to the first embodiment, first, with a simple circuit configuration, the high-voltage pulse Po having a steep rise time and an extremely narrow pulse width is supplied. can do. Then, three first semiconductor switches 28a to 28c are provided in parallel with the main switch part 24, and three second semiconductor switches 30a to 30c are respectively provided corresponding to the first semiconductor switches 28a to 28c. Since the three diodes 50a to 50c are connected, the current capacity of each of the main switch section 24, the sub-switch section 26, and the diode section 48 can be increased, and as a result, the output of the high-voltage pulse Po increases. It can be done. In addition, a semiconductor switch having a small capacity can be used as each of the first semiconductor switches 28a to 28c, so that the operation speed can be increased and the power supply performance can be improved.

Next, high voltage pulse generating circuits 10B to L0H according to some other embodiments will be described with reference to FIGS.

First, as shown in FIG. 3, the high-voltage pulse generating circuit according to the second embodiment has substantially the same configuration as the high-voltage pulse generating circuit 10A according to the above-described first embodiment. However, they differ in the following points.

[0047] That is, the main switch section 24 has four first semiconductor switches 28a to 28d. The sub-switch section 26 has two second semiconductor switches 30a and 30b, and the four first semiconductor switches 28a to 28d of the main switch section 24 and the two second semiconductor switches 30a and 30b are respectively 2 They are connected in a one-to-one relationship.

[0048] Specifically, the force source terminals of the two first semiconductor switches 28a and 28b are connected to one of the second semiconductor switches 30a via contacts, and the other two first semiconductor switches 28a and 28b are connected to each other. Each of the force source terminals 28c and 28d is connected to the other second semiconductor switch 30b via a contact.

[0049] The diode section 48 has four diodes 50a to 50d, and these four diodes 50a -50d and the four first semiconductor switches 28a-28d are connected in a one-to-one relationship.

Next, as shown in FIG. 4, the high-voltage pulse generation circuit 10 C according to the third embodiment has a configuration substantially similar to that of the high-voltage pulse generation circuit 10 A according to the first embodiment described above. However, they differ in the following points.

That is, the main switch section 24 has two first semiconductor switches 28a and 28b.

畐 The IJ switch section 26 has four second semiconductor switches 30a to 30d, and the two first semiconductor switches 28a and 28b of the main switch section 24 and the four second semiconductor switches 30a to 30d respectively. They are connected in a one-to-two relationship.

Specifically, the force source terminals of one first semiconductor switch 28a are connected to two second semiconductor switches 30a and 30b via contacts, and each of the other first semiconductor switch 28b A force source terminal is connected to the other two second semiconductor switches 30c and 30d via contacts.

The diode section 48 has two diodes 50a and 50b, and these two diodes 50a and 50b are connected to the two first semiconductor switches 28a and 28b in a one-to-one relationship. .

Next, as shown in FIG. 5, a high-voltage pulse generating circuit 10D according to the fourth embodiment has a configuration substantially similar to that of the high-voltage pulse generating circuit 10A according to the above-described first embodiment. However, they differ in the following points.

The sub-switch section 26 has two second semiconductor switches 30a and 30b, and the two first semiconductor switches 28a and 28b of the main switch section 24 and the two second semiconductor switches 30a and 30b respectively. They are connected in a one-to-one relationship. The diode section 48 has four diodes 50al, 50a2, 50bl, and 50b2, and two diodes (50al, 50a2) and (50bl, 50b2) respectively correspond to the first semiconductor switches 28a and 28b. It is connected.

Next, as shown in FIG. 6, the high-voltage pulse generation circuit 10E according to the fifth embodiment has substantially the same configuration as the high-voltage pulse generation circuit 10D according to the above-described fourth embodiment. To However, the difference is that the diode section 48 has one diode 50, and the one diode 50 is commonly connected to the two first semiconductor switches 28a and 28b.

In the first embodiment, the connection relation between the first semiconductor switch 28 and the second semiconductor switch 30 is one-to-one, and the connection relation between the first semiconductor switch 28 and the diode 50 is one. In the second embodiment, the connection relationship between the first semiconductor switch 28 and the second semiconductor switch 30 is many-to-one, and in the third embodiment, the first semiconductor switch 28 The connection relationship between the first semiconductor switch 28 and the second semiconductor switch 30 is one-to-many, and the connection relationship between the first semiconductor switch 28 and the second semiconductor switch 30 is many-to-one. , One-to-one and one-to-many combinations, or many-to-one and one-to-many combinations.

Next, as shown in FIG. 7, the high-voltage pulse generating circuit 10F according to the sixth embodiment has a configuration substantially similar to that of the high-voltage pulse generating circuit 10D according to the above-described fourth embodiment. However, they differ in the following points.

That is, the cathode terminals of the two first semiconductor switches 28a and 28b in the main switch section 24 are connected via the contact 60, and the two second semiconductor switches 30a and 30b in the sub-switch section 26 are connected. The drain terminal is connected via a contact 62, and the contact 60 and the contact 62 are shared to form a common contact 64. That is, the main switch section 24 and the sub switch section 26 are connected via the common contact 64.

The diode section 48 has two diodes 50a and 50b, and the two diodes 50a and 50b are connected to the two first semiconductor switches 28a and 28b in a one-to-one relationship.

Next, as shown in FIG. 8, the high-voltage pulse generation circuit 10G according to the seventh embodiment has a configuration substantially similar to that of the high-voltage pulse generation circuit 10D according to the fourth embodiment described above. However, they differ in the following points.

[0062] That is, the diode section 48 has two diodes 50a and 50b, and the anode terminal of one diode 50a is connected to the gate terminal 42a of the first semiconductor switch 28a of the main switch section 24. The anode terminal of the other diode 50b is connected to the gate terminal 42b of the other first semiconductor switch 28b via a contact 66b. It is. Further, the contact 66a and the contact 66b are shared to form a common contact 66. That is, the main switch portion 24 and the diode portion 48 are connected via the common contact 66.

Next, as shown in FIG. 9, the high-voltage pulse generation circuit 10H according to the eighth embodiment is different from the high-voltage pulse generation circuit according to the sixth embodiment and the seventh embodiment. It has a configuration in which such a high-voltage pulse generation circuit is combined.

That is, the main switch section 24 and the sub-switch section 26 are connected via the common contact 64, and the main switch section 24 and the diode section 48 are connected via the common contact 66.

The high-voltage pulse generating circuits 10 B and 10 B according to the above-described second to eighth embodiments: LOH as well as the high-voltage pulse generating circuit 10 A according to the above-described first embodiment. It is possible to supply a high-voltage pulse having a pulse width with a steep rise time and a very narrow width with a simple circuit configuration, to achieve a large capacity, and to increase the output of a high-voltage pulse. Can be. In addition, the operation speed can be increased, and the power supply performance can be improved.

By providing the plurality of first semiconductor switches 28a and 28b in the main switch section 24, there is a possibility that the following current imbalance may occur.

For example, a description will be given based on the high-voltage pulse generating circuit 10 D according to the fourth embodiment shown in FIG. 10 and the waveform diagram of FIG. 11, first, the period Ton shown in FIG. During the period when the two first semiconductor switches 28a and 28b are conducting and energy is stored, the currents Ial and Ibl flowing through the two first semiconductor switches 28a and 28b (the anode terminal force is also applied to the force source terminal). Values may vary.

In the period Toff shown in FIG. 11, that is, during the period in which the two first semiconductor switches 28a and 28b in the main switch section 24 are turned off, the current in each of the first semiconductor switches 28a and 28b Due to the difference in the breaking behavior, variations may occur in the extraction currents Ia2 and Ib2 (the anode terminal force and the gate terminal) in each of the first semiconductor switches 28a and 28b.

First, the current I in the period Ton during which the first semiconductor switches 28a and 28b are conducting is As shown in FIG. 12, variations in al and Ibl are caused by the resistance value (accurately, impedance) Ra of the wiring 72a from one end 44 of the inductor 22 to the anode terminal of one of the first semiconductor switches 28a, and the inductor 22 It is considered that the variation from the resistance value (impedance) Rb of the wiring 72b from one end 44 of the first semiconductor switch 28b to the anode terminal of the other first semiconductor switch 28b is greatly involved.

For example, when the diameter of the wiring 72a is 2 mm ² , the length is 50 mm, and the diameter of the wiring 72b is 2 mm ² and the length is 60 mm, the resistance values Ra and Rb are proportional to the lengths of the wirings 72a and 72b. Therefore, the difference between the resistance values Ra and Rb is 20%, and the distribution of the currents Ial and Ibl flowing through the two first semiconductor switches causes a difference of 20%.

Therefore, by appropriately adjusting the values of these wiring resistances Ra and Rb, it is considered that the variation of the currents Ial and Ibl can be suppressed. The values of these wiring resistances Ra and Rb are different from those of other wirings. Since the resistance value is smaller than the resistance value, the adjustment itself is extremely difficult. In particular, when the number of the first semiconductor switches constituting the main switch section 24 is large in parallel, the wiring distances may not be uniform due to structural restrictions and the like. There is a limit.

Therefore, in the high-voltage pulse generating circuit 10a according to the first modification, as shown in FIG. 13, the number of primary windings 32 is the same as the number of the first semiconductor switches in the main switch section 24. (In this example, the first primary winding 32a and the second primary winding 32b) are configured in parallel, and the two windings 32a and 32b and the two first semiconductor switches 28a and 28b Are connected in a one-to-one relationship.

As a result, the wiring resistance Ra between one of the first semiconductor switches 28a and the first primary winding 32a is significantly smaller than the wiring resistance Rc of the first primary winding 32a. The wiring resistance Rb between the first semiconductor switch 28b and the second primary winding 32b is significantly smaller than the wiring resistance Rd of the second primary winding 32b. The deviation between the wiring resistances Ra and Rb is almost negligible, and easily balances the current la1 flowing through one first semiconductor switch 28a with the current lb1 flowing through the other first semiconductor switch 28b. It comes out.

For example, the length of the first and second primary windings 32a and 32b is 800 mm, and the diameter of the wiring 72a is 2 mm ^2, the length and 50 mm, when the diameter of the wires 72b and 2 mm ^2, a length of 60 mm, the deviation of the resistance value including the first and second primary卷線32a and 32b, 1.25% And the deviation of the currents la 1 and Ibl is almost eliminated.

In the first modified example, the two windings 32a and 32b and the two first semiconductor switches 28a and 28b are connected in a one-to-one relationship, respectively. Like the high-voltage pulse generating circuit 10b according to the second modification, the four first semiconductor switches are connected to the main switch unit 24 in the same manner as the high-voltage pulse generating circuit 10B according to the above-described second embodiment. The switches 28a to 28d may be provided to connect the two windings 32a and 32b to the four first semiconductor switches 28a to 28d in a one-to-two relationship.

Of course, the relationship between the main switch portion 24 and the sub-switch portion 26 and the relationship between the main switch portion 24 and the diode portion 48 are different from those in the second embodiment and the third embodiment described above. A configuration similar to that of the high-voltage pulse generation circuit 10C to the high-voltage pulse generation circuit 10H according to the eighth embodiment may be adopted.

Next, the variation of the currents Ia2 and Ib2 during the period Toff when the two first semiconductor switches 28a and 28b in the main switch section 24 are turned off, as shown in FIG. This is due to the variation in the storage time of the switches 28a and 28b. The storage time is, for example, with respect to one of the first semiconductor switches 28a, from the time when the corresponding second semiconductor switch 30a is turned off, is accumulated in the first semiconductor switch 28a! This is the time until the charge becomes zero. The same applies to the other first semiconductor switch 28b.

For example, as shown in FIG. 15, from the state where the two first semiconductor switches 28a and 28b are conducting and the currents Ial and Ibl flow together, If the other semiconductor switches 30a and 30b are turned off at the same time, the two first semiconductor switches 28a and 28b will be turned off at the same time. That is, the storage time starts. From this time ti, the anode of each first semiconductor switch 28a and 28b → the gate of each first semiconductor switch 28a and 28b → the anode of each diode (50al, 50a2) and (50bl, 50b2) → each diode (50al, 50a2) and (50bl, 50b2) The reflux (the flow of the Ia currents Ia2 and Ib2) occurs in two paths composed of the force swords, At each of the first semiconductor switches 28a and 28b, the charge is extracted.

Here, when the storage time Tstl of one first semiconductor switch 28a is shorter than the storage time Tst2 of the other first semiconductor switch 28b, first, the first semiconductor switch 28a At 28a, the charge becomes zero and the storage time Tstl ends, and at time tl2, the first semiconductor switch 28a is turned off. Therefore, after that, during the period Tb until the remaining first semiconductor switch 28b is turned off, a larger extraction current Ib2 than in the start of turn-off suddenly flows through only the first semiconductor switch 28b, The power of loss and reliability is also not preferable.

Therefore, in the high-voltage pulse generating circuit 10c according to the third modified example shown in FIG. 16, an individual circuit is provided between each gate terminal and the source terminal of the two second semiconductor switches 30a and 30b. The control signals Sa and Sb are configured to be supplied. Then, as shown in FIG. 17, of the two first semiconductor switches 28a and 28b, one second semiconductor switch 30a corresponding to, for example, one of the first semiconductor switches 28a having a short storage time is turned off. The timing for turning off the second semiconductor switch 30b is set to be slightly later than the timing for turning off the second semiconductor switch 30b.

[0081] Thus, the timings at which the two first semiconductor switches 28a and 28b are turned off (the end times of the respective storage times Tstl and Tst2) can be set to be substantially the same, and the other first semiconductor switches 28a and 28b can be set to be substantially the same. It is possible to avoid the disadvantage that a large extraction current Ib2 flows only in the switch 28b. This leads to reduced losses and improved reliability.

As another configuration, for example, as in a high-voltage pulse generation circuit 10d according to a fourth modification shown in FIG. 18, two diodes corresponding to the gate terminal 42a of one first semiconductor switch 28a Between the inductance component La of the wiring 70a between the common anode terminal of 50al and 50a2 and the common anode terminal of the two diodes 50b 1 and 50b2 corresponding to the gate terminal 42b of the other first semiconductor switch 28b. Adjust the inductance component Lb of the wiring 70b. The adjustment includes changing the length of the wiring 70a and the length of the wiring 70b. As a result, for example, the extraction current Ia2 of one of the first semiconductor switches 28a can be delayed, and the timing of turning off the two first semiconductor switches 28a and 28b (the end times of the respective storage times Tstl and Tst2) is substantially the same. Can be set to As another configuration, for example, as in a high-voltage pulse generation circuit 10e according to a fifth modified example shown in FIG. 19, two diodes corresponding to the gate terminal 42a of one first semiconductor switch 28a The resistance component ra and inductance component La of the wiring 70a between the common anode terminal of 50al and 50a2 and the common anode terminal of the two diodes 50bl and 50b2 corresponding to the gate terminal of the other first semiconductor switch 28b. The resistance component rb and the inductance component Lb of the wiring 70b between them are adjusted. Also in this case, for example, the extraction current Ia2 of one of the first semiconductor switches 28a can be delayed, and the two first semiconductor switches 28a and 28b are turned off (at the end of each of the storage times Tstl and TsT2). Can be set to be almost the same.

Of course, by adjusting only the resistance component m of the wiring 70a and the resistance component rb of the wiring 70b, for example, the extraction current Ia2 of one of the first semiconductor switches 28a is delayed.

As another configuration, for example, as in a high-voltage pulse generation circuit 10f according to a sixth modification example shown in FIG. 20, two diodes (first and second diodes) having different forward voltage or forward recovery voltage are provided. Diodes 50A and 50B), for example, a first diode 50A is connected to one of the first semiconductor switches 28a, and a second diode is connected to the other first semiconductor switch 28b. Connect 50B. Since the forward voltage or the forward recovery voltage of each diode 50A and 50B is different, for example, the bow I extraction current Ia2 of one first semiconductor switch 28a can be delayed, and the two first semiconductor switches 28a and The timing of 28b off (the end time of each storage time Tstl and Tst2) can be set to be almost the same.

[0086] Of course, three diodes having the same characteristics are prepared. For example, two diodes are connected in series corresponding to one first semiconductor switch 28a, and one diode is connected to the other first semiconductor switch 28b. Two diodes may be connected. According to this, for example, the pull-out current Ia2 of one of the first semiconductor switches 28a can be delayed.

[0087] The high-voltage pulse generating circuit according to the present invention is not limited to the above-described embodiment, but may, of course, adopt various configurations without departing from the gist of the present invention.

Claims

The scope of the claims

[1] Inductor (22) connected in series to both ends (18, 20) of DC power supply (16), main switch

(24) and a sub-switch part (26),

The main switch part (24) has a plurality of first semiconductor switches (28),

One end (44) of the inductor (22) is connected to the anode terminal of the first semiconductor switch (28),

The sub-switch section (26) has at least one second semiconductor switch (30), and a diode section is provided between a gate terminal of the first semiconductor switch and the other end (46) of the inductor (22). (48) is connected,

The diode section (48) has at least one anode terminal connected to the gate terminal of the first semiconductor switch (28) and a force source terminal connected to the other end (46) of the inductor (22). A high-voltage pulse generating circuit having two diodes (50).

[2] The high-voltage pulse generating circuit according to claim 1,

The inductor (22) has a plurality of windings,

A high-voltage pulse generating circuit, wherein the first semiconductor switch (28) and the winding are connected in a one-to-one, a many-to-one, a one-to-many, or a combination thereof. .

[3] The high-voltage pulse generating circuit according to claim 1 or 2,

The sub-switch part (26)

The first semiconductor switch (28) and the second semiconductor switch (30) are connected in a one-to-one, a many-to-one, a one-to-many, or a combination thereof. High voltage pulse generation circuit.

[4] The high-voltage pulse generating circuit according to claim 3, wherein

One or more second semiconductor switches (30) corresponding to each of the first semiconductor switches (28) are so arranged that the off points of the plurality of first semiconductor switches (28) are substantially the same. A high-voltage pulse generating circuit, characterized in that the timing of turning off each is adjusted.

[5] The high-voltage pulse generating circuit according to any one of claims 1 to 4, The diode section (48)

A high voltage, wherein the first semiconductor switch (28) and the diode (50) are connected in a one-to-one, a many-to-one, a one-to-many, or a combination thereof. Pulse generation circuit.

[6] The high-voltage pulse generating circuit according to claim 5,

Each of the first semiconductor switches (28) and one corresponding to each of the first semiconductor switches (28) such that the off-points of the plurality of first semiconductor switches (28) are substantially the same. Alternatively, the wiring between the plurality of diodes (50) is adjusted in impedance, and the high voltage noise generation circuit is characterized in that the impedance is adjusted.

[7] The high-voltage pulse generating circuit according to claim 6,

The impedance is

There is an inductance component or a resistance component between each of the first semiconductor switches (28) and one or more diodes (50) corresponding to each of the first semiconductor switches (28). A high voltage pulse generation circuit characterized by a combination of these.

[8] The high-voltage pulse generating circuit according to claim 5,

Each of the first semiconductor switches (28) and one corresponding to each of the first semiconductor switches (28) such that the off-points of the plurality of first semiconductor switches (28) are substantially the same. Alternatively, the plurality of diodes (50) have a forward voltage or a forward recovery voltage adjusted, and a high-voltage noise generation circuit is characterized in that the forward voltage or the forward recovery voltage is adjusted.

[9] The high-voltage pulse generating circuit according to claim 1 or 2,

The sub-switch part (26) has a plurality of the second semiconductor switches (30), and the main switch part (24) and the sub-switch part (26) are connected via a common contact.

V, a high-voltage pulse generation circuit.

[10] The high-voltage pulse generating circuit according to claim 1 or 2,

The diode unit (48) has a plurality of the diodes (50),

The main switch part (24) and the diode part (48) are connected via a common contact.

V, a high voltage pulse generation circuit characterized by: [11] The high-voltage pulse generating circuit according to claim 1 or 2,

The sub-switch unit (26) has a plurality of the second semiconductor switches (30), the diode unit (48) has a plurality of the diodes (50),

The main switch part (24) and the sub switch part (26) are connected via a first common contact,

A high-voltage pulse generating circuit, wherein the main switch section (24) and the diode section (48) are connected via a second common contact.

[12] The high-voltage pulse generating circuit according to any one of claims 1 to 1, wherein

The high voltage pulse generation circuit according to claim 1, wherein the first semiconductor switch (28) has an electrostatic induction thyristor.

[13] The high-voltage pulse generating circuit according to any one of claims 1 to 12,

The high voltage pulse generation circuit according to claim 2, wherein the second semiconductor switch (30) includes a power metal oxide semiconductor field effect transistor.