WO2005081769B1 - Nor-type channel-program channel-erase contactless flash memory on soi - Google Patents
Nor-type channel-program channel-erase contactless flash memory on soiInfo
- Publication number
- WO2005081769B1 WO2005081769B1 PCT/US2005/002655 US2005002655W WO2005081769B1 WO 2005081769 B1 WO2005081769 B1 WO 2005081769B1 US 2005002655 W US2005002655 W US 2005002655W WO 2005081769 B1 WO2005081769 B1 WO 2005081769B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gate
- memory cells
- eeprom memory
- column
- semiconductor device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims abstract 26
- 210000000746 body regions Anatomy 0.000 claims abstract 9
- 239000012212 insulator Substances 0.000 claims abstract 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 11
- 229910052710 silicon Inorganic materials 0.000 claims 11
- 239000010703 silicon Substances 0.000 claims 11
- 238000009413 insulation Methods 0.000 claims 10
- 238000000151 deposition Methods 0.000 claims 6
- 238000005530 etching Methods 0.000 claims 5
- 238000000059 patterning Methods 0.000 claims 5
- 239000012535 impurity Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 2
- 230000000873 masking Effects 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N AI2O3 Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 229910017083 AlN Inorganic materials 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims 1
- 229910052593 corundum Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- 239000002159 nanocrystal Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910001845 yogo sapphire Inorganic materials 0.000 claims 1
Abstract
A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines (WL, Fig. 9) each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines (BL) each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines (SL) each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines (DL) each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.
Claims
1. A semiconductor device having an electrically erasable programmable read only memory (EEPROM), comprising a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer, each EEPROM memory cell comprising a drain region, a source region, a gate region, and a body region; a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells; a plurality of source lines each connecting the source regions and the body regions of a column of EEPROM memory cells; and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells; wherein the source lines and the drain lines are buried lines; and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.
2. The semiconductor device of claim 1, wherein the EEPROM memory cells include stacked gate structure fabricated on the silicon-on-insulator wafer.
3. The semiconductor device of claim 2, wherein the stacked gate structure includes a control gate region and a floating region separated from the control gate region by an insulating layer.
4. The semiconductor device of claim 3, wherein the floating region is disposed over the body region and is separated from the body region by an insulating layer.
5. The semiconductor device of claim 4, wherein the insulating layer is a silicon oxide film.
6. The semiconductor device of claim 1 , wherein the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells by one or more oxide layers.
7. The semiconductor device of claim 1 , further comprising at least a plurality of body lines each connecting the body regions of a column of EEPROM memory cells wherein the source line of a column of EEPROM memory cells is electrically connected to the body line of the same column of EEPROM memory cells.
43
8. The semiconductor device of claim 7, wherein the source line and the body line of a column of EEPROM memory cells are electrically connected by butting contacts.
9. The semiconductor device of claim 1, wherein the drain region and the source region in one or more of the EEPROM memory cells are disposed in a substantially symmetric structure relative to the gate region and the body region.
10. The semiconductor device of claim 1, wherein the body region comprises a semiconductor material of a first conductivity type, and the source region and the drain region comprise a semiconductor material of a second conductivity type that is opposite to the first conductivity type.
11. The semiconductor device of claim 1, wherein the memory states of the EEPROM memory cells are programmed by applying a first set of one or more voltages at the gate lines and erased by applying a second set of one or more voltages at the gate lines.
12. The semiconductor device of claim 11, wherein the first set of voltages are higher than the second set of voltages.
13. The semiconductor device of claim 12, wherein the first set of voltages are positive and the second set of voltages are negative.
14. The semiconductor device of claim 11, wherein the first set of voltages are lower than the second set of voltages.
15. The semiconductor device of claim 14, wherein the first set of voltages are negative and the second set of voltages are positive.
16. The semiconductor device of claim 11, wherein the EEPROM memory cells are programmed to two or more memory states by applying the first set of two or more voltages at the gate lines.
17. The semiconductor device of claim 16, wherein a row of EEPROM memory cells are programmed to two or more memory states by applying two or more voltages to different source lines and applying a fixed voltage at the gate line connecting to the row of EEPROM memory cells.
18. The semiconductor device of claim 16, wherein a row of EEPROM memory cells are programmed to two or more memory states by applying two or more voltages to different drain lines and applying a fixed voltage at the gate line connecting to the row of EEPROM memory cells.
44
19. The semiconductor device of claim 16, wherein a row of EEPROM memory cells are programmed to two or more memory states by applying two or more voltages to different body lines and applying a fixed voltage at the gate line connecting to the row of EEPROM memory cells.
20. A method for correcting out-of-range threshold voltages of EEPROM memory cells in a semiconductor device, comprising specifying a tolerance range for the threshold voltage of each memory state for the
EEPROM memory cells; detecting at least one out-of-range threshold voltage in the EEPROM memory cells; applying a positive voltage pulse to the gate region if the detected out-of-range threshold voltage is below the specified tolerance range; and applying a negative voltage pulse to the gate region if the detected out-of-range threshold voltage is above the specified tolerance range.
21. The method of claim 20, wherein detecting at least one out-of-range threshold voltage comprises applying a range of voltages to the gate line and sensing the threshold voltages of the EEPROM memory cells.
22. The method of claim 20, further comprising applying a positive voltage pulse to a gate line if out-of-range threshold voltages are detected below the specified tolerance range at a plurality of EEPROM memory cells connected to the gate line; and applying a negative voltage pulse to a gate line if out-of-range threshold voltages are detected above the specified tolerance range at a plurality of EEPROM memory cells connected to the gate line.
23. The method of claim 22, further comprising applying two or more different voltages to different source lines wherein the different voltages correspond to different memory states of the memory cells.
24. The method of claim 22, further comprising applying two or more different voltages to different drain lines wherein the different voltages correspond to different memory states of the memory cells.
25. The method of claim 22, further comprising applying two or more different voltages to different body lines wherein the different voltages correspond to different memory states of the memory cells.
45
26. A method of manufacturing a semiconductor device having an electrically erasable programmable read only memory (EEPROM) having a plurality of EEPROM cells, comprising: providing a silicon-on-insulator (SOI) wafer comprising a top silicon layer of a first conductivity type; growing a gate insulation film over the top silicon layer; depositing a floating-gate layer over the gate insulator; patterning the floating-gate layer and the gate insulation film in a first photo-masking step to form floating-gate structures in column-wise stripes. implanting impurities on the top silicon layer to form heavily doped areas of a second conductivity type, wherein the heavily doped areas are self-aligned to the floating- gate structures; forming insulating floating-gate sidewall spacers on the side walls of the column-wise floating-gate structures; removing the heavily doped area in the exposed top silicon layer between the insulating floating-gate sidewall spacers by etching to form electrically isolated heavily doped areas and grooves between the electrically isolated heavily doped areas, wherein the grooves and the electrically isolated heavily doped areas are self-aligned to the floating-gate structures; forming a first insulation film over the grooves between the two heavily doped regions, wherein the first insulation film is in stripe-wise pattern and self-aligned to the floating-gate structure; forming an inter-gate dielectric layer over the wafer; depositing a control gate layer over the wafer; patterning the control gate layer to form row-wise control-gate stripes in a second photo- masking step; and removing the floating-gate structures not covered by the control-gate stripes by etching such that the remaining floating-gate structures are self-aligned to the control-gate stripes.
27. A method of claim 26, wherein the EEPROM cells comprise source regions and drain regions formed in the electrically isolated heavily doped areas in the top silicon layer.
28. A method of claim 26, further comprising depositing a first sacrificial insulating film over the floating-gate layer after the floating- gate layer is deposited over the gate insulator; patterning the first sacrificial insulating film in the first photo-masking step such that the floating-gate structures further include the first sacrificial insulating film; and removing the sacrificial insulating film before an inter-gate dielectric layer is formed over the wafer.
29. A method of claim 26, further comprising forming conductive floating-gate sidewall spacers on the side walls of said column- wise floating-gate structures before an inter-gate dielectric layer is formed over the wafer, wherein the floating-gate sidewall spacers are electrically connected with the floating-gate layer and the floating-gate sidewall spacers are self-aligned to the floating-gate structures.
30. A method of manufacturing a semiconductor device having an electrically erasable programmable read only memory (EEPROM) having a plurality of EEPROM cells, comprising: providing a silicon-on-insulator (SOI) wafer comprising a top silicon layer of a first conductivity type; growing a first insulation film over the top silicon layer; forming a charge storage layer over the first insulation film; growing a second insulation film over the charge storage layer; depositing a column-gate layer over the second insulation film; patterning the column-gate layer in a first photo-masking step to form column gates in column- wise stripes; implanting impurities on the top silicon layer to form heavily doped areas of a second conductivity type, wherein the heavily doped areas are self-aligned to the column gates; forming insulating sidewall spacers on the side walls of the column gates; removing the heavily doped area in the exposed top silicon layer between the insulating sidewall spacers by etching to form electrically isolated heavily doped areas and grooves between the electrically isolated heavily doped areas, wherein the grooves and the electrically isolated heavily doped areas are self-aligned to the column gates; forming an insulation film over the grooves, wherein the insulation film is in stripe-wise pattern and self-aligned to the column gates;
47 depositing a control gate layer over the wafer; and patterning the control gate layer to form row-wise control-gate stripes in a second photo- masking step.
31. A method of claim 30, wherein the EEPROM cells comprise source regions and drain regions formed in the electrically isolated heavily doped areas in the top silicon layer.
32. A method of claim 30, wherein the charge storage layer is made of silicon nitride, Al2O3, or AlN.
33. A method of claim 30, wherein the charge storage layer consists of mutually isolated silicon or germanium nanocrystals.
34. A method of claim 30, wherein the column-gate layer is made of polysilicon.
35. A method of claim 30, further comprising removing the column-gate layer not covered by the control-gate stripes by etching such that the remaining column gates are self-aligned to the control-gate stripes.
36. A method of claim 30, further comprising removing the column-gate layer by etching before depositing the control gate layer.
48
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/781,112 US7042044B2 (en) | 2004-02-18 | 2004-02-18 | Nor-type channel-program channel-erase contactless flash memory on SOI |
| US10/781,112 | 2004-02-18 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2005081769A2 WO2005081769A2 (en) | 2005-09-09 |
| WO2005081769A3 WO2005081769A3 (en) | 2005-12-29 |
| WO2005081769B1 true WO2005081769B1 (en) | 2006-02-23 |
Family
ID=34838687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2005/002655 WO2005081769A2 (en) | 2004-02-18 | 2005-02-01 | Nor-type channel-program channel-erase contactless flash memory on soi |
Country Status (3)
| Country | Link |
|---|---|
| US (3) | US7042044B2 (en) |
| CN (1) | CN1914739A (en) |
| WO (1) | WO2005081769A2 (en) |
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2004
- 2004-02-18 US US10/781,112 patent/US7042044B2/en not_active Expired - Fee Related
-
2005
- 2005-02-01 WO PCT/US2005/002655 patent/WO2005081769A2/en active Application Filing
- 2005-02-01 CN CNA2005800026091A patent/CN1914739A/en active Pending
- 2005-08-01 US US11/193,653 patent/US7495283B2/en not_active Expired - Fee Related
- 2005-08-01 US US11/193,652 patent/US20090029511A1/en not_active Abandoned
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