CN102420230B - Manufacturing method of structure of MOS capacitor - Google Patents
Manufacturing method of structure of MOS capacitor Download PDFInfo
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- CN102420230B CN102420230B CN 201110194151 CN201110194151A CN102420230B CN 102420230 B CN102420230 B CN 102420230B CN 201110194151 CN201110194151 CN 201110194151 CN 201110194151 A CN201110194151 A CN 201110194151A CN 102420230 B CN102420230 B CN 102420230B
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Abstract
The invention discloses a structure of a metal-insulator-metal MOS (Metal-Oxide-Semiconductor) capacitor. The structure comprises a top electrode, an intermediate electrode, a bottom electrode and an insulating layer and is formed in an MOS region, wherein a control gate of a gate of an MOS is the top electrode; a floating gate is the intermediate electrode; a dielectric layer is a first insulating layer; the manufacturing method comprises the following steps of: forming an oxidation layer by adopting dry method back etching; forming a bottom pole plate in a substrate by using a method for backfilling polycrystal, or implanting a certain dose of oxygen atoms in the certain depth of the substrate by adopting an ion implantation mode; then forming the bottom pole plate by using a subsequent processing method; and finishing other structures by adopting a stack gate structure or selectively back etching and chemical mechanical polishing. According to the structure and the method disclosed by the invention, the MOS region also used as one part of the semiconductor device is integrated to a capacitor circuit so as to provide a novel path for searching a method for increasing the capacitance value density of the metal-insulator-meta capacitor in unit area for engineers in the field.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, relate in particular to the manufacture method of the structure of mos capacitance device.
Background technology
Reducing circuit area is a kind of power of economy to microelectronic revolution, and the current densities of integrated circuit or chip increases because of dwindling constantly of size of circuit.Along with within increasing element is designed in integrated circuit, the complexity of integrated circuit can increase gradually, therefore possess stronger functional, a kind of passive component that wherein is included into gradually in many integrated circuits is metal-insulator-metal type (Metal Insulator Metal, MIM) capacitor, it generally includes the material of arranged stacked, comprises at least top and the bottom conductive electrode made by electric conducting material in material, and the intermediate insulating layer of being made by dielectric material.The most frequently used capacitance structure comprises traditional single-layer capacitor structure at present, the Chinese patent that is CN1208964A such as publication number discloses a kind of MIM capacitor, also have the invention of a lot of high-density capacitor structures mainly to concentrate on to adopt different technique at (or on volume) on unit are more electric capacity in parallel increasing capacitance density, be that the Chinese patent of CN100390910C just discloses a kind of method that increases the unit area capacitance density of MIM capacitor such as authorizing publication number.But, the different technique of above-mentioned employing is also very limited at the capacitance density that (or on volume) on unit are more electric capacity in parallel can increase, how just can seek the method for capacitance density of the unit are of more increase MIM capacitors, be the target that this area manufacturing engineers seek assiduously.
Summary of the invention
Problem for above-mentioned existence, the manufacture method that the purpose of this invention is to provide the structure of novel mos capacitance device, be mainly fully excavate the MOS device area as a part that forms capacitor and be integrated into possibility in capacitor circuit, provide new way for increasing final capacitance density.
The objective of the invention is to be achieved through the following technical solutions:
A kind of manufacture method of structure of mos capacitance device wherein, comprising:
Carry out etching in inside is formed with the well region that the silicon substrate of fleet plough groove isolation structure comprises, forms groove in this well region;
Growth one deck the first isolation oxide in established groove;
Growth one deck the first polysilicon above the first layer of isolation oxide, this first polysilicon layer is used to form bottom electrode;
Continuation covers one deck the second isolation oxide above silicon substrate and this first polysilicon layer, form the second insulating barrier between middle electrode and bottom electrode;
At second layer of isolation oxide superficial growth one deck the second polysilicon layer, this second polysilicon layer is used to form middle electrode;
Continuation covers one deck the 3rd isolation oxide above the second polysilicon layer, the 3rd layer of isolation oxide forms the first insulating barrier;
Cover one deck the 3rd polysilicon layer on the 3rd layer of isolation oxide, the 3rd polysilicon layer is used to form top electrodes;
Carry out graphical and selective etch, form the grid of MOS device, the first polysilicon layer, the second layer of isolation oxide, the second polysilicon layer, the 3rd layer of isolation oxide and the 3rd polysilicon layer form capacitor.
The manufacture method of the structure of above-mentioned mos capacitance device wherein, when forming groove in the well region that silicon substrate comprises, first at its surface-coated one deck photoresistance glue, then adopts the mode of photoetching and etching to complete.
The manufacture method of the structure of above-mentioned mos capacitance device, wherein, described etching mode is dry etching.
A kind of manufacture method of structure of mos capacitance device wherein, comprising:
Carry out etching in inside is formed with the well region that the silicon substrate of fleet plough groove isolation structure comprises, forms groove in this well region;
Growth one deck the first isolation oxide in established groove;
Growth one deck the first polysilicon above the first layer of isolation oxide, this first polysilicon layer is used to form bottom electrode;
Continuation forms the second insulating barrier between middle electrode and bottom electrode in surface coverage one deck the second isolation oxide;
Growth one deck the second polysilicon layer, carry out graphical and selective etch above the second layer of isolation oxide;
Continuation is in second polysilicon layer surface coverage one deck the 3rd isolation oxide;
Cover one deck the 3rd polysilicon layer on the 3rd layer of isolation oxide, carry out selective etch, and planarization is carried out on its surface;
Again carry out graphical and selective etch, the first polysilicon layer, the second layer of isolation oxide, the second polysilicon layer, the 3rd layer of isolation oxide and the 3rd polysilicon layer form capacitor.
The manufacture method of the structure of above-mentioned mos capacitance device wherein, when forming groove in the well region that silicon substrate comprises, first at its surface-coated one deck photoresistance glue, then adopts the mode of photoetching and etching to complete.
The manufacture method of the structure of above-mentioned mos capacitance device, wherein, described etching mode is dry etching.
The manufacture method of the structure of above-mentioned mos capacitance device, wherein, it is to adopt chemical mechanical milling method that described effects on surface carries out planarization.
A kind of manufacture method of structure of mos capacitance device wherein, comprising:
Carry out graphically on the surface that is formed with the silicon substrate of fleet plough groove isolation structure in inside;
The oxygen atom of doses is injected at well region lower face that the mode that adopts Implantation comprises at silicon substrate one segment distance place, after carrying out high-temperature heat treatment, forms bottom electrode in the well region that silicon substrate comprises;
Continuation covers one deck the first isolation oxide above silicon substrate, form the second insulating barrier between middle electrode and bottom electrode;
Growth one deck the first polysilicon layer, carry out graphical and selective etch above the first layer of isolation oxide;
Continuation is in first polysilicon layer surface coverage one deck the second isolation oxide;
Cover one deck the second polysilicon layer on the second layer of isolation oxide, carry out selective etch, and planarization is carried out on its surface;
Again carry out graphical and selective etch, form the grid of MOS device, the well region that silicon substrate comprises, the first layer of isolation oxide, the first polysilicon layer, the second layer of isolation oxide and the second polysilicon layer form capacitor.
The manufacture method of the structure of above-mentioned mos capacitance device wherein, carries out on the silicon substrate surface first at its surface-coated one deck photoresistance glue, then adopting photolithographicallpatterned to complete when graphical.
The manufacture method of the structure of above-mentioned mos capacitance device, wherein, described etching mode is dry etching.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after accompanying drawing, the advantage of these and other aspects of the present invention undoubtedly will be apparent.
Description of drawings
With reference to appended accompanying drawing, describing more fully embodiments of the invention, yet appended accompanying drawing only is used for explanation and sets forth, and does not consist of limitation of the scope of the invention.
Fig. 1 is the structural representation of the structure of mos capacitance device of the present invention;
Fig. 2 A～Fig. 2 G is the structural representation in the step of embodiment one of manufacture method of mos capacitance device of the present invention;
Fig. 3 A～Fig. 3 H is the structural representation in the step of embodiment two of manufacture method of mos capacitance device of the present invention;
Fig. 4 A～Fig. 4 F is the structural representation in the step of embodiment three of manufacture method of mos capacitance device of the present invention;
Fig. 5 A～Fig. 5 G is the structural representation in the step of embodiment four of manufacture method of mos capacitance device of the present invention.
Embodiment
The invention will be further described below in conjunction with schematic diagram and concrete operations embodiment.
as shown in Figure 1, the structure of mos capacitance device of the present invention, specifically comprise top electrodes 1, middle electrode 2, bottom electrode 3, the first insulating barrier 4 between top electrodes 1 and middle electrode 2, the second insulating barrier 5 between middle electrode 2 and bottom electrode 3, this structure is formed in a MOS device area, the MOS device comprises a silicon substrate 0, the grid of MOS device comprises the control gate 1 on upper strata and the floating boom 2 of lower floor, floating boom 2 is wrapped in a dielectric substance layer 4, control gate 1 is exactly top electrodes 2, floating boom 2 is exactly middle electrode 2, dielectric substance layer 4 is exactly the first insulating barrier 4, silicon substrate 0 surface is covered with an isolating oxide layer 5, top electrodes 1 and middle electrode 2 are positioned on isolating oxide layer 5, bottom electrode 3 be formed in the well region of MOS device and with silicon substrate 0 electric insulation, isolating oxide layer 5 is exactly the second insulating barrier 5.The electric capacity that forms between the electric capacity of top electrodes 2 and 2 formation of middle electrode and middle electrode 2 and bottom electrode 3 is relation in parallel each other.
Embodiment one
The manufacture method of mos capacitance device of the present invention specifically comprises:
As shown in Fig. 2 A and Fig. 2 B, in being formed with the well region that the silicon substrate 0 of fleet plough groove isolation structure 00 comprises, inside carries out etching, form groove 6 in this well region, when forming groove 6 in the well region that silicon substrate 0 comprises, first at its surface-coated one deck photoresistance glue 7, then adopt the mode of photoetching and dry etching to complete;
As shown in Fig. 2 C, in interior growth one deck the first isolation oxide 8 of established groove 6;
As shown in Fig. 2 D, at 8 layers of superficial growth one deck of the first isolation oxide the first polysilicon 3, be used to form bottom electrode 3;
As shown in Fig. 2 E, continue in silicon substrate 0 and first polysilicon layer 3 surface coverage one deck the second isolation oxide 5, form the second insulating barrier 5 between middle electrode and bottom electrode;
As shown in Fig. 2 F, at second layer of isolation oxide 5 superficial growth one deck the second polysilicon layers 9, this second polysilicon layer 9 is used to form middle electrode;
As shown in Fig. 2 G, continue to cover one deck the 3rd isolation oxide 10, the three layer of isolation oxide 10 and form the first insulating barrier 4 above the second polysilicon layer 9; Cover one deck the 3rd polysilicon layer 11, the three polysilicon layers 11 and be used to form top electrodes 1 on the 3rd layer of isolation oxide 10;
Carry out graphical and selective etch, form top electrodes 1, the first insulating barrier 4 and middle electrode 2, the structural representation after completing as shown in Figure 1.
Preferably, the etching mode of employing is dry etching.
Embodiment two
The manufacture method of mos capacitance device of the present invention specifically comprises:
As shown in Fig. 3 A and Fig. 3 B, in being formed with the well region that the silicon substrate 0 of fleet plough groove isolation structure 00 comprises, inside carries out etching, form groove 6 in this well region, when forming groove 6 in the well region that silicon substrate 0 comprises, first at its surface-coated one deck photoresistance glue 7, then adopt the mode of photoetching and dry etching to complete;
As shown in Figure 3 C, in interior growth one deck the first isolation oxide 8 of established groove 6;
As shown in Fig. 3 D, at 8 layers of superficial growth one deck of the first isolation oxide the first polysilicon 3, be used to form bottom electrode 3;
As shown in Fig. 3 E, continue in surface coverage one deck the second isolation oxide 5, form the second insulating barrier 5 of 3 of middle electrode and bottom electrodes;
As shown in Fig. 3 F, growth one deck the second polysilicon layer 9 above the second layer of isolation oxide 5 after carrying out graphical and selective etch, continues to cover one deck the 3rd isolation oxide 10 above the second polysilicon layer 9;
As shown in Fig. 3 G and Fig. 3 H, cover one deck the 3rd polysilicon layer 11 on 10 layers of the 3rd isolation oxide, carry out selective etch, planarization is carried out on the surface, again carry out graphical and selective etch, form top electrodes 1, the first insulating barrier 4 and middle electrode 2, the structure after completing as shown in Figure 1.
Preferably, the etching mode of employing is dry etching.
Preferably, to carry out planarization be to adopt chemical mechanical milling method (CMP) to effects on surface.
Embodiment three
The manufacture method of mos capacitance device of the present invention specifically comprises:
As shown in Fig. 4 A, Fig. 4 B and Fig. 4 C, carry out graphically on the surface that is formed with the silicon substrate 0 of fleet plough groove isolation structure 00 in inside, specifically first at its surface-coated one deck photoresistance glue 7, then adopts the mode of photoetching to complete; Oxygen atom (the O of doses is injected at well region lower face that the mode that adopts Implantation comprises at silicon substrate 0 one segment distance place
2), after carrying out high-temperature heat treatment, form bottom electrode 3 in the well region that silicon substrate 0 comprises;
As shown in Fig. 4 D, continue to cover one deck the first isolation oxide 5 above silicon substrate 0, form the second insulating barrier 5 of 3 of middle electrode and bottom electrodes;
As shown in Fig. 4 E, growth one deck the first polysilicon layer 9 above the first layer of isolation oxide 5, this first polysilicon layer 9 is used to form middle electrode;
As shown in Fig. 4 F, continue to cover one deck the second isolation oxide 10 above the first polysilicon layer 9, cover one deck the second polysilicon layer 11 on the second layer of isolation oxide 10, this second polysilicon layer 11 is used to form top electrodes;
Carry out graphical and selective etch, form the grid of MOS device, the well region 3 that silicon substrate 0 comprises, the first layer of isolation oxide 5, the first polysilicon layer 9, the second layer of isolation oxide 10 and the second polysilicon layer 11 form bottom electrode 3, the second insulating barrier 5, middle electrode 2, the first insulating barrier 4 and the top electrodes 1 of capacitor, and the structural representation after completing as shown in Figure 1.
Preferably, the etching mode of employing is dry etching.
Embodiment four
The manufacture method of mos capacitance device of the present invention specifically comprises:
As shown in Fig. 5 A, Fig. 5 B and Fig. 5 C, carry out graphically on the surface that is formed with the silicon substrate 0 of fleet plough groove isolation structure 00 in inside, specifically first at its surface-coated one deck photoresistance glue 7, then adopts the mode of photoetching to complete; Oxygen atom (the O of doses is injected at well region lower face that the mode that adopts Implantation comprises at silicon substrate 0 one segment distance place
2), after carrying out high-temperature heat treatment, form bottom electrode 3 in the well region that silicon substrate 0 comprises;
As shown in Fig. 5 D, continue to cover one deck the first isolation oxide 5 above silicon substrate 0, form the second insulating barrier 5 of 3 of middle electrode and bottom electrodes;
As shown in Fig. 5 E, growth one deck the first polysilicon layer 9 above the first layer of isolation oxide 5, carry out graphical and selective etch, this first polysilicon layer 9 is used to form middle electrode, continues to cover one deck the second isolation oxide 10 above the first polysilicon layer 9;
As shown in Fig. 5 F and Fig. 5 G, cover one deck the second polysilicon layer 11 on the second layer of isolation oxide 10, carry out selective etch, planarization is carried out on the surface, again carry out graphical and selective etch, form top electrodes 1, the first insulating barrier 4 and middle electrode 2, the structure after completing as shown in Figure 1.
Preferably, the etching mode of employing is dry etching.
Preferably, to carry out planarization be to adopt chemical mechanical milling method (CMP) to effects on surface.
In sum, also as being integrated in capacitor circuit after the part of semiconductor capacitor, the method for capacitance density of seeking to increase the unit are of MIM capacitor for the manufacturing engineers of this area provides new way to the manufacture method of the structure of mos capacitance device of the present invention with the MOS device area.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, therefore, although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as, and any and all scope of equal value and contents, all should think still to belong in the intent of the present invention and scope in claims scope.
Claims (10)
1. the manufacture method of the structure of a mos capacitance device, is characterized in that, comprising:
Carry out etching in inside is formed with the well region that the silicon substrate of fleet plough groove isolation structure comprises, forms groove in this well region;
Growth one deck the first isolation oxide in established groove;
Growth one deck the first polysilicon above the first layer of isolation oxide, this first polysilicon layer is used to form bottom electrode;
Continuation covers one deck the second isolation oxide above silicon substrate and this first polysilicon layer, form the second insulating barrier between middle electrode and bottom electrode;
At second layer of isolation oxide superficial growth one deck the second polysilicon layer, this second polysilicon layer is used to form middle electrode;
Continuation covers one deck the 3rd isolation oxide above the second polysilicon layer, the 3rd layer of isolation oxide forms the first insulating barrier;
Cover one deck the 3rd polysilicon layer on the 3rd layer of isolation oxide, the 3rd polysilicon layer is used to form top electrodes;
Carry out graphical and selective etch, form the grid of MOS device, the first polysilicon layer, the second layer of isolation oxide, the second polysilicon layer, the 3rd layer of isolation oxide and the 3rd polysilicon layer form capacitor.
2. the manufacture method of the structure of mos capacitance device according to claim 1, is characterized in that, when forming groove in the well region that silicon substrate comprises, first at its surface-coated one deck photoresistance glue, then adopts the mode of photoetching and etching to complete.
3. the manufacture method of the structure of mos capacitance device according to claim 2, is characterized in that, described etching mode is dry etching.
4. the manufacture method of the structure of a mos capacitance device, is characterized in that, comprising:
Carry out etching in inside is formed with the well region that the silicon substrate of fleet plough groove isolation structure comprises, forms groove in this well region;
Growth one deck the first isolation oxide in established groove;
Growth one deck the first polysilicon above the first layer of isolation oxide, this first polysilicon layer is used to form bottom electrode;
Continuation forms the second insulating barrier between middle electrode and bottom electrode in surface coverage one deck the second isolation oxide;
Growth one deck the second polysilicon layer, carry out graphical and selective etch above the second layer of isolation oxide;
Continuation is in second polysilicon layer surface coverage one deck the 3rd isolation oxide;
Cover one deck the 3rd polysilicon layer on the 3rd layer of isolation oxide, carry out selective etch, and planarization is carried out on its surface;
Again carry out graphical and selective etch, the first polysilicon layer, the second layer of isolation oxide, the second polysilicon layer, the 3rd layer of isolation oxide and the 3rd polysilicon layer form capacitor.
5. the manufacture method of the structure of mos capacitance device according to claim 4, is characterized in that, when forming groove in the well region that silicon substrate comprises, first at its surface-coated one deck photoresistance glue, then adopts the mode of photoetching and etching to complete.
6. the manufacture method of the structure of mos capacitance device according to claim 5, is characterized in that, described etching mode is dry etching.
7. the manufacture method of the structure of mos capacitance device according to claim 4, is characterized in that, it is to adopt chemical mechanical milling method that described effects on surface carries out planarization.
8. the manufacture method of the structure of a mos capacitance device, is characterized in that, comprising:
Carry out graphically on the surface that is formed with the silicon substrate of fleet plough groove isolation structure in inside;
The oxygen atom of doses is injected at well region lower face that the mode that adopts Implantation comprises at silicon substrate one segment distance place, after carrying out high-temperature heat treatment, forms bottom electrode in the well region that silicon substrate comprises;
Continuation covers one deck the first isolation oxide above silicon substrate, form the second insulating barrier between middle electrode and bottom electrode;
Growth one deck the first polysilicon layer, carry out graphical and selective etch above the first layer of isolation oxide;
Continuation is in first polysilicon layer surface coverage one deck the second isolation oxide;
Cover one deck the second polysilicon layer on the second layer of isolation oxide, carry out selective etch, and planarization is carried out on its surface;
Again carry out graphical and selective etch, form the grid of MOS device, the well region that silicon substrate comprises, the first layer of isolation oxide, the first polysilicon layer, the second layer of isolation oxide and the second polysilicon layer form capacitor.
9. the manufacture method of the structure of mos capacitance device according to claim 8, is characterized in that, carries out on the silicon substrate surface first at its surface-coated one deck photoresistance glue, then adopting photolithographicallpatterned to complete when graphical.
10. the manufacture method of the structure of mos capacitance device according to claim 8, is characterized in that, described etching mode is dry etching.
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| CN 201110194151 CN102420230B (en) | 2011-07-12 | 2011-07-12 | Manufacturing method of structure of MOS capacitor |
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| CN 201110194151 CN102420230B (en) | 2011-07-12 | 2011-07-12 | Manufacturing method of structure of MOS capacitor |
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| CN102420230B true CN102420230B (en) | 2013-06-05 |
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| KR100480641B1 (en) * | 2002-10-17 | 2005-03-31 | 삼성전자주식회사 | Metal-Insulator-Metal capacitor having high capacitance, integrated circuit chip having the same and method for manufacturing the same |
| US7042044B2 (en) * | 2004-02-18 | 2006-05-09 | Koucheng Wu | Nor-type channel-program channel-erase contactless flash memory on SOI |
| JP4594921B2 (en) * | 2006-12-18 | 2010-12-08 | 株式会社東芝 | Method for manufacturing nonvolatile semiconductor device |
| KR100842470B1 (en) * | 2006-12-28 | 2008-07-01 | 동부일렉트로닉스 주식회사 | Method for manufacturing capacitance of semiconductor device |
| CN101609844A (en) * | 2008-06-18 | 2009-12-23 | 和舰科技(苏州)有限公司 | A kind of nonvolatile storage location and manufacture method thereof |
| CN101937878B (en) * | 2010-07-30 | 2014-02-19 | 上海宏力半导体制造有限公司 | Memory and method for manufacturing same |
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