WO2005062287A1

WO2005062287A1 - Signal line driver of display panel

Info

Publication number: WO2005062287A1
Application number: PCT/JP2004/006152
Authority: WO
Inventors: Keiichi Noguchi; Toshiyuki Wada
Original assignee: Hiji High-Tech Co., Ltd.
Priority date: 2003-12-24
Filing date: 2004-04-28
Publication date: 2005-07-07
Also published as: WO2005062286A1

Abstract

A display panel having capacitive pixels in which the cost and power consumption are reduced while satisfying the requirements such as a line of various types, multilevel halftone, high definition, and large screen. A step of precharging a selected pixel to a specified charge start voltage at the start of the time during which the pixel is selected, a main charging step of charging the pixel to a desired halftone voltage by applying a specified voltage to a signal line connected with the pixel for a specified time after the precharge step, and a step of holding the charging voltage of the pixel by disconnecting the signal line from the pixel without waiting the end of the time during which the pixel is selected after the main charging step are included. In the main charging step, at least the specified time out of the applied specified voltage and the specified time during which the specified voltage is applied, is varied depending on the value of the provided halftone data.

Description

Description Display panel signal line driver Technical field

The present invention relates to a signal line driving method and apparatus suitable for driving a signal line connected to each pixel in a display panel having pixels provided with capacitance, such as a liquid crystal display panel and an organic EL display panel. is there. Background art

As is well known, an active matrix type liquid crystal display device includes a display panel in which pixels are arranged vertically and horizontally, a plurality of signal lines respectively corresponding to a vertical pixel row on the display panel, and a display panel. A plurality of scanning lines respectively corresponding to the upper horizontal pixel column, and arranged at each intersection of the signal line and the scanning line, on / off controlled by the scanning line, and conduction between the signal line and each pixel It includes a plurality of switch elements, a signal line driving circuit for driving signal lines, and a scanning line driving circuit for driving scanning lines (edited by Hiroo Hori and Koji Suzuki “Color Liquid Crystal Display” Kyoritsu Shuppan 200) 1 year).

A configuration example of such a liquid crystal display device is shown in FIG. In FIG. 2, 1 is a liquid crystal display panel in which pixels are arranged vertically and horizontally, 7 is a plurality of signal lines respectively corresponding to a vertical pixel row on the liquid crystal display panel, and 8 is a horizontal direction on the display panel. Scanning lines corresponding to the pixel columns of

.. 20n is a signal line drive circuit cut, 3ι,... 3m is a scan line drive circuit unit, 4 is a liquid crystal controller, and 50 is a gray scale power supply. is there.

In FIG. 22, thick arrow L 1 indicates data from CPU Thick arrow L 2 indicates an output control signal for timing control, etc.3 signal, thick arrow L 3 indicates an image and gradation data and an output control signal for timing control, etc.Thick arrow L 101 indicates a power supply line from the gradation power supply 50. Is shown.

An enlarged view of the part A in FIG. 22 is shown in FIG. In FIG. 23, 90 is disposed at each intersection of the signal line 7 and the scanning line 8, and is controlled to be on and off by the scanning line 8, so that a plurality of conductions are made between the signal line 7 and each pixel 91. A switch element (TFT) 92 is an auxiliary capacitance. In FIG. 23, C3 is the capacitance value of the liquid crystal pixel, and C4 is the capacitance value of the auxiliary capacitance. In FIG. 23, when the voltage of the scanning line 8 becomes “H” (ON), the switch element 90 is turned on, and the liquid crystal pixel 91 and the auxiliary capacitor 92 are charged.

A configuration example of a conventional signal line drive circuit unit is shown in FIG. As shown in the figure, the signal line drive circuit unit 20 is provided with gradation data (D00 to D05, D1) of a 6-bit gradation data line of 6 parallel channels connected to the liquid crystal controller 4. 0 to D 15, D 20 to D 25, D 30 to D 35, D 40 to D 45, D 50 to D 55) are latched in response to the edge of the data capture clock S 4 Data latch 204a, shift register (1-bit x 64 stages) 201 0 that generates strobe signals for 64 channels by sequentially shifting the time, and strobes for 64 channels output from shift register 201 0 In response to each of the signals, a latch circuit group (parallel 3 84 × 6 bits × serial 2 stages) 2020 which sequentially latches 6 bits of data of 6 parallel channels on the output line of the data latch 204a, and Latch circuit group 20 2 Parallel sent out from 0 3 6 for 84 channels Tsu DOO gradation data, respectively and a D / A converter group 20 3 0 into an analog gradation voltage.

In FIG. 23, S1 is the first start signal, and S2 is the second start signal. A signal S3 is a shift direction switching signal. In the figure, L81 indicates an output control signal such as an output timing signal or a data capture clock, and L101 indicates a power supply line for gradation generation (VDD, VSS).

Fig. 25 shows a configuration example (operational amplifier system) for one channel of a conventional signal line drive circuit. As shown in the figure, the signal line drive circuit includes a latch circuit 20 20-1 for latching one channel of 6-bit grayscale data at a timing designated by an output control signal (L81), and a latch circuit. And a D / A converter 2030-1 for converting 6-bit grayscale data output from the circuit 202-1 to the corresponding grayscale voltage. In this example, the DZA converter 2030-1 generates a 64-level gradation reference voltage (V1 to V64) based on the power supply voltage from the gradation haze source 50. The 6-bit level output from the latch circuit 20 20-1-1 out of the 64 grayscale reference voltages (V1 to V64) output from the grayscale reference voltage generator VREF and the grayscale reference voltage generator VREF -Selection switch network SEL that extracts one gray-scale voltage specified by the gray-scale data, and gray-scale voltage extracted by the over-voltage selection switch network SEL are impedance-converted and output to the output pad (PAD-1). Output circuit OP.

The power supply for gradation generation (see FIG. 22) 50 includes a constant voltage circuit composed of a power transistor for voltage control, a radiator, and the like. The reference voltage generation circuit V REF includes a resistance ladder circuit that generates 64 levels of gradation reference voltages (V 1 to V 64) based on the power supply voltage from the gradation generation power supply 50. The voltage selection switch network SEL has one end connected to each of the 64 grayscale reference voltage (Vl to V64) output lines, and the other end connected in common. The sixty-four analog switches ASS1, ASSS 2, · · 'Includes ASS 64. Further, the output circuit OP is configured by an op amp whose voltage follower is switched. The output pad (PAD-1) is connected to the signal connected to the pixel. Functions as the drive end of Route 7.

Fig. 27 shows an example of the configuration of a conventional signal line drive circuit for one channel (op-ampless method). As shown in the figure, in this example, the output of the voltage selection switch network SEL is led directly to the output pad PAD-1 without passing through the output circuit OP composed of an operational amplifier. ing. Note that the same components as those in the circuit of FIG. 24 are denoted by the same reference numerals, and description thereof will be omitted.

The output waveform of the signal line driving circuit shown in FIGS. 25 and 26 is shown in FIG. In the figure, there are two charging characteristic curves, one for charging from VSS to + V1 to + V64 and the other for charging from VDD to one V1 to one V64. The drawing is performed in consideration of the fact that the chargeability for the pixels is alternately switched, for example, every frame. Note that the actual charging start voltage varies depending on the charging voltage one frame before, but for convenience of explanation, in this example, the charging start voltage is unified to VDD or VSS. For example, when charging a pixel to + V63, + V63 is directly applied to the output pad (PAD-1). Therefore, the voltage of the signal line reaches + V63 while gradually rising from VSS in a time constant curve, and thereafter, is maintained at + V63 until the selection period of the pixel ends.

In recent years, there has been a tendency for further reductions in power consumption and cost in signal line drive circuits for liquid crystal display panels of this type. It is expected that this trend will be further strengthened from the viewpoint of higher functions such as higher definition and larger screen as follows.

[Multiple types]

Since the types of liquid crystal display panels vary widely even from the same manufacturer, signal line drive circuits that match the characteristics of each type are required. Cost increases are inevitable due to inevitable births.

[Multi gradation]

As the number of processing bits of the DZA converter (see reference numeral 230 in FIGS. 24 and 25) increases with the increase in the number of gradations, the area of the DZA converter occupying on the semiconductor substrate increases dramatically. However, cost reductions are incurred due to lower yields. For example, when the gradation data is changed from 64 gradations (6 bits) to 128 gradations (7 bits), the bit number of the gradation data increases by 1 bit. Occupied area is doubled. Similarly, when the gradation data is changed from 64 gradations (6 bits) to 256 gradations (8 bits), the number of bits of the gradation data increases by 2 bits. The area occupied by the A converter is quadrupled. In addition, in a signal line drive circuit that uses an op amp as an output circuit (see Fig. 25), if the potential difference between gradations becomes smaller as the number of gradations increases, the output accuracy of each operational amplifier will be reduced. The demands are becoming more stringent, increasing the area occupied by operational amplifiers, and increasing cost. At the same time, the power consumption of the operational amplifier also increases, which is an obstacle to reducing power consumption.

[High definition, large screen]

If the number of pixels on a liquid crystal display panel increases with higher definition and larger screens, the wiring resistance will increase, and it will be necessary to increase the driving capability of the output circuit. For this purpose, the element sizes of the operational amplifier (see Fig. 25) constituting the output circuit OP and the analog switches ASS1 to ASSn (see Fig. 26) constituting the voltage selection switch network SEL are increased. This leads to an increase in cost and power consumption due to an increase in circuit area.

The present invention has been made by paying attention to the above-mentioned problems in the conventional signal line driving circuit of a liquid crystal display panel. Satisfies the demand for higher functionality such as larger screen Another object of the present invention is to provide a signal line driving method and apparatus for a display panel, which can realize low cost and low power consumption. Disclosure of the invention

A signal line driving method for a display panel according to the present invention is a method for driving a display panel having a plurality of signal lines and a plurality of scanning lines, wherein the selection is performed by a scanning line among a plurality of pixels connected to each signal line. The charged pixel is charged to the gradation voltage specified by the gradation data given to the pixel. Due to the nature of the invention, a display panel to which the method of the present invention is applied must have a pixel having a capacitance component or a pixel having a capacitance component. From such a viewpoint, examples of the display panel to which the method of the present invention is applied include a liquid crystal display panel and an organic EL display panel. The signal line driving method includes a pre-charging step of pre-charging the pixel to a predetermined charging start voltage at the start of a period in which a pixel is selected; and a pre-charging step; By applying a voltage for a predetermined time, fl, the main charging step of charging the pixel to a desired gradation voltage, and following the main charging step, without waiting for the end of the period in which the pixel is selected, the signal is output. A charging voltage holding step of holding a charging voltage of the pixel by disconnecting the line from the pixel.

In the main charging step, at least the value of the predetermined time between the applied predetermined voltage and the applied predetermined time is changed according to the value of the given gradation data. Here, "at least the value of the predetermined time" means that in addition to changing the value of the predetermined time, the predetermined voltage itself may be continuously or stepwise changed with the distance between B temples. Means.

In addition, in the case of an active matrix type display / nel, a switch element interposed between a pixel and a signal line selects a pixel on a scanning line. This is performed by being turned on by the signal and conducting. In the case of a passive matrix type display panel, this is performed by applying a specified voltage between a row electrode and a column electrode opposed to each other with a pixel interposed therebetween.

For example, when a display panel including pixels that need to be charged alternately with voltages having different polarities, such as a liquid crystal display panel, is targeted, the predetermined voltage applied to the signal line in the main charging step is as follows. Alternatively, two types of constant voltages having an appropriate potential difference between positive and negative with respect to the charge start voltage may be prepared, and either one of the two types of constant voltages may be selected and applied to the signal line.

The charging of the pixel in the pre-charging step may be performed by applying a constant voltage equal to the charging start voltage to a signal line connected to the pixel for a predetermined time. Conversely, according to the present invention, the charging to a predetermined charging start voltage may be accelerated by applying a voltage higher than the charging start voltage to the pixel.

Further, the relationship between the applied gradation data and the predetermined voltage application time in the main charging step may be determined in consideration of the charging characteristic of the signal line and the Gamma curve characteristic. . As is well known, the Gamma curve is a curve indicating the relationship between each piece of grayscale data and the grayscale voltage of a pixel required to obtain the grayscale. Generally, gradation data and gradation voltage do not have a proportional relationship due to human visual characteristics.

From another aspect, the present invention can be grasped as a signal line driving device for a display panel. In a display panel having a plurality of signal lines and a plurality of scanning lines, the signal line driving device includes a pixel selected by a scanning line among a plurality of pixels connected to each signal line with respect to the pixel. The signal line driving device functions to charge to a gradation voltage specified by a given gradation data. At the start of a period in which a pixel is selected, Precharging means for precharging the battery to a predetermined charging start voltage, and applying a predetermined voltage to the signal line connected to the pixel for a predetermined time following the precharging to the charging open! Main charging means for charging the pixel to a desired grayscale voltage; and, following main charging, the signal line is disconnected from the pixel without waiting for the end of the period in which the pixel is selected, and And charging voltage holding means for holding the charging voltage.

Further, in the main charging means, of the applied predetermined voltage and the applied predetermined time, at least the value of the predetermined time may be changed according to the value of the given gradation data. .

As the predetermined voltage applied to the signal line in the main charging means, there are provided two types of constant voltages having an appropriate potential difference between positive and negative with respect to the charging start voltage, and one of the two types of constant voltages is selected. And then applied to the signal line.

The charging of the pixel by the pre-charging means may be performed by applying a constant voltage equal to the charging start voltage for a predetermined time to a signal spring extending to the pixel.

In the main charging means, the relationship between the applied gradation data and the predetermined voltage application time may be determined by considering the charging characteristics of the signal line and the Gamma curve characteristics.

According to the above-described method and apparatus of the present invention, the charge characteristic curve defined by the time constant of the signal line peripheral circuit including the pixel and the signal line applied voltage, and the predetermined voltage application time to the signal line, Since the charging voltage is uniquely determined, as in the case of the conventional signal line driving method, a gray scale voltage for preparing a large number of gray scale reference voltages corresponding to respective target pixel charging voltages in advance. Including a constant voltage circuit centered on one transistor), a gradation reference voltage JE generation circuit (including a resistor ladder circuit), a voltage selection switch network (many holes) (Including switches) becomes unnecessary, and the chip area can be reduced by reducing the number of components and the circuit area, thereby reducing costs and reducing power consumption.

Further, according to the method and apparatus of the present invention, since only three processes of precharging, main charging, and charging voltage holding are sequentially performed on a signal line, a power source having an appropriate voltage can be used. It can be realized with a simple circuit configuration such as interposing a charging switch between each signal line, and the effective output impedance of the signal line drive circuit is extremely low, so high definition and large area are intended. Even if this is the case, there is no need to provide an operational amplifier for driving the signal lines or to increase the size of the analog switch that constitutes the voltage selection switch network.From this aspect as well, the number of components and the circuit area are reduced. As a result, a small chip area can be realized, and cost and power consumption can be reduced.

Furthermore, according to the method and apparatus of the present invention, since only three processes of precharging, main charging, and charging voltage holding are performed sequentially on a signal line, a power supply having an appropriate voltage and each signal This can be realized by controlling the conduction time of the precharging switch and the main charging switch interposed between the line and the line using a counter, a digital converter, or the like. Because of the digitalization of the entire circuit, there is no analog circuit that requires high precision, so that the entire circuit or a part of the circuit can be built into the display panel, and it can be manufactured simultaneously with the display panel. Cost can be reduced.

As an embodiment of the signal line driving device according to the present invention, a configuration as shown in FIG. That is, the signal line driving device includes a precharging switch interposed between a driving end of a signal line connected to a pixel and a precharging power source having a predetermined voltage, and a driving end of a signal line connected to the pixel. The main charge switch interposed between the main charge power supply with voltage and the pixel are selected At the beginning of the period, the main charging switch is kept in the non-conductive state, and only the pre-charging switch is turned on for a predetermined time, thereby pre-charging the pixel to a predetermined charging start voltage. Following the pre-charge control and the pre-charge, the pre-charge switch is kept in the non-conductive state, and the main 3fe switch is turned on for a predetermined time determined based on the given gradation data. By setting the state, the main charging control means for enriching the pixel with a desired gradation voltage, and following the main charging, both the pre-charging switch and the 兰 charging switch are turned off. Accordingly, the voltage holding control means for holding the charging voltage of the pixel by disconnecting the signal line from the power is used.

According to such a configuration, the precharging switch and the main charging switch are provided, and the conduction timing and conduction time of the switches are only controlled by the precharge control means and the main charge control means. A simple configuration can be applied to a display panel that performs unipolar charging of pixels.

As another embodiment of the signal line driving device according to the present invention, the following configuration can be adopted. That is, a precharge switch interposed between a driving end of a signal line o connected to a pixel and a precharge power supply having a predetermined voltage, and a high end having a driving end of a signal line connected to a pixel and a predetermined high-side voltage. between the high-side main charging Suitsuchi interposed between俱ϋ ShuTakashi electric power, the low side main charging power supply having a drive end and a predetermined low side voltage繫Ka ^s Ru signal Line in pixels By keeping the low-side main charging switch and the high-side and low-side main charging switches interposed in a non-conducting state, only the pre-charging switch is turned on for a predetermined period of time. Pre-charge control means for pre-charging the pixels to a predetermined charging start voltage, and following the pre-charge, the high-side main charge switch and the low-side main charge switch while the pre-charge switch is kept in the non-conductive state. With Suites Only the main / slave switch on one side, which is determined according to the charging polarity required for the pixel, is made conductive for a predetermined time set based on the given gradation data. Main charging control means for charging the pixel to a desired gradation voltage, and following the main charging, the pre-charging switch, the high-side main charging switch, and the low-side main charging switch are all in a non-conductive state. And voltage holding control means for holding the charging voltage of the pixel.

According to such a configuration, the switch for pre-charging, the switch for high-side main charging, and the switch for low-side main charging are provided, and the conduction timing and conduction time of these switches are determined by the pre-charge control means and the main charging switch. Since the control is performed only by the control unit and the voltage holding unit, a simple configuration can be applied to a display panel that performs bipolar charging of pixels.

Aside from the choice of using a single power supply or two power supplies with different polarities for main charging, the second switch control means determines the charging characteristics of the signal line and the G a of the display panel. The predetermined time corresponding to the switch conduction period may be determined based on the grayscale data on the premise of the mma curve characteristic.

At this time, the second switch control means includes a counter clock generation means for generating a counter clock which is a series of clock pulse trains whose pulse intervals are adjusted to match the gamma carp characteristics, and a counter clock generation means. The pulse width determined according to the gradation data by comparing the given gradation data with the count value of the counter by comparing the given gradation data with the count value of the counter. And a comparator that outputs a one-shot pulse. The one-shot pulse may control the conduction period of the main charging switch.

According to such a configuration, the converter included in the signal line driving circuit is Since it can be realized with a small number of elements, the chip area can be reduced as compared with a signal line drive circuit using a conventional resistance ladder type gradation reference voltage generation circuit. In addition, according to such a circuit configuration, there is an advantage that the increase in the chip area is small even when the number of display gradations increases.

At this time, the counter clock generating means constitutes a series of power contacts whose pulse intervals are adjusted to match the gamma curve characteristics, and a series of reference pulses corresponding to successive counter pulse intervals. A series of reference clock count data is read out from the Gamma curve memory that has recorded the clock count data and the Gamma curve memory, and this is counted using the reference clock. And a counter clock generation circuit that repeats an operation of outputting a counter pulse every time.

According to such a configuration, the configuration of the precharge switch, the main charge switch, etc. is not changed, and only the data stored in the Gamma curve memory and the counter clock generation circuit are individually designed. It can be applied to various types of display panels with different characteristics, etc., and it can avoid cost increase even in high-mix low-volume production.

The signal line driving device of the present invention or the embodiment described above has a rewritable storage area corresponding to each gradation data, and the storage area has a corresponding storage area for each gradation data. A correction value memory for storing correction value data to be added and subtracted, and a correction value data corresponding to given gradation data are read out from the correction value data memory, and are added to and subtracted from the given gradation data. And a display process based on the gradation data added / subtracted via the addition / subtraction circuit.

According to such a configuration, even if the display panel has a variation in the time constant around the pixel including the signal line, it is suitable for the characteristics of each completed display panel. By writing the corrected correction value into the correction value memory, it is possible to suppress the quality variation of each product and to manufacture a low-cost and high-quality display panel. Brief Description of Drawings

FIG. 1 is a configuration example of a liquid crystal display lightning device to which the signal line driving circuit of the present invention is applied.

FIG. 2 shows an example of the configuration of the signal line drive circuit unit of the present invention (64 | ¾, 3384 channels).

FIG. 3 is a configuration example of one channel of the signal line driving circuit of the present invention. FIG. 4 is an equivalent circuit of a pixel and its peripheral circuit elements.

FIG. 5 is a diagram (part 1) illustrating a signal waveform of each part of the circuit illustrated in FIGS. 3 and 4.

FIG. 6 is a diagram (part 2) showing a signal waveform of each part of the circuit shown in FIG. 3 and FIG.

FIG. 7 is a diagram (part 3) showing signal waveforms at various parts of the circuit shown in FIGS. 3 and 4.

FIG. 8 is a diagram (part 4) showing a signal waveform of each part of the circuit shown in FIGS. 3 and 4.

FIG. 9 is a diagram showing signal waveforms at various parts of the circuit shown in FIGS. 3 and 4.

(Part 5).

FIG. 10 is a diagram (part 6) illustrating a signal waveform of each part of the circuit illustrated in FIGS. 3 and 4.

FIG. 11 is a layout diagram of FIGS. 5 to 10.

FIG. 12 is a diagram showing the relationship between the gradation data and the gradation voltage (gamma curve characteristic). FIG. 13 is a diagram showing the relationship between the gamma curve characteristics and the counter clock.

FIG. 14 is an explanatory diagram of a Gamma curve memory.

FIG. 15 is a diagram showing another configuration example (256 gradations, 384 channels) of the signal line drive circuit unit of the present invention.

FIG. 16 is a diagram showing a modification of the liquid crystal display device to which the signal line driving circuit of the present invention is applied, and a method of adjusting the modification.

Fig. 17 shows a configuration example (64 → 64 gradation correction) of the addition and subtraction circuit.

FIG. 18 is a diagram showing an output example of the comparator (64 → 64 gradation correction). FIG. 19 is a diagram showing an example of the configuration of an addition-subtraction circuit (256-> 256 gradation correction).

FIG. 20 is a diagram showing an example of the configuration of an addition / subtraction circuit (64 → 256 gray scale high accuracy correction).

FIG. 21 is a diagram illustrating an output example of a comparator (64-> 256 gray-scale high-precision correction).

FIG. 22 is a diagram showing a configuration example of a conventional liquid crystal display device.

FIG. 23 is an enlarged view of a portion A of FIG.

FIG. 24 is a diagram showing a configuration example of a conventional signal line drive circuit unit. FIG. 25 is a diagram showing a configuration example (op-amplifier method) for one channel of a conventional signal line drive circuit.

FIG. 26 is a diagram showing an example of a configuration for one channel of a conventional signal line drive circuit (an operation press method).

FIG. 27 is a diagram showing an output waveform of a conventional signal line driving circuit. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. I will tell. FIG. 1 shows a configuration example of a liquid crystal display device to which the signal line driving circuit of the present invention is applied. In the figure, 1 is a liquid crystal display panel in which pixels are arranged vertically and horizontally, 7 is a plurality of signal lines respectively corresponding to a vertical pixel row on the liquid crystal display panel, and 8 is a horizontal pixel on the display panel. A plurality of scanning lines corresponding to each column, 2ι, 22, ··· 2n-1 and 2n are signal line driving circuit units for driving signal line 7, and 3ι, ··· 3n are scanning A scanning line driving circuit unit for driving the line 8, 4 is a liquid crystal controller, 5 is a Gamma curve memory, and 6 is a power jack generation circuit.

In the figure, the thick arrow L1 is data from the CPU bus or the like. A thick arrow L2 is an output control signal for timing control or the like. The bold arrow L3 is an output control signal for image, gradation data, timing control, and the like. The thick arrow L4 is a series of reference clock count data corresponding to successive counter pulse intervals that constitute a series of counter clocks whose pulse intervals are jS adjusted to match the Gamma curve characteristics. Thick arrow L5 is before and after phase

This is the corresponding reference clock number data. The bold arrow L6 is a reference clock signal used for generating a counter clock, and the bold arrow L7 is a power clock generated by the counter clock generation circuit. The thick arrow L8 is an output control signal (including a counter clock) for the image, gradation data, and timing IJ control.

In the above configuration, the liquid crystal controller 4 operates by receiving data (L 1) from the CPU bus and the like, and outputs an output control signal (L 2) for timing control and the like, image, gradation data, and timing control. And an output control signal (L 3). Output control signals such as timing control thus obtained

(L2) is supplied to the scanning line drive circuit units 3i to 3m. The counter clock generation circuit 6 stores the reference clock number data L5 corresponding to the counter pulse interval read from the Gamma curve memory 5 and A counter clock L7 is generated and output based on the reference clock signal (L6) supplied from the controller 4. The output control signal (L3) for the image, gradation data, timing control, etc. thus obtained, and the counter clock signal

(L7) is integrated as a signal (L8), and then supplied in parallel to each of the signal line drive circuit units 2ι, 22 ··· 2n-1, 2n. The storage contents of the Gamma card memory 5 and the operation of the counter generation circuit 6 will be described later in detail.

FIG. 2 shows a configuration example (64 gradations, 384 channels) of the signal line drive circuit unit of the present invention. As shown in the figure, the signal line drive circuit unit 2 includes a shift register (1 bit x 64 stages) 210 for generating strobe signals for 64 channels, and a signal (L8). 6-channel gradation data (D00-DO5, D10-D15, D20-D25, D30-D35, D40-D45, D50- D5 5) Data latch 240 that latches L82 in accordance with the edge of data acquisition clock S4, and a gradation data bus (BUS) for 6 parallel channels provided on the output side of data latch 240. ) Is latched in response to each of the 64 channels of strobe signals output from the shift register (1 bit x 64 stages) 210 (parallel 384 x 6 bits X series 2 stages) 2 20 and Latch circuit group 2 20 Gray scale data of 84 channels output in parallel from the gray scale DZA converters for converting to voltage (384 units in parallel) 23 ° are included. In the figure, reference numeral L82 denotes the 6-bit grayscale data for the six channels of the system IJ, and reference numeral L81 denotes the output control signal (output timing polarity). Etc.), the signal CLK is added to the counter clock signal generated by the counter clock generation circuit 6. FIG. 3 shows a configuration example for one channel of the signal line driving circuit of the present invention. As shown in the figure, the signal line driving circuit for one channel is provided with a latch circuit 220 for latching the gradation data (D00 to D05) for one channel in response to the output control signal L81. — 1 and the one-channel gradation data D 00 to D 05 output from the latch circuit 220-1 are converted into one-shot pulses with different lengths, and the output pad is the signal line drive end. (PAD 1) output to the DZA converter 230_1.

The DZA converter 230-1 has three switches, a switch SW1 for pre-charging, a switch SW2 for high-side main charging, and a switch SW3 for low-side main charging. The precharge switch SW1 is interposed between the output pad (PAD1), which is a signal line driving terminal, and the precharge power supply VX having a predetermined voltage. In this example, the switch SW1 for precharging uses a p-channel type MOSFET 21a and an n-channel type MOS FET 21b connected in antiparallel to each other. The 髙 -side main charging switch SW2 is interposed between the output pad PAD1, which is a signal line driving terminal, and the high-side main charging power supply VDD having a predetermined high-side voltage. In this row, a ρ-channel type MO SF Ε is used as the high-side main charging switch SW2. The low-side main charging switch SW3 is interposed between the output pad (PAD 1), which is a signal line driving terminal, and the low-side main charging power supply VSS having a predetermined low-side voltage. In this example, an n-channel MOSFET is used as the low-side main charging switch SW3. The gate of the p-channel type MOS FET constituting the high-side main charging switch SW2 and the gate of the n-channel type M〇SFET constituting the low-side main charging switch SW3 are analog switches AS 1 , AS2, and then to the output terminal of the comparator CMP. These ana mouth The switches AS 1 and AS 2 are controlled so as to be selectively turned on by a data capture clock S 4. Specifically, when the logic level of the data acquisition clock 4 indicates a positive polarity voltage, the analog switch AS1 conducts. Similarly, when the logic level of the data acquisition clock S4 indicates a negative voltage, the analog switch AS2 is turned on.

The comparator CMP is a digital comparator that compares the gradation data D00 to D05 coming from the latch 220-1 with the 6-bit data coming from the counter CTR, and compares the comparison result with the result. Outputs the corresponding binary signal. The counter CTR counts the counter clock CLK. The start and stop of counting by the counter CTR are controlled by the output timing signal S5. As will be described later in detail, the pulse intervals before and after the counter clock CLK are adjusted to match the Gamma curve characteristics. The output polarity of the comparator CMP is alternately switched between positive polarity and negative polarity by the data capture clock S4. Therefore, on the output side of the comparator CMP, a positive one-shot pulse and a negative one-shot pulse having a pulse width T corresponding to the magnitude of the latched data D00 to D05 and a force The signal is output at the start of the selection period of the signal line. In the figure, the one-shot pulse of negative polarity is drawn in the circle with the symbol 250a, and similarly drawn in the circle with the symbol 250b. This is a positive one-shot pulse. As is clear from the figure, each of these pulses has a pulse width TXX corresponding to the magnitude of the gradation data D00 to D05 output from the latch 220_1.

Next, the operation of the signal line drive circuit shown in FIG. 3 will be described with reference to the signal waveform diagrams shown in FIGS. 5 to 10. The layouts in FIGS. 5 to 10 are in accordance with the layout diagrams in FIG. In FIGS. 5 to 10, reference numeral S6 denotes a precharge signal. A one-shot pulse having a pulse width Tp appears in the precharge signal S6 only at the beginning of one horizontal scanning period. The precharge signal S6 functions as a switching control signal for the precharge switch SW1, as shown in FIG. Specifically, the precharge signal exists as two complementary signals having different logical polarities, and the negative polarity signal, inverted S6, is given to the gate of the p-channel type MOS FET 21a. The positive polarity signal S 6 is supplied to the gate of the n-channel MOSFET 21 b. As a result, the two MOS FETs 21a and 21b conduct simultaneously, and the bidirectional conductivity is given to the precharge switch SW1.

The counter mark is attached with the code C LK. In the figure, the intervals between the pulsing pulses that make up the power interface are equal, but as will be described in detail later, these pulse intervals are set so as to match the Gamma mm curve characteristics. Has been adjusted.

The output of the CMP is the output of the comparator CMP. The CMP output (n) is the output of the comparator CMP when the latch data D00 to D05 supplied to the comparator CMP indicates the gradation (n).

A data capture clock is denoted by reference symbol S4. The logical polarity of the data capture clock S4 is inverted every horizontal scanning period. As a result, the pixel columns on the adjacent scanning lines are alternately charged positively and negatively.

The output of the scanning line driving circuit is denoted by reference numeral S7. This is the signal at point P2 on the output side of output pad PAD2, as shown in FIG. As will be described later, the scanning line driving circuit output S7 allows the switch element (TFT) 93 connecting the signal line 7 and the pixel 91 to be conductive or non-conductive. Communication is controlled.

The reference numeral V in denotes the signal line applied voltage, in other words, the signal line driving circuit output. This is the signal at the P1 point on the output side of the output pad PAD1, as shown in FIG. As will be described later, main charging of the pixel 91 is performed by the signal line applied voltage V in. The reference numeral Vc indicates the liquid crystal pixel charging voltage. This is the signal at the point P 3 connected to the pixel 91 as shown in FIG. As described later, the display gradation of the pixel is controlled by the liquid crystal pixel charging voltage Vc.

FIG. 4 shows an equivalent circuit of the pixel and its peripheral circuit elements. In the figure, PAD 1 is an output pad of a signal line drive circuit, PAD 2 is an output pad of a scan line drive circuit, 91 is a liquid crystal pixel, 92 is an auxiliary capacitor, 93 is a thin film transistor that constitutes a switch element, 8 1 is a wiring circuit element of the scanning line 8, and 71 is a wiring circuit element of the signal line 7. The wiring circuit element 71 of the signal line includes a wiring resistance 71a and a wiring capacitance 71b. R1 is the resistance value of the wiring resistance, and C1 is the capacitance value of the wiring capacitance. The wiring circuit constant 81 of the scanning line includes a resistance component 81a and a capacitance component 81b. Note that R2 is the resistance value of the resistance component 81a, and C2 is the capacitance value of the capacitance component 81b. Further, R 3 is the on-resistance value of the thin film transistor 93, C 3 is the capacitance value of the liquid crystal pixel 91, and C 4 is the capacitance value of the auxiliary capacitance 92.

The scanning line driving circuit output S7 is the signal at the point P2 on the output side of the pad PAD2 in the circuit of FIG. 4, and the signal line applied voltage Vin is the signal of the pad in the circuit of FIG. The signal at point P 1 on the output side of (PAD 1). Further, the charging voltage Vc of the liquid crystal pixel is the signal at point P3 in the circuit of FIG.

Assuming the above knowledge, it is now assumed that a pixel on any one horizontal scanning line; ^ Assume that you have selected. Then, in response to the start time t00 of the period in which the pixel on the one horizontal scanning line is selected (one horizontal scanning period), a one-shot pulse having a pulse width Tp appears in the precharge signal S6. (See Figure 5). Upon receiving the one-shot panorama in the precharge signal S6, the precharge switch SW1 is turned on, whereby the precharge voltage Vx is applied to the signal line, and the charge voltage V c is rapidly precharged from any negative voltage to Vx (see time too-to, too-to 'in Figs. 9 and 10). The important point here is that the precharge to the voltage Vx is completed within a time corresponding to the pulse width Tp of the one-shot pulse in the precharge signal S6. Subsequently, when the time Tp has elapsed from the start of one horizontal scanning period, the precharge switch SW1 is turned off again, and the precharge power supply Vx is disconnected from the signal line.

When the precharge period ends at time t0, the counter CTR subsequently starts counting the counter pulse CLK. The period in which the count value of the counter CTR is smaller than the gradation data D00 to D05 latched by the latch 220-1 (T1, T2,-- In 6 3, T 6 4), the output of the comparator CMP is maintained at "L". During the period in which the output of the comparator CMP is maintained at "L", only the analog switch AS1 is turned on by the operation of the data capture clock S4. Then, the output “L” of the comparator CMP is supplied to the gate of the p-channel type M〇SFET constituting the switch SW2 for high-side main charging, and the switch SW2 for high-side main charging is turned on. Then, application of the 髙 side main charging power supply VDD to the signal line is started (see time t O in FIG. 7). Then, the value of the charging voltage Vc of the pixel increases with time from the charging start voltage VX by drawing a predetermined time constant curve (No. (See time t O in Fig. 9). In this charging progress state, when the values of the gradation data D 00 to D 05 latched by the latches 220 to 11 match the count value of the counter CT, the output of the comparator CMP changes from “L” to “L”. H ”(see times tl, t 2,..., T η,..., T 63, t 64 in FIG. 5). The non-conducting state is established, and the marking of the high-side main charging power supply VDD for the signal line is stopped (see the horizontal portion in FIG. 9).

Now, assuming that the grayscale indicated by the grayscale data D00 to D05 latched by the latch 220-1 is "n", the value of the signal line applied voltage Vin becomes the time tn At this time, the voltage drops from + VDD to the voltage (Hiz) determined by the pixel charging voltage at that time (see Fig. 7). On the other hand, at time t n, the value of the pixel charging voltage V c has reached + V n (see FIG. 9). After that, the three switches SW1, SW2, and SW3 are all kept in the non-conductive state, so that the signal line connected to the pixel is disconnected from all power supplies without waiting for one horizontal scanning period. It is in an electrically floating state. As a result, the value of the charging voltage Vc of the pixel is maintained at + Vn, which is the charging voltage up to that point (see the horizontal portion of the charging curve in FIG. 9).

On the other hand, when the next selection period for the pixel comes, as shown in FIG. 6, at the start of one horizontal scanning period when the pixel is selected, the one-shot pulse included in the precharge signal S6 causes The precharging switch SW1 is turned on again (see t00 to t0 "in Fig. 6). Then, the precharging power supply Vx is applied to the signal line again, so that The value of the pixel charging voltage Vc is precharged from an arbitrary positive voltage to the precharging voltage Vx (see the dotted line in the charging curve in Fig. 8). At ij t O ′, when the pre-charge period ends, the pre-charge switch SW1 becomes non-conductive again, and the signal line connected to the pixel is Disconnected from the pre-charge power supply Vx. Thereafter, in the same manner as in the previous case, when the power counter CTR starts counting the counter clock signal CLK, the gradation data D 00 latched by the latch 220-1 in the comparator CMP is obtained. The magnitude comparison between ~ D05 and the count value of the counter CTR is started. At this time, the output of the comparator CMP is set to “H” during a period in which the count value of the counter CTR is smaller than the latched gradation data D0O to DO5 due to the operation of the data capture clock S4. It is maintained (periods Τ 1, Τ 2 · · · Τ η, '· Τ 63, Τ 64 in Fig. 6). At this time, only the analog switch AS2 is turned on by the action of the data polarity switching signal S7. As a result, the output “H” of the comparator CMP is supplied to the gate of the n-channel MOS FET constituting the low-side main charging switch SW3, so that the low-side main charging switch SW3 becomes conductive. Then, the application of the low-side main charging power supply VSS to the signal line is started (see time t C ^ in FIG. 8). Then, as shown in FIG. 6, the value of the pixel charging voltage V c gradually decreases while drawing a time constant curve from the charging start voltage V x (from time t 0 ′ in FIG. 10). See). Thereafter, when the latched gradation data D00 to D05 match the count value of the counter CTR, the output of the comparator CMP switches from "H" to "shi" (t1 'in FIG. 6). , t 2 ", ··· tn 1,--t 63 ', t 64'). Then, the low-side main charging switch SW3 becomes non-conductive, so that the low-side main At this time, the application of the charging power supply VSS stops, and the three switches SW1, SW2, and SW3 are all non-conductive, so that the signal line connected to the pixel is disconnected from any of the power supplies and electrically connected. It is assumed to be in a floating state.

As shown in FIG. 6, if the value of the gradation data is n gradations of negative polarity, the charging voltage Vc of the pixel is 1 Vn (see FIG. 10). Thereafter, when the signal line connected to the pixel is disconnected from any power supply, the value of the charging voltage Vc of the pixel is maintained at 1 Vn in this example.

(See the horizontal part of the charging curve in FIG. 10).

As described above, the signal line drive circuit according to the above-described embodiment includes the precharge power supply Vx interposed between the drive end (PAD 1) of the signal line 7 connected to the pixel 91 and the precharge power supply Vx. Switch SW1 and drive end of signal line 7 connected to pixel 91

(PAD 1) and the high-side main charging power supply VDD interposed between the high-side main charging power supply VDD and the driving end PAD 1 of the signal line 7 connected to the pixel 91 and the low-side main charging power supply VS With the low-side main charging switch SW3 and the high-side and low-side main charging switches SW2 and SW3 interposed between S and the non-conductive state, only the pre-charging switch SW1 is held for a predetermined time. (T p), the first switch control means for pre-charging the pixel 91 to a predetermined charging start voltage, and the pre-charge switch SW1 following the pre-charge. While keeping the non-conducting state, one of the high-side main charging switch SW2 and the low-side main charging switch SW3, which is determined in accordance with the charging polarity required for the pixel 91, is used for main charging. Only the switch is switched for a predetermined time (T n) determined based on the given gradation data DO 0 to D 05. The second switch control means for charging the pixel 91 to a desired gradation voltage and the three charging switches SW1, SW2, and SW3 are all turned off. Further, a charge voltage holding means for holding the charge voltage of the pixel 91 by disconnecting the signal line 7 connected to the pixel 91 from the power supply to make it electrically floated is provided.

Next, the data stored in the Gamma force memory 5 and the operation of the force counter clock generation circuit 6 will be described. The relationship between the gradation data and the gradation voltage (Gamma curve characteristic) is shown in Fig. 12, and the Gamma curve characteristic and The relationship with the counter clock is shown in FIG. 13 respectively.

As shown in FIG. 12, a non-linear relationship is established between the gradation data and the gradation voltage. Therefore, even if the grayscale data is carved at equal intervals, the corresponding potential difference between adjacent grayscale voltages is AV 0 1> AV 1

2> Not equal to ΔV23> ΔV34. Therefore, when each of the series of gradation data is determined by the voltage application time to the signal line, even if the gradation data changes at equal intervals, the voltage application time T l, Τ2, Τ3, Τ

4 · · · Τ 64 cannot be increased in proportion to this. Therefore, in the present invention, as shown in FIG. 13, the voltage application time Tl, Τ2, Τ3, Τ4,..., 64 shown in FIG. Then, the intervals of the clock pulses before and after constituting the counter clock are adjusted as ΔΤ01, ΔΤ12, Τ23, ΔΤ34, thereby obtaining the gradation voltage from the gradation data. In this case, the Gamma curve correction is realized.

More specifically, as shown in FIG. 14 (a), the Gamma curve memory 5 includes a series of counter clocks whose pulse intervals are adjusted to match the Gamma curve characteristics. Is stored as a series of reference click count data corresponding to successive counter pulse intervals. On the other hand, as shown in FIG. 14 (b), the counter clock generation circuit 6 sequentially reads out the reference clock number from the head address of the Gamma curve memory and reads this as the reference clock. The counter clock is generated by counting at. If the counter clock (CLK) thus obtained is counted by the counter CTR shown in FIG. 3, the value of the time length TXX corresponding to the count value is Tl, Τ2, Τ

3 · Τ 6 1 and G a mm a curve correction is performed, and the energizing time of switch SW2 or SW3 is controlled by this time length TXX By doing so, a desired gradation voltage can be generated.

The principle of generating the gradation voltage of the signal line driving circuit of the present invention described above is basically that the application time (T xx) is reduced while the applied voltage (V x, VDD, VSS) to the signal line 7 is fixed. Since it is changed according to the grayscale data, no special design change is required for the grayscale voltage generation system even if the number of grayscale bits is increased to achieve multiple grayscales. Therefore, as shown in Fig. 15, even in the case of 256 gradations and 384 channels, the number of bits is simply increased without any special design change. You can respond immediately.

The principle of generating a gray scale voltage of a liquid crystal display panel to which the signal line driving circuit of the present invention is applied is based on the assumption that the time constant of various circuit elements connected to the signal line and the applied voltage applied to the signal line are used. Since the charging voltage is generated by controlling, if the time constant fluctuates due to the variation of the circuit constant connected to the signal line, it may be assumed that the charging voltage cannot be generated accurately. . As shown in FIG. 4, a number of circuit elements (resistance components Rl, R2, capacitance components CI, C2, C3, C4) exist around the signal line, and in particular, a thin film transistor 9 It is recognized that the on-resistance R 3 of 3 has a relatively large variation.

Therefore, if a gradation correction process using the correction value memory 9 and the addition and subtraction circuit 10 shown in FIG. 16 is adopted, even if such circuit elements have variations, they can be corrected immediately before shipment or By making corrections during adjustment, it is possible to avoid quality degradation.

FIG. 16 shows a modification of the liquid crystal display device to which the signal line driving circuit of the present invention is applied and a method of adjusting the liquid crystal display device. As shown in the figure, in this example, an optical characteristic measuring device 100 used for inspection and adjustment is provided, while a correction value memory 9 and an addition / subtraction circuit 10 are provided on the liquid crystal display device side. Set Thus, the display processing is performed based on the gradation data added / subtracted via the addition / subtraction circuit 10.

The optical characteristic measuring device 100 is used for, for example, inspection and adjustment at the time of shipment of the liquid crystal display panel 1. The optical characteristic measuring apparatus 100 includes an image pickup apparatus 11 for photographing an image projected on the liquid crystal display panel 1 and normal tone data of each pixel corresponding to predetermined reference image data. The reference value memory 12 stored as the reference value is compared with the gradation data of each pixel obtained from the imaging device 11 and the gradation data of each reference pixel stored in the reference value memory 12. And a comparator 13 for generating and outputting the difference between them. Thick arrow L12 indicates the difference between each pixel and the reference value. The difference data generated by the comparator 13 is stored in the correction value memory 9. The addition and subtraction circuit 10 adds and subtracts the gradation data of each pixel obtained from the liquid crystal controller 4 and the correction value data of each pixel read from the correction value memory 9 to thereby obtain the characteristic of the liquid crystal display panel. The gradation data is corrected according to the above, and this is supplied in parallel to the signal line drive circuit units 2ι, 22 ··· 2n-1 and 2n.

An example of the configuration of the addition / subtraction circuit (64 → 64 gradation correction) is shown in FIG. As shown in the figure, the addition and subtraction circuit 10 includes a gradation detection circuit 1001 that detects gradation from gradation data (L 16) given from the liquid crystal controller 4, An adder / subtractor 1002 for adding and subtracting the correction value (L 15) read from the correction value memory 9 to the original gradation data (L 16) based on the detected gradation (L 14); Gamma curve memo

A counter clock generation circuit 6 that generates a counter clock based on the data (L5) from V5, and a counter clock based on an output control signal (L17) such as timing control obtained from the LCD controller 4. Generation circuit timing control signal (L19) and output control to scanning line drive circuit 3 And a timing control circuit 1003 for generating a signal (L 2). The gradation data (L 8) obtained from the addition / subtraction circuit 10 is sent to the 64 gradation signal line driving circuit, and the output control signal (L 2) is sent to the scanning line driving circuit 3. Thus, by storing the difference data 12 obtained from the comparator 13 in the correction value memory 9, the gradation data (L16) given from the liquid crystal controller 4 is appropriately corrected, whereby It is possible to realize a high-quality liquid crystal display panel by correcting the characteristic variation of each pixel.

An example of the output of the comparator (64 → 64 full tone correction) is shown in FIG. In this example, the actual gradation data is compared with the reference value (n).

If it is (n + 2), "1 2" is obtained as the correction value. In addition, when the actually measured gradation data is the reference value (n-1), which should be the reference value (n), "+1" is obtained as the correction value.

An example of the configuration of the addition and subtraction circuit (256 to 256 correction) is shown in FIG. This addition and subtraction circuit is almost the same as the circuit configuration of FIG. 17 except that the number of gradations of the gradation data is 256 gradations, and therefore, will be described in detail with reference to the description of FIG. Is omitted.

An output example of the comparator (64 → 256 gray scale high-precision correction) is shown in Fig. 21. In this example, if the reference value (n) should be the reference value (n-1), "+1" is obtained as the correction value. In addition, when (n + 2)-1 should be the reference value (n), "1-111" is obtained as the correction value. Similarly, if the reference value should be (n), but (n) ----, "0 ++" is obtained as the correction value. Similarly, if the reference value (n) should be the actual gradation value (n + 1) —, “1 1+” is obtained as the correction value. Thus, according to this comparator, the original gradation By increasing the measurement resolution of the optical property measuring device over the resolution of data, high-precision correction of 64 → 256 gradations is possible.

As shown in FIG. 20, the addition / subtraction circuit 10 includes a gradation detection circuit 1001 for detecting gradation from gradation data (L 16) supplied from the liquid crystal controller 4, and a detected gradation ( L20) is converted from 64 gradations to 256 gradations, and the corrected value (L2 3) obtained by accessing the correction value memory 9 with the converted gradations (L21) ), And an adder / subtracter 1 that performs addition and subtraction of the correction value (L 24) obtained from the optimization circuit 1004 and the gradation data (L 16) obtained from the liquid crystal controller 4. 02, a counter clock generation circuit 6 that generates a counter clock (L18) based on data from the Gamma curve memory 5, and an output control signal such as timing control obtained from the liquid crystal controller 4. Based on (L 17), the control signal (L 19) of the counter clock generation circuit 6 and the And a timing control circuit 103 for generating the output control signal (L 2). According to the addition / subtraction circuit 10, the optimization circuit 10

By the operation of 04, high-precision correction of 64 → 256 gradations becomes possible. As is clear from the above embodiments, according to the present invention, a charging characteristic probe defined by a time constant of a signal line peripheral circuit including a pixel and a signal line applied voltage, and a predetermined signal line Since the charging voltage of the pixel is uniquely determined by the voltage application time, it is necessary to prepare a number of gradation reference voltages corresponding to each of the target pixel charging voltages in advance, as in the conventional signal line driving method. , Power supply for gradation (including constant voltage circuit centering on power transistor), gradation reference voltage generation circuit (including resistance ladder circuit), voltage selection switch network (including many analog switches) are unnecessary, and the number of parts By reducing the chip area and the circuit area, the chip area can be reduced, and the cost and power consumption can be reduced. Further, according to the present invention, only three processes of precharging, main charging, and charging voltage holding are sequentially performed on the signal lines, so that a power supply having an appropriate voltage is connected to each signal line. It can be realized with a simple circuit configuration such as interposing a charging switch in the power supply, and the execution output impedance of the signal line drive circuit is extremely low. Therefore, it is not necessary to provide an operational amplifier or to increase the size of the analog switch that constitutes the voltage selection switch network.From this point of view, the number of components and the circuit area are reduced, and the chip area is reduced. Cost reduction and low power consumption can be achieved. Further, according to the present invention, only three processes of precharging, main charging, and charging voltage holding are sequentially performed on the signal lines, so that a power supply having an appropriate voltage is connected to each signal line. This can be realized by controlling the conduction time of the pre-charging switch and the main-charging switch interposed in the switch by using a counter, a digital comparator, or the like. Therefore, since there is no analog circuit or the like that requires high precision due to the digitization of the entire circuit, the entire circuit or a part of the circuit can be built into the display panel, and cost due to simultaneous manufacturing with the display panel can be reduced. You can also take down.

Further, according to the above embodiment, the switch SW1 for pre-charging, the switch SW2 for high-side main charging, and the switch SW3 for low-side main charging are provided, and the conduction timing and the conduction time of these switches are determined. However, since it is only controlled by the pre-charge control means and the main charge control means, there is an advantage that a simple configuration can be applied to a display panel which performs bipolar charging of pixels.

Further, according to the above embodiment, since the comparator CMP included in the signal line driving circuit can be realized with a small number of elements, the signal line using the conventional resistance ladder set of gradation reference voltage generation circuit can be realized. Saves time compared to drive circuits It is possible to increase the chip area. In addition, according to such a circuit configuration, there is an advantage that the increase in the chip area is small even if the number of display gradations increases.

Further, according to the above embodiment, the configuration of the pre-charge switch, the main charge switch, etc. is kept as it is, and only the data stored in the G amma curve memory and the count clock generation circuit are individually designed. It can be applied to various types of display panels with different characteristics such as mma power characteristics, and has the advantage that it does not increase the cost even for high-mix low-volume production.

In the above embodiment, in the main charging step, the applied voltage is fixed at VSS or VDD, and only the applied time TxX is changed in accordance with the value of the gradation data (D00 to D05). However, for example, the applied voltages are VSS1, VSS2, VSS3 (VSS1> VSS2> VSS3) and VDD1, VDD2, VDD3 (VDD1 <VDD2 <VDD3). In this way, three levels of positive and negative are prepared, and the gradation data (D00 to D05) is discriminated into three steps, and the three kinds of applied voltages are selected according to the discrimination result. For example, it is possible to eliminate the variation in the required charging time due to the magnitude of the gradation data value and to make the response speed uniform.

In the above embodiment, two types of applied voltages, positive and negative, are prepared. However, if the display panel uses a pixel material that does not require the polarity of the applied voltage to be alternately changed, such a bipolar voltage is used. Needless to say, it is not necessary to prepare an applied voltage.

Furthermore, in the above embodiments, the present invention is applied to a TFT liquid crystal panel, but the present invention can be widely applied to other display panels having capacitive pixels (for example, organic EL panels and the like). Industrial applicability

As is clear from the above description, according to the present invention, in a display panel having this kind of capacitive pixel, high-performance functions such as multi-product, multi-gradation, high-definition, and large-screen are realized. It is possible to achieve low cost and low power consumption while satisfying the requirements.

Claims

The scope of the claims

1. In a display panel having a plurality of signal lines and a plurality of scanning lines, a pixel selected by a scanning line among a plurality of pixels connected to each signal line is converted into a gray scale given to the pixel. A signal line driving method of a display panel for charging to a gradation voltage specified by data,

A precharge step of precharging the pixel to a predetermined charging start voltage at the start of a period in which the pixel is selected;

Subsequent to the pre-charging step, a main charging step of charging the pixel to a desired gradation voltage by applying a predetermined voltage to a signal line connected to the pixel for a predetermined time;

A charging voltage holding step of holding a charging voltage of the pixel by disconnecting the signal line from the pixel without waiting for an end of a period in which the pixel is selected, after the main charging step, and

In the main charging step, the value of at least the predetermined time is changed according to the value of the given gradation data, between the applied voltage and the predetermined time during which the predetermined voltage is applied. Driving method for display panel signal lines.

2. As the predetermined voltage applied to the signal line in the main charging step, two types of constant voltages having an appropriate potential difference between positive and negative with respect to the charging start voltage are prepared, and one of the two types of constant voltages is provided. 2. The signal line driving method for a display panel according to claim 1, wherein is selected and applied to a signal line.

3. The charging of the pixel in the pre-charging step is performed by applying a constant voltage equal to a charging start voltage to a signal line connected to the pixel for a predetermined time. 3. The signal line driving method for a display panel according to item 2 or 2.

4. In the main charging step, a relation between the applied gradation data and a predetermined voltage application time is determined in consideration of a charging characteristic and a gamma curve characteristic of the signal line. 4. The signal line driving method for a display panel according to any one of items 1 to 3.

5. In a display panel having a plurality of signal lines and a plurality of scanning lines, a pixel selected by a scanning line among a plurality of pixels connected to each signal line is converted into a gradation given to the pixel. A signal line driver for a display panel for charging to a gradation voltage specified by data,

Precharging means for precharging the pixel to a predetermined charging start voltage at the start of a period in which the pixel is selected;

Main charging means for charging the pixel to a desired gradation voltage by applying a predetermined voltage to a signal line connected to the pixel for a predetermined time after the pre-charging to the charging start voltage,

A charging voltage holding unit for holding a charging voltage of the pixel by disconnecting the signal line from the pixel without waiting for an end of a period in which the pixel is selected, after the main charging, and

The main charging means changes at least the value of the predetermined time according to the value of the given gradation data, between the applied voltage and the applied time. Signal line driving device.

6. As the predetermined voltage applied to the signal line in the second means, two kinds of constant voltages having a proper potential difference between positive and negative with respect to the charging start voltage are prepared. 6. The signal line driving device for a display panel according to claim 5, wherein the signal is selected and applied to a signal line.

7. The charging of the pixel in the pre-charging means is performed by applying a constant voltage equal to a charging start voltage for a predetermined time to a signal line connected to the pixel. Item or paragraph 6 Signal line driving device for display panel.

8. In the main charging means, a relationship between the applied gradation data and the predetermined voltage application time is determined in consideration of a charging characteristic and a gamma curve characteristic of the signal line. Item 8. The signal line driving device for a display panel according to any one of Items 5 to 7.

9. In a display panel having a plurality of signal lines and a plurality of scanning lines, a pixel selected by a scanning line among a plurality of pixels connected to each signal line is converted into a gradation given to the pixel. A signal line driver for a display panel for charging to a gradation voltage specified by data,

A precharge switch interposed between a drive end of a signal line connected to the pixel and a precharge power supply having a predetermined voltage;

A main charging switch interposed between a driving end of a signal line connected to the pixel and a main charging power supply having a predetermined voltage;

At the start of the period in which a pixel is selected, the pixel is precharged to a predetermined charge start voltage by leaving only the precharge switch conductive for a predetermined time while keeping the main charging switch in the non-conductive state. Precharge control means for causing

Subsequent to the pre-charging, the main charging switch is turned on for a predetermined time determined based on the given gradation data while the pre-charging switch is kept in the non-conducting state. Main charging control means for main charging to a desired gradation voltage;

Voltage holding control means for disconnecting the signal line from the power supply and holding the charging voltage of the pixel by setting both the pre-charging switch and the main charging switch to the non-conductive state following the main charging;

A signal line driving device for a display panel, comprising:

10. In a display panel having a plurality of signal lines and a plurality of scanning lines, a pixel selected by a scanning line among a plurality of pixels connected to each signal line is referred to as: A signal line driving device for a display panel for charging the pixel to a gradation voltage specified by gradation data given to the pixel,

A high-side main charging switch interposed between a driving end of a signal line connected to a pixel and a high-side main charging power supply having a predetermined high-side voltage;

A low-side main charging switch interposed between a driving end of a signal line connected to a pixel and a low-side main charging power supply having a predetermined low-side voltage;

By keeping only the pre-charging switch conductive for a predetermined time while keeping both the high-side and low-side main charging switches in the non-conductive state, the pixel can be pre-charged to the predetermined charging start voltage. Of the high-side main charging switch and the low-side main charging switch following the pre-charging control means and the pre-charging switch while the pre-charging switch is kept in the non-conductive state. By turning on only the main / slave power switch on one side determined according to the polarity for a predetermined time determined based on the applied grayscale data, the pixel is set to a desired grayscale voltage. Main charging control means for charging;

Voltage holding control means for holding the charging voltage of the pixel by setting all of the pre-charging switch, the high-side main charging switch, and the low-side main charging switch to a non-conductive state following the main charging;

A signal line driving device for a display panel, comprising:

11. The main charge control means determines a predetermined time corresponding to the switch conduction period based on the grayscale data, based on the premise of the charge characteristic of the signal line and the gamma carp characteristic of the display panel. 3. The signal line driving device for a display panel according to claim 1 or 2, wherein

1 2. The main charge control means

A series in which the pulse interval is adjusted to match the G a mm a curve characteristics A power clock generating means for generating a power clock which is a clock pulse train of

A counter for counting the pulse train generated by the counter clock generating means,

A comparator that outputs a one-shot pulse having a pulse width determined according to the gradation data by comparing the given gradation data with the count value of the counter,

12. The signal line driving device for a display panel according to claim 11, wherein a conduction period of the main charging switch is controlled by the one-shot pulse.

1 3. The counter clock generation means

A Gamma curve memory storing a series of reference clock number data corresponding to successive counterpulse intervals constituting a series of counterclocks whose pulse intervals are adjusted to match the Gamma curve characteristics,

A counter clock generation circuit that reads a series of reference count data from the Gamma carp memory, counts the count data at the reference count, and outputs a counter pulse each time counting is completed. , including,

13. The signal line driving device for a display panel according to claim 12, wherein:

14. A correction value memory having a rewritable storage area corresponding to each gradation data, and storing, in those storage areas, correction value data to be added to or subtracted from each gradation data.

An addition / subtraction circuit for reading correction value data corresponding to the given gradation data from the correction value data memory, and adding / subtracting the correction value data to / from the given gradation data. 14. The signal line driving device for a display panel according to claim 9, wherein display processing is performed based on the gradation data added / subtracted via the addition / subtraction circuit.