WO2005062183A1

WO2005062183A1 - Device for processing access concurrence to shared memory

Info

Publication number: WO2005062183A1
Application number: PCT/JP2004/017684
Authority: WO
Inventors: Tetsuya Hirano
Original assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
Priority date: 2003-12-22
Filing date: 2004-11-29
Publication date: 2005-07-07

Abstract

[PROBLEMS] To provide a data processing device comprising a data-length-variable DSP which can access data while a CPU accesses an external memory thereof. [MEANS FOR SOLVING PROBLEMS] In the case of 24-bit mode, if the judgment unit (11) judges that an access from the DSP (2) to the external memory (102) is present, a control unit (12) instructs wait of an access from the CPU (111) to the external memory (102). Moreover, in the case of 16-bit mode, by using an empty third bus-cycle, the control unit (12) outputs an instruction to an address data switching unit (13), so that the CPU (111) can access the external memory (102).

Description

Specification

Access conflict processing device for shared memory

Technical field

[0001] The present invention relates to a processing device having a plurality of data processing configurations in the same package, in which the CPU can access the external memory used by the processing device only via the processing device. The present invention relates to a data processing device capable of accessing an external memory.

Background art

[0002] In recent years, the amount of signal processing using a DSP capable of digitally processing voices, instrument sounds, and audio signals tends to increase. For this reason, measures are being taken to use DSPs with high signal processing capabilities and to use multiple DSPs.

[0003] The sound source of electronic musical instruments and the like The DSP that performs signal processing to apply effects to output musical sounds has an external memory and is used for delay processing and the like.

As shown in FIG. 20, such a DSP 2c is generally used by connecting an external memory 102 for storing digital delay data. The figure shows a state in which there are 64 times when the external memory 102 can be accessed in one sampling cycle (44. IKHz). Disclosure of the invention

Problems to be solved by the invention

[0005] Some CPUs provided in electronic musical instruments have a function of accessing an external memory for a DSP via a DSP depending on the case where it is normal to use RAM or the like on a system bus. is there.

[0006] In such a system, when CPU access and DSP access conflict, the operation timing of the DSP is determined by the program, so the operation priority is given priority. There is a method of giving a wait to CPU access (see Patent Document 1 described later). By delaying the CPU access, the timing of external memory access can be given to the DSP without waste.

Patent Document 1: Patent No. 2850707

[0007] As another method, there is a method of performing time-division access between the CPU and the DSP. This is, Compared to the above method, the number of times that the DSP can access is slightly reduced. The number of times that the CPU can access is given more.

[0008] Here, the relationship between the word unit handled by the DSP and the bus cycle will be described. In DSP

In many cases, the external memory used for delay processing is accessed via an 8-bit data bus, depending on the system's nos configuration and CPU.

[0009] One word, which is the data processing unit of the DSP, has 16 bits and 24 bits, and each of these bit units is one word. Usually, 16 bits (16-bit mode) are used to perform high-precision processing. In some cases, switch to 24-bit (24-bit mode).

[0010] In such a configuration, three access cycles (bus cycles) are grouped into one, and in the 16-bit mode, two access cycles out of the three cycles are used. In the 24-bit mode, three access cycles are used. Use

On the other hand, since the data length accessed by the CPU is not restricted by the data length of the DSP, the access may be repeated using the data bus width of the memory as the data length. In this case, 8 bits are 1 word

(1 byte) should be accessed.

[0012] When the above is premised, in a configuration in which the data length accessed by the DSP is variable, inconvenience occurs when either of the above-mentioned conventional configurations is adopted.

[0013] For example, when the method of giving a wait to the CPU access is adopted, the power suitable for the 24-bit mode is always more than one bus cycle in one data access unit (3 bus cycles) in the 16-bit mode. Precious bus cycles are wasted.

[0014] In addition, when a method of performing time-division access between the CPU and the DSP is employed, the fixed timing of the CPU is completely eliminated in the 24-bit mode, which is suitable for the 16-bit mode.

[0015] On the other hand, such a problem of the data processing device alone, which is not related to competition with CPU access, has the following problems.

[0016] That is, when the amount of memory delayed by the external memory is smaller than the memory size, connecting the external memories independently of each other is wasteful in terms of capacity and increases the cost. . When using multiple DSPs, multiple external memories are usually required.

However, the increase in the number of discrete parts causes a problem in circuit design. The present invention has been made in view of the above-described problems. A first object of the present invention is to provide a variable data length DSP in which a CPU can access an external memory between data accesses. No data processing device is provided.

[0018] A second object is to solve the above-mentioned second problem by providing a data processing apparatus in which a plurality of DSPs are packaged into one and these DSPs can share one external memory. I'm trying.

A third object is to provide a configuration in which such a data processing device can be used particularly for effect processing on musical sound waveform data stored in one external memory.

Means for solving the problem

[0020] The configuration of the present invention comprises:

Data processing that has at least a CPU that controls the entire device, a DSP that performs predetermined arithmetic processing, and an external memory that is accessed by the DSP and that can be accessed from the CPU via the DSP. In the device,

The DSP itself has a configuration in which at least two or more bus cycles are used as one data access unit, the number of bus cycles used in one data access unit can be selected, and the data length for accessing the external memory can be changed. And

Means for determining whether the DSP has accessed the external memory;

Means for controlling whether or not to access the external memory according to the presence or absence of the signal of the determination means;

Means for switching the address and data of the external memory and inputting / outputting the data in accordance with a command from the control means in the DSP;

If the data length is selected so as to access with the maximum number of nos cycles, and if the judgment means has determined that the DSP has access to the external memory, the control means also controls the CPU power to the external memory. The data length is selected so that the access is waited and the access is made with the maximum number of bus cycles. In the case where the data length is not available, the CPU can access the external memory by the control means using the empty bus cycle. It is a basic feature of the system. According to the above configuration, when the data length is selected to access with the maximum number of bus cycles (for example, 3 bus cycles) (for example, in the case of 1 word = 24-bit mode), When it is determined that the DSP has access to the external memory, the control means waits for the CPU to access the external memory, and the data length is selected so as to access the maximum number of bus cycles. In this case (for example, in the case of 1 word = 16-bit mode), the control means uses the vacant bus cycle to allow the CPU to access the external memory. (That is, in the 16-bit mode, etc., so that the CPU can access the external memory during the vacant bus cycle, If there is no free bus cycle, use the DSP priority access method (ie, if there is no free bus cycle in 24-bit mode, etc., basically use it for DSP access, Only when there is no DSP access, it is possible to avoid switching to CPU external memory access).

[0022] The configuration of claim 2 is applied to a data processing device provided in an electronic musical instrument having a sound source and capable of generating musical tones, and more specifically,

A CPU that controls the entire apparatus, a sound source that supplies musical tone signals, a DSP that adds an arbitrary effect to the musical tone signal supplied by performing predetermined arithmetic processing, and is accessed by the DSP. And a data processing device having at least an external memory accessible from a CPU via the DSP.

The DSP itself uses at least two or more bus cycles as a unit of data access for signal processing of a musical tone signal, and can select the number of bus cycles to be used in one data access unit, and data for accessing an external memory. The length can be changed.

Means for determining whether the DSP has accessed the external memory;

If the data length is selected to access with the maximum number of nos cycles, When it is determined by the disconnection means that the DSP has access to the external memory, the data length is selected by the control means so that the CPU power also waits for the access to the external memory and accesses with the maximum number of bus cycles. In some cases, the CPU is configured to allow the CPU to access the external memory by the control means using the empty bus cycle.

[0023] As a configuration for achieving the second object, the invention of claim 3 is provided. That is, the structure of claim 3 is

A data processing apparatus having a fixed number of memory access timings per sampling cycle and having a plurality of DSPs in the same package for accessing the same external memory,

The data processing device comprises:

Read / write control means for controlling which of these instructions is to be enabled when there is a read or write instruction for each DSP at the same timing;

When there is a read instruction or a write instruction of each DSP at the same timing, access determination means for determining which DSP is to access the memory;

A first selector for outputting an address from a DSP according to a determination signal from the access determination means;

A second selector for outputting data from the DSP based on the determination signal,

In the DSP, data acquisition control means for acquiring data from an external memory in accordance with a judgment signal from the access judgment means is provided.

It is characterized by having.

[0024] According to the above configuration, when there is a read instruction or a write instruction from each DSP at the same timing, the read / write control means controls which of these instructions is valid, and also at the same timing. When there is a read instruction or a write instruction for each DSP, the access determination means determines which DSP is to be accessed for memory. Then, the first selector outputs an address from the DSP to the external memory in response to the determination signal from the access determination means, and the second selector similarly outputs a DS based on the determination signal. Output data from P to external memory. On the other hand, the DSP that has performed the memory access by the access determination means and has read the data receives the determination signal from the access determination means, and receives data input from the external memory by the data acquisition control means provided in the DSP. You will get By the operation of each of these means, it becomes possible to provide a data processing device in which a plurality of DSPs can be packaged in one and these DSPs can share one external memory.

[0025] Further, the structure of claim 5 is as follows:

A data processing apparatus having a plurality of DSPs having a fixed number of memory access timings per sampling cycle and storing a musical tone waveform data and accessing one external memory in a same package,

The data processing device comprises:

It is characterized by having.

[0026] When tone waveform data is output from a plurality of channels, two or more DSPs are used depending on the number of effects to be applied (including different types of effects). May be In order to implement multiple DSPs as signal processing using DSPs increases, it is more reasonable to reduce the power consumption and improve the processing speed by using a single package to form a system LSI. It is considered to be. Therefore, the configuration of claim 5 packages a plurality of DSPs into one package, and the power of these DSPs is one. There is provided a device which uses a configuration of a data processing device capable of sharing an external memory as a configuration for applying an effect to musical tone waveform data.

[0027] In both the configurations of claims 3 and 5, the read / write control means is preferably controlled so as not to access the external memory when there are a plurality of instructions from the DSP. (Claims 4 and 6).

The invention's effect

[0028] According to the data processing device according to claims 1 and 2 of the present invention, in a configuration in which the data length accessed by the DSP is variable, the CPU can access the external memory during the data access of the DSP. As a result, it is possible to operate the CPU that does not disturb the access of the DSP so that the number of accesses is the largest.

[0029] Further, according to the data processing device of claims 3 to 6 of the present invention, there is provided an LSI in which a plurality of DSPs are packaged into one, and these DSPs can share one external memory. Therefore, if the capacity of the external memory can be wasted and the design of the circuit for performing signal processing using a plurality of DSPs can be more simplified, excellent effects can be achieved.

[0030] Particularly, as in claims 5 and 6, since two or more kinds of effects are applied to the musical sound waveform data by the DSP, when two or more DSPs are required, the waste of the capacity of the external memory can be eliminated. In addition, there is no need to complicate circuits around an electronic musical instrument or the like in which the configuration is used, and a merit can be obtained if the manufacturing process can be shortened.

Brief Description of Drawings

FIG. 1 is a circuit schematic diagram of an electronic keyboard instrument using the configuration of the data processing device according to Embodiment 1 of the present invention.

FIG. 2 is a schematic explanatory diagram of an internal circuit of a DSP 2 according to the data processing device of the present invention.

FIG. 3 is a detailed explanatory diagram of a configuration of a determination unit 11.

FIG. 4 is an explanatory diagram showing a signal processing state according to a configuration of a determination unit 11

FIG. 5 is a state transition diagram showing a state machine for controlling access from CPU 111 to external memory 102. FIG. 6 is an explanatory diagram showing a state of a no-cycle switching in an address / data switching unit 13 when an address and data are switched between a DSP operation unit 14 and a CPU 111.

FIG. 7 is a flowchart showing main processing of the electronic keyboard instrument of the first embodiment.

FIG. 8 is a flowchart showing a procedure of a panel scan process in step S102 of FIG. 7.

FIG. 9 is a flowchart showing a flow of a writing process or a reading process to the external memory 102 by the CPU 111 in step S203 and step S205 in FIG.

[10] FIG. 10 is a circuit schematic diagram of an electronic keyboard instrument using the configuration of the data processing device according to the second embodiment of the present invention.

FIG. 11 is a schematic explanatory diagram of an internal circuit of the effect LSI 21.

FIG. 12 is an explanatory diagram showing a circuit configuration of the memory access control unit 3 among the internal configurations of the photo LSI 21;

FIG. 13 is an explanatory diagram showing a control output state of a read / write control unit 22 when a read command or a write command is output from DSP 2a and DSP 2b.

FIG. 14 is an explanatory diagram showing a control output state of the access determination unit 23 when a read command or a write command is output from the DSP 2a.

FIG. 15 is a schematic explanatory diagram of a circuit configuration of DSP 2a or DSP 2b contained in the same package of the internal configuration of the effect LSI 21.

FIG. 16 shows the state of the instruction of each DSP 2 a and DSP 2 b and the control function of the memory access control unit 3 at 64 access timings in one sampling cycle when the effect LSI 21 operates in the two-chip mode. FIG.

FIG. 17 is a flowchart showing main processing of the electronic keyboard instrument of the second embodiment.

FIG. 18 is a flowchart showing a procedure of a panel scan process in step S402.

FIG. 19 is an explanatory diagram showing another configuration of the access determination unit 23 in FIG.

[Figure 20] Conventional DS that uses external memory 102 for digital delay data storage

FIG. 4 is an explanatory diagram showing a connection state of P2c.

Explanation of symbols

1 Data processing device

2, 2a, 2b, 2c DSP Memory access control unit Judgment unit Control unit Data switching unit

DSP operation unit Instruction RAM decoder

Effect LSI read / write control unit Access judgment unit Address output selector Data output selector Data acquisition control unit Data register Sound source waveform memory External memory System bus

CPU

ROM

RAM

Operation panel a None scan circuit Keyboard a Keyboard scan circuit

DZA conversion circuit Amplifier 118 speaker

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

Example 1

FIG. 1 is a circuit schematic diagram of an electronic keyboard instrument using the configuration of the data processing device 1 according to the first embodiment of the present invention.

In the present electronic keyboard instrument, as described later, effect processing is performed on musical sound data output from the sound source 100 by the DSP 2 using the external memory 102 used for delay processing. In the DSP2, one word as a data processing unit has a 16-bit mode in a 16-bit unit and a 24-bit mode in a 24-bit unit. Normally, a 16-bit mode is used. Depending on the settings, it is possible to switch to 24-bit mode when performing highly accurate processing.

In the case of the configuration of the present embodiment, three bus cycles (8 bits) are grouped into one, and in the 16-bit mode, two bus cycles among them are used. In the 24-bit mode, three bus cycles are used. Use the file.

On the other hand, a CPU 111 described later, which controls the entire electronic keyboard instrument, can access not only the RAMI 13 but also the external memory 102 used by the DSP 2 via the DSP 2. In this case, since the data length accessed by the CPU 111 is not restricted by the data length of the DSP 2, the data length is accessed using the data bus width of the memory (8 bits = 1 word).

As shown in FIG. 1, in this electronic keyboard instrument, a CPU 111, a ROM 112, a RAM 113, a nonel scan circuit 114a, a keyboard scan circuit 115a, a sound source 100, and an effect processing DSP 2 are interconnected via a system bus 110. It is connected to and configured. The system bus 110 is used for transmitting and receiving address signals, data signals, control signals, and the like.

CPU 111 controls the entire electronic keyboard instrument by operating according to a control program stored in ROM 112.

The ROM 112 stores various data referenced by the CPU 111 in addition to the above-described control program. The RAMI 13 is used for temporarily storing various data when the CPU 111 executes various processes. The RAMI 13 defines registers, counters, flags, and the like. The main ones will be described.

(A) Tone setting flag: Stores data for indicating whether any channel force is to be generated from the sound source 100 by setting on the operation panel 114 described later.

(B) Effect setting flag: A flag to be automatically set to the tone color by tone color setting is selected from a plurality of types of selectable effects, and the setting data is stored.

(C) 24-bit mode setting flag: When one word, which is a data processing unit of the DSP2, is set to 24 bits by operating the operation panel 114 described later, the setting data is stored ( 1: 24-bit mode, 0: 16-bit mode).

The operation panel 114 is connected to the panel scan circuit 114a. The operation panel 114 includes, for example, a panel switch for setting a tone used in a performance and adding an optional effect to an output musical tone. In this case, a tone color setting flag is set by selecting a tone color on the operation panel 114, an effect to be added when the tone color is output is automatically selected, and the effect setting flag is set.

In addition, a 24-bit mode setting switch for performing the processing of the effect processing DSP 2 in 24-bit units is provided on the operation panel 114. When the mode is set, the above-mentioned 24-bit mode setting flag is set. become. If not set, DSP2 processing is performed in 16-bit units. Although not shown, an LED display for displaying the setting state of each switch, an LCD for displaying various messages, and the like are provided.

The panel scan circuit 114a scans each switch on the operation panel 114 in response to a command from the CPU 111, and, based on a signal indicating the open / closed state of each switch obtained by this scan, Creates panel data with switches corresponding to 1 bit. In each bit, for example, “1” indicates a switch-on state, and “0” indicates a switch-off state. This panel data is sent to the CPU 111 via the system bus 110. This panel data is used to determine whether an on event or an off event of the switch on the operation panel 114 has occurred.

The panel scan circuit 114a operates display data sent from the CPU 111. Send to LED indicator and LCD on panel 114. As a result, the LED display is turned on and off according to the data sent from the CPU 111, and a message is displayed on the LCD.

The keyboard scanning circuit 115a detects key press data generated by the keyboard 115.

That is, each of these keys 115 is provided with a two-point switch. When it is detected that an arbitrary key 115 has been pressed down to a predetermined depth or more, the key data of the pitch data (key number) of the key is depressed. In addition to generating a signal, it generates a velocity velocity passing between the two-point switches, and sends them to the keyboard scan circuit 115a as key depression data. As the two-point switch, an optical sensor, a pressure sensor, and other sensors that can detect that the key has been pressed down to a predetermined depth or more can be used. When the keyboard scan circuit 115a receives the key press data from the two-point switch, it sends it to the CPU 111.

The key press data from the keyboard scan circuit 115a is sent by the CPU 111 to the sound source 100 corresponding to each channel by referring to the tone setting flag on the RAMI 13. At this time, the effect setting flag and the 24-bit mode setting flag are also referred to by the CPU 111, and the command for the necessary effect effect and the processing unit (1 word) of the DSP for performing the effect adding process are 24 bits. The command to determine whether to use 16 bits (command to determine whether or not to set the 24-bit mode) is sent to DSP2.

[0051] The sound source 100 uses the waveform memory 101 and performs memory access to it. That is, a read address is generated for the waveform memory 101, and the original data is read. After interpolating the read original data, it multiplies the envelope for each timbre, also generated by the same circuit, accumulates the waveform data of each timbre for the set channel, and externally It has a normal sound source configuration for outputting as waveform data.

The DSP 2 has an ordinary configuration such as a DSP operation unit 14, an instruction RAM 15 and a decoder 16 in addition to the configuration of an embodiment of the present invention described later shown in FIG. In response to a command from 111, a necessary effect is added to the tone data received from the sound source 100, and the resulting data is output to the DZA conversion circuit 116.

The command received from the CPU 111 is based on the effect setting flag and the 24-bit mode flag referred to by the CPU 111. That is, the panel of the operation panel 114 At the time of scanning, the CPU 111 refers to the effect setting flag indicating the effect corresponding to the selected tone, and issues a command to the DSP 2 to instruct what effect is to be applied to the output musical tone. Is done. The 24-bit mode flag set by the player's panel switch operation is also referred to. If the flag is set, the word of DSP2 is changed from 16 bits to 24-bit units.

In the DSP 2, as described above, the external memory 102 is used for storing digital delay data. At that time, in the 16-bit mode, one of the three bus cycles is vacant, so that the CPU 111 can fixedly access the external memory 102. On the other hand, in the 24-bit mode, the CPU 111 cannot access the external memory 102 because there is usually no free space in three bus cycles while the DSP 2 is processing. As a result, while the processing by DSP2 is not being performed, all three bus cycles are free, and one of the bus cycles is made available for the CPU 111 to access the external memory 102. The details will be described later.

Further, the waveform data on which a desired effect has been applied by the DSP 2 is input to the DZA conversion circuit 116, digital-to-analog converted, amplified by the amplifier 117, and emitted as a musical tone to the outside of the speaker 118.

FIG. 2 is a schematic explanatory diagram of the internal circuit of the DSP 2 as described above. The DSP 2 has a normal configuration such as the DSP operation unit 14, the instruction RAMI 5, and the decoder 16 described above, and a determination unit 11 and a control unit 12 between the CPU 111 and the external memory 102 via the bus 110. , And an address / data switching unit 13, and these components are involved in the memory access of the CPU 111 to the external memory 102 and are controlled.

[0057] The determination unit 11 is configured to determine whether the DSP 2 accesses the external memory 102. FIG. 3 is a detailed explanatory diagram of the configuration of the determination unit 11. As shown in the figure, the judging unit 11 includes an OR circuit to which a DSP 2 read instruction (R instruction) or a write instruction (W instruction) is input from the decoder 16, and an output of the OR circuit and the CPU 111 in a 24-bit mode. It is composed of an AND circuit that receives the word length switching signal sent by referring to the flag. These outputs are output as signals indicating that the CPU memory is accessible (CpTmE24Acs: accessible when 0, accessible not when 1). FIG. 4 shows a read instruction (R instruction) or a write instruction (W instruction) output from the decoder 16 of the DSP 2 in the 24-bit mode (= 1) or the 16-bit mode (= 0), respectively. FIG. 4 is an explanatory diagram showing how the output signal (CpTmE24Ac _S ) of the circuit of the determination unit 11 changes.

In the 16-bit mode (= 0), one of the three bus cycles is vacant, so that the CPU 111 can access the external memory 102 in a fixed manner. That is, the signal (CpTmE24Acs) is always 0, and the CPU 111 is always ready to access the external memory 102 during one of three bus cycles!

[0060] On the other hand, in the 24-bit mode (= 0), while DSP2 is processing (there is an R instruction or W instruction), there is usually no free space in three bus cycles. Therefore, the CPU 111 cannot access the external memory 102. As long as the processing by DSP2 is not being performed (in the state of N in the figure), all three bus cycles are free, and one bus cycle can be used to access the external memory 102 of the CPU 111. Like! /

The control unit 12 controls whether the CPU 111 can access the external memory 102 according to the presence or absence of the signal from the determination unit 11 (CpTmE24Acs = 0 or 1). That is, while the presence or absence of the signal (CpTmE24Acs) is 1, the external memory 102 access from the CPU 111 is waited.

FIG. 5 is a state transition diagram showing a state machine (an example at the time of a W instruction) for controlling access from CPU 111 to external memory 102.

The control unit 12 in the initial (00) state maintains the state (idle) as long as there is no change in the external force signal.

When the write instruction (W instruction) is output from the CPU 111, the state changes to a state (01) in which the write operation of the write instruction (W instruction) to the instruction receiving register of the DSP 2 has been started (01). During the continuation of the writing operation, the state is maintained (idle).

Further, when the operation of writing the write instruction (W instruction) from the CPU 111 to the instruction reception register of the DSP 2 is completed, the state changes to the instruction reception completed state (11), and the state is maintained (idle ). During this time, the write instruction (W instruction) from the CPU 111 is given a wait by the control unit 12 for memory access to the external memory 102. Thereafter, when the presence or absence of a signal from the determination unit 11 (CpTmE24Acs) is 0 and the state (10) is reached with the bus cycle timing described as the CPU in FIG. A command is issued to the data switching unit 13 to make the CPU111 write instruction (W instruction) valid. As a result, the address designation from the CPU 111 to the external memory 102 and the writing of data to the designated address are performed via the address / data switching unit 13. The address specification and data write state are maintained (idle).

Then, at the end timing of the bus cycle, that is, at the end timing of the write instruction (W instruction), the state returns to the initial state (00). This is almost the same for a read instruction (R instruction).

[0068] The address / data switching unit 13 switches addresses and data to the external memory 102 between the DSP operation unit 14 and the CPU 111 in accordance with a command from the control unit 12, and performs input / output thereof. It is.

In this configuration, as shown in FIG. 2, in addition to the above command from the control unit 12, a word switching signal output by the CPU 111 by referring to the 24 bit mode flag, (CpTmE24Acs) is input, and the address and data are switched between the DSP operation unit 14 and the CPU 111. FIG. 6 shows a state of the bus cycle switching in the address / data switching unit 13 at that time.

[0070] In the configuration of the present embodiment, as described above, three bus cycles are the maximum number of bus cycles, and when a data length is selected such that three bus cycles are fully used, that is, 24 bits In the mode, when the determination unit 11 determines that there is access from the DSP 2 to the external memory 102, as shown in the middle part of FIG. 6, a 24-bit lower byte access (L) and a middle byte Since the three bus cycles of the access (M) and the upper byte access (H) are fully used, the command from the control unit 12 issues a read instruction (R instruction) from the CPU 111 to the external memory 102 or a write instruction ( W instruction) will be weighted.

[0071] However, even in the 24-bit mode, when the determination unit 11 determines that the DSP 2 does not access the external memory 102, as shown in the lower part of FIG. In the cycle, the address' data switching unit 13 is enabled to read (R instruction) or write instruction (W instruction) from the CPU 111 to the external memory 102. On the other hand, when the data length is not selected so as to access with the maximum number of bus cycles (three bus cycles), that is, in the 16-bit mode, as shown in the upper part of FIG. Since only two bus cycles of the lower byte access (L) and the next higher byte access (H) of the packet are used, the control unit 12 uses the vacant bus cycle (third bus cycle). A command is issued to the address / data switching unit 13, a read command (R command) or a write command (W command) from the CPU 111 to the external memory 102 is output, and the CPU 111 can access the external memory 102.

Here, since the third bus cycle is always an empty bus cycle, it is possible to fixedly access the external memory 102 even with the CPU 111.

FIG. 7 is a flowchart showing main processing of the electronic keyboard instrument of the first embodiment. This main processing routine is started when the power is turned on. That is, when the power is turned on, the CPU 111, the RAM 113, the scan circuits 114a and 115a, the external memory 102, and other initial processing are first performed (step S101). In these initial processes, the hardware inside the CP Ul 1 and DSP 2 are set to the initial state, and the initial values are set to the registers, counters, flags, and the like defined in the RAMI 13.

When the initial process is completed, a panel scan process of the operation panel 114, which will be described later, is performed next (step S102).

Then, keyboard processing (keyboard scanning processing) for the keyboard 115 is performed (step S103). In this keyboard processing, key depression data corresponding to the key depression of the electronic keyboard instrument is created and output to the sound source 100 described above.

After that, based on the key press data, the sound source 100 and the DSP 2 are used to perform a sound generation process (and a mute process according to a key release) (step S104).

Next, other processing is performed (step S 105). In this processing, processing other than those described above, ONZOFF processing of the pedal, MIDI processing, and the like are performed.

Thereafter, the process returns to step S102, and the processes of steps S102 to S105 are repeated thereafter.

FIG. 8 is a flowchart showing the procedure of the panel scan process in step S102 in FIG.

First, the fact that the panel operation of the operation panel 114 has been performed indicates that the panel scan circuit 114a And the flag processing corresponding to those operations is performed (step S201).

Here, as described above, the operation panel 114 can be used to set, for example, a tone used in a performance, add an arbitrary effect to an output musical tone, and set a 24-bit mode. . At this time, a tone setting flag is set by selecting a tone on the operation panel 114, an effect to be added when the tone is output is automatically selected, and the effect setting flag is set. These are written to the registers on RAMI13.

[0083] Next, the CPU 111 refers to the state of the register of the setting storage switch for temporarily storing the setting state of the panel switch on the operation panel 114, and checks whether or not the switch is ON. Is performed (step S202). If the switch is ON (step S203; Y), the CPU 111 transfers the setting state of the panel switch from the register on the RAM 113 to the register set on the external memory 102 used by DSP2. (Step S203). That is, the setting is such that the external memory 102 can be handled in the same manner as the RAMI 13. This is to increase the free space of the RAMI 13 at the time of keyboard processing or sound generation processing performed later.

[0084] The CPU 111 refers to the state of the register of the setting return switch for restoring the setting state of the previous panel switch temporarily stored in the register set on the external memory 102 used by the DSP2, When the switch is turned ON !, it is checked whether or not the switch is ON (step S204). If the switch is in the ON state (Step S204; Y), the CPU 111 reads the setting state of the previous panel switch from the external memory 102 (Step S205).

Then, similarly from the CPU 111, the setting state of the previous panel switch is written to the register set on the RAMI 13 (step S206).

[0086] After that, other switch processing is performed (step S207), and the process returns to the main routine.

FIG. 9 is a flowchart showing the flow of the processing of writing or reading the external memory 102 by the CPU 111 in step S203 and step S205 in FIG. As shown in the figure, first, it is checked whether or not the instruction for reading or writing data from / to the external memory 102 by the CPU 111 is acceptable by the DSP 2 (step S301). The case where such an operation cannot be accepted by the DSP2 is a case where the state machine in FIG. 5 is in a state other than the state (00) as described above, and the DSP2 executes the execution of the previously specified write or read instruction. That is the end.

[0089] If this check fails to accept such an operation in DSP2 (step S301; N)

Then, the process returns to step S301, and the process is repeated.

[0090] On the other hand, if the above operation can be accepted by DSP2 (step S301; Y), the CPU

The program 111 branches the process depending on whether the operation is a writing operation ability (step S302).

If the operation is a write operation (Step S302; Y), the data to be written from the CPU 111 to the external memory 102 and the designated address are set in the DSP 2 (Step S303). Then, a write command is instructed to DSP2 (step S304).

After that, inside the DSP 2, the operation of the state machine shown in FIG. 5 is started, and the control unit 12 issues a command to the address / data switching unit 13 at the timing indicated by the judgment unit 11.

Then, data is written to the external memory 102.

On the other hand, if the above operation is a read operation (Step S302; N), the CPU

The address of the data read to 111 is set in DSP2 (step S305). Then, a read command is instructed (step S306).

[0094] After that, in the DSP 2, the operation of the state machine for the read operation according to Fig. 5 is started, and at the timing instructed by the determination unit 11, the control unit 12 issues a command to the address data switching unit 13. Then, data is read from the external memory 102 to the internal register of DSP2.

[0095] Then, the CPU 111 checks whether or not the DSP 2 has completed the read instruction from the CPU 111 (the CPU 111 checks the state of the state machine in the DSP 2, step S307).

If the read operation from the external memory 102 has not been completed (step S307; N), the above check is repeated until the read operation is completed. If the read operation is completed (Step S307; Y), the data is temporarily stored in the internal register of DSP2 when the read is completed. The read data is read, and the read operation ends (step S308).

After the write operation in step S304 or the read operation in step S308 is completed, the CPU 111 checks whether there is next data to be written or read (step S309). .

[0098] If there is such data (step S309; Y), the process returns to step S301, and the above processing is repeated. Conversely, if there is no such data (step S309; N), the process returns to the above step S204 or step S206 in FIG.

In the configuration of the first embodiment described above in detail, the access to the external memory 102 by the DSP 2 is fully used with the maximum data length of 3 bus cycles. In the case of the 24-bit mode, the determination unit 11 Therefore, when it is determined that there is access from DSP2 to external memory 102, three bus cycles are fully used by DSP2. Will be weighted.

[0100] However, when there is no access from the DSP 2 to the external memory 102 by the determination unit 11, the address / data switching unit 13 accesses the external memory 102 from the CPU 111 in the last bus cycle of three bus cycles. Will be allowed.

[0101] On the other hand, when the data length is 2 bus cycles and the access to the external memory 102 by DSP2 is used. In the 16-bit mode, only 2 bus cycles are used. Using the cycle, a command is issued from the control unit 12 to the address / data switching unit 13, so that the CPU 111 can access the external memory 102. Here, since the third bus cycle is always a free bus cycle, the CPU 111 can fixedly access the external memory 102.

Example 2

FIG. 10 is a circuit schematic diagram of an electronic keyboard instrument using the configuration of the data processing device 1 according to the second embodiment of the present invention.

[0103] In this electronic keyboard instrument, multiple tone settings can be made, but two effects that can be applied to those tone colors can also be set at the same time. Depending on the operation, 1) two effects are automatically determined by the tone setting, and 2) two effects are determined by the player's selection of the effect to be added. And there are.

As shown in FIG. 10, the present electronic keyboard instrument has a configuration substantially similar to that of the first embodiment, and includes a CPU 111, a ROM 112, a RAMI 13, a panel scan circuit 114a, The keyboard scan circuit 115a, the sound source 100 and the effect LSI 21 are connected to each other. The system bus 110 is used for transmitting and receiving address signals, data signals, control signals, and the like.

CPU 111 controls the entire electronic keyboard instrument by operating in accordance with the control program stored in ROM 112.

The ROM 112 stores various data referenced by the CPU 111 in addition to the above-described control program.

The RAMI 13 is used for temporarily storing various data when the CPU 111 executes various processes. The RAMI 13 defines registers, counters, flags, and the like. The main ones will be described.

[0108] (a) Tone setting flag: Stores data for indicating whether any channel force is to be generated from the sound source 100 by setting on the operation panel 114 described later.

[0109] (b) Effect setting flag: from the ability to select one or two main flags to be automatically set to the timbre by the timbre setting from a plurality of types of selectable effects, or depending on the player 1 or 2 this flag is set by direct selection and the setting data is stored.

[0110] (c) Two-chip mode flag: This electronic keyboard instrument is used in the case where the effect is added to the tone data generated from the sound source 100 by the above-described tone setting or by the player's selection. The number of effect setting flags is confirmed by the CPU 111, and if the number is two, two DSPs (DSP2a and DSP2b) used in the effect LSI 21 to be described later are used. Is set (= 1). At this time, the CPU 111 refers to the two-chip mode flag and outputs a mode switching signal (0: 1 chip mode, 1: 2 chip mode).

[0111] The operation panel 114 is connected to the panel scan circuit 114a. The operation panel 114 includes, for example, the setting of the tone used in the performance and the setting of any effect on the output tone. There is a panel switch for which addition can be set. In this case, a tone color setting flag is set by selecting a tone color on the operation panel 114, an effect to be added when the tone color is output is automatically selected, and the effect setting flag is set. In addition, as described above, the effect setting flag is changed by the player's direct operation of the panel switch of the operation panel 114, the two-chip mode flag is set, and the effect LSI 21 is set to the two-chip mode. In some cases. Although not shown, an LED display for displaying the setting state of each switch, an LCD for displaying various messages, and the like are provided.

[0112] When the two-chip mode flag is released by the above tone setting or the player's operation of the operation panel 114, the DSP in the effect LSI 21 is brought into a state in which one of the DSP2a or DSP2b is used. Tones can be output with no effects applied, or one effect can be applied and output. Also, when the two-chip mode flag is set by operating the tone setting change operation panel 114, two effects can be applied and output.

[0113] The panel scan circuit 114a scans each switch on the operation panel 114 in response to a command from the CPU 111, and, based on a signal indicating the open / closed state of each switch obtained by this scan, based on each signal. Creates panel data with switches corresponding to 1 bit. In each bit, for example, “1” indicates a switch-on state, and “0” indicates a switch-off state. This panel data is sent to the CPU 111 via the system bus 110. This panel data is used to determine whether an on event or an off event of the switch on the operation panel 114 has occurred.

The panel scan circuit 114a sends the display data sent from the CPU 111 to the LED display and the LCD on the operation panel 114. As a result, the LED display is turned on and off according to the data sent from the CPU 111, and a message is displayed on the LCD.

[0115] The keyboard scanning circuit 115a detects key press data generated by the keyboard 115.

That is, each of these keys 115 is provided with a two-point switch. When it is detected that an arbitrary key 115 has been pressed down to a predetermined depth or more, the key data of the pitch data (key number) of the key is depressed. A signal is generated and the velocity force passing between the two switches A city is generated and sent to the keyboard scan circuit 115a as key press data. As the two-point switch, an optical sensor, a pressure sensor, and other sensors that can detect that the key has been pressed down to a predetermined depth or more can be used. When the keyboard scan circuit 115a receives the key press data from the two-point switch, it sends it to the CPU 111.

The key press data from the keyboard scan circuit 115a is sent by the CPU 111 to the sound source 100 corresponding to each channel by referring to the tone setting flag in the RAM 113. At this time, the CPU 111 also refers to the effect setting flag and the two-chip mode flag, and issues a command for the necessary effect effect and a command for the required number of DSP chips (command for whether or not to set the two-chip mode). Will be sent to

[0117] The sound source 100 uses the waveform memory 101 and accesses the memory. That is, a read address is generated for the waveform memory 101, and the original data is read. After interpolating the read original data, it multiplies the envelope for each timbre, also generated by the same circuit, accumulates the waveform data of each timbre for the set channel, and externally It has a normal sound source configuration for outputting as waveform data.

As shown in FIGS. 10 and 11, the effect LSI 21 includes two DSPs 2a and 2b therein, and receives a musical tone data received from the sound source 100 in response to a command from the CPU 111. Then, the necessary effects are added to the data and output to the DZA conversion circuit 116 side.

[0119] The instruction received from the CPU 111 is based on the effect setting flag and the two-chip mode flag referred to by the CPU 111. That is, at the time of panel scanning of the operation panel 114, the CPU 111 checks what effect can be applied to the output musical tone by using the effect setting flag, and prepares a command to the effect LSI 21. At this time, a two-chip mode flag is set depending on whether the processing for adding the effect requires only one DSP in the effect LSI 21 or whether processing using two DSPs is required. Furthermore, when the sound generation process is actually performed, whether two DSPs 2a and 2b are used for the effect LSI 21 or only one of them (for example, DSP2a) is used depending on the setting of the two-chip mode flag. And then issue the effect commands necessary for the actual effect processing.

[0120] As described above, the effect LSI 21 uses an external memory for storing digital delay data. In the two-chip mode, two DSPs 2a and 2b are connected to the external memory.

102 will be shared. Details thereof will be described later.

[0121] Further, the waveform data to which the desired effect has been applied by the effect LSI 21 is input to the Ό / Α conversion circuit 116, and is converted into a digital-to-analog signal, amplified by the amplifier 117, and externally outputted as a musical tone from the speed 118. Released.

FIG. 11 is a schematic explanatory diagram of the internal circuit of the effect LSI 21 as described above. The effect LSI 21 is provided with DSPs 2a and 2b in the same package, and the memory access control unit 3 is used and controlled for memory access to the external memory 102.

In the configuration of the present embodiment, DSP2a and DSP2b having a memory access timing of 64 times per sampling period are used. In the two-chip mode, the read instruction (R1ZR2) output from the DSP2a and DSP2b and the The write command (W1ZW2) is received by the memory access control unit 3, and it is determined which DSP chip command is valid or not, and the chip command is issued to the chip enable signal (EAcID) power DSP2a and DSP2b. Based on this, an address is specified (A1 or A2) for the external memory 102, and data is input / output to / from the DSP 2a or DSP 2b.

FIG. 12 is an explanatory diagram showing a circuit configuration (indicated by a dashed line in the figure) of the internal configuration of the effect LSI 21, particularly, the circuit configuration of the memory access control unit 3. Here, a read / write control unit 22, an access determination unit 23, an address output selector 24, and a data output selector 25 are provided.

[0125] The read / write control unit 22 issues a read instruction for each DSP2a or DSP2b at the same timing.

If there are (R1 / R2) or write instructions (W1ZW2), control whether or not to enable the deviation of these instructions.

That is, as shown in FIG. 13, when both of the instructions (WZR) are output from both of the DSPs 2a and 2b or neither instruction is issued, the external memory 102 No access! / ヽ (N after control: No access). On the other hand, when either instruction (WZR) is output from either DSP2a or DSP2b, access to external memory 102 is validated. [0127] When there is a read instruction (R1 / R2) or a write instruction (W1ZW2) for each DSP 2a or DSP 2b at the same timing, the access determination unit 23 determines which DSP is to be accessed for memory.

In the present embodiment, as shown in FIG. 12, a NOR circuit that receives the read instruction R1 and the write instruction W1 of the DSP 2a on the input side and outputs the chip enable signal (EAcID) on the output side is also configured. I have. As shown in FIG. 14, when no instruction is issued from the DSP 2a side, it is output as a chip enable signal (EAcID), and the memory access of the DSP 2b is enabled.

[0129] Conversely, if any instruction is issued on the DSP2a side, the chip enable signal (EAcID) is output as 0 and the memory access of the DSP2a is enabled.

[0130] The address output selector 24 outputs the address A1 or A2 from the DSP 2a or DSP 2b according to the chip enable signal (EAcID) from the access determination unit 23. This address is, of course, for specifying an address for writing data to the external memory 102 or for specifying an address for reading data from the external memory 102.

[0131] The data output selector 25 outputs data D1 or D2 from the DSP 2a or DSP 2b based on the chip enable signal (EAcID). This data to be output is, of course, data to be written to the external memory 102, and is data being processed in the DSP 2a or DSP 2b.

FIG. 15 is a schematic explanatory diagram of the circuit configuration of the DSP 2a or DSP 2b contained in the same package of the internal configuration of the effect LSI 21. The DSP 2a or DSP 2b has a data register 27 for temporarily storing data in the digital signal processing, an instruction RAM 15 for storing instructions sent from the CPU 111, and decoding of the instructions. A normal DSP configuration such as a decoder 16 and a DSP arithmetic unit 14 for performing arithmetic processing (addition and multiplication instructions) stored in a data register 27 in accordance with decoded instructions is provided.

In the configuration of the present embodiment, the data read from the external memory 102 according to the chip enable signal (EAcID) from the access determination unit 23 and the data in the DSP 2a or DSP 2b and the data A data acquisition control unit 26 for causing the register 27 to acquire is provided. This Since the data acquisition is accompanied by a data read instruction R from the DSP itself, the read instruction of the decoder 16 is also input to the data acquisition control unit 26.

[0134] FIG. 16 shows each of the effects LSI21 having the above-described configuration at 64 access timings within one sampling cycle (44. IKHz) when operated in the 2-chip mode. FIG. 9 is an explanatory diagram showing instructions of DSP2a and DSP2b and states of control functions of a memory access control unit 3; As shown in the figure, when either instruction (WZR) is output from either DSP2a or DSP2b at each access timing, access to external memory 102 is enabled and external memory 102 is enabled. Data is written to or read from 102.

[0135] Conversely, if either of the instructions (WZR) is output from both DSP2a and DSP2b, or if neither of the two instructions is issued, neither access to external memory 102 is performed. N: No access).

FIG. 17 shows a processing flow of the main processing of the electronic keyboard instrument of the second embodiment, and is basically the same as the flowchart shown in FIG. 7 of the first embodiment. This main processing routine is started when the power is turned on. That is, when the power is turned on, first, the CPU 111, the RAM 113, each of the scan circuits 114a and 115a, the external memory 102, and other serial processes are performed (step S401). In these initial processes, the internal hardware of the CPU 111 after-effect LSI 21 is set to an initial state, and initial values are set to registers, counters, flags, and the like defined in the RAMI 13.

When the initial processing is completed, a panel scan processing of the operation panel 114 described later is performed (step S402).

[0138] Then, a keyboard process (keyboard scan process) for the keyboard 115 is performed (step S403). In this keyboard processing, key depression data corresponding to the key depression of the electronic keyboard instrument is created and output to the sound source 100 described above.

[0139] Thereafter, based on the key press data, the sound source 100 and the effect LSI 21 are used to perform sound emission processing (and mute processing according to key release) (step S404).

[0140] Next, other processing is performed (step S405). In this processing, processing other than those described above, ONZOFF processing of the pedal, MIDI processing, and the like are performed. [0141] Thereafter, the process returns to step S402, and the processing of steps S402 to S405 is repeated thereafter.

FIG. 18 is a flowchart showing the procedure of the panel scan process in step S402 in FIG.

First, the fact that the panel operation of the operation panel 114 has been performed is sensed by the panel scan of the panel scan circuit 114a, and the flag processing 'register corresponding to those operations is written (step S501).

Here, as described above, the operation panel 114 may be used to set, for example, a timbre to be used in a performance, or to add an arbitrary effect to an output musical tone. In this case, a tone setting flag is set by selecting a tone on the operation panel 114, an effect to be added when the tone is output is automatically selected, and the effect setting flag is set.

[0145] As described above, the effect setting flag is changed by a direct operation of the player using the panel switch of the operation panel 114, the two-chip mode flag is set, and the ef- fect LSI 21 is set to the two-chip mode. May be set.

Next, the CPU 111 refers to the timbre setting flag, sets a new timbre setting flag, and checks whether or not a force is applied (step S502). If there is no tone setting or no tone setting (step S502; N), the previous tone setting or the tone specified by default (eg, piano tone) is set (step S507). ).

[0147] Then, the CPU 111 refers to the effect setting flag and checks whether or not there is an effect to be added (step S503). If there is no such effect (step S503; N), the panel scan process ends, and the process returns to the main routine.

[0148] On the other hand, if there is an effect that requires additional processing (step S503; Y), it is further checked whether the effect power is sufficient (step S504). If two such effects are not required (step S504; N), the DSP 2a is enabled (step S508), and the process returns to the main routine.

[0149] Conversely, if two such effects are required (step S504; Y), the partition processing of the external memory 102 is performed for the DSP2a and the DSP2b (step S505), and the DSP2a and the DSP2b are enabled. Is performed (step S506). Then mainle Return to a chin.

According to the configuration of the second embodiment described in detail above, the system LSI 21 capable of sharing one external memory 102 by mounting one or more DSPs for applying effects to output musical sound waveform data by mounting a plurality of DSPs. With this configuration, it is possible to not only reduce power consumption and improve processing speed, but also to waste the capacity of the external memory 102 and to process signals using multiple DSPs. Circuit design can be simplified.

FIG. 19 is an explanatory diagram showing another configuration of the access determination unit 23 in FIG. As shown in the figure, all the read and write instructions (RD1, RD2, W1 and W2) of DSP2a and DSP2b are connected to the input side, and the read instruction (R1ZR2) or When a write instruction (W1ZW2) is issued, it is configured to determine which DSP is to be accessed for memory.

[0152] As shown in the figure, the read instruction R1 and the write instruction Wl of the DSP2a, and the read instruction R2 and the write instruction W2 of the DSP2b are input and the chip enable signal (EAcID) is output from the output. Logic circuit configuration is used. Also in this configuration, if no instruction is issued from the DSP 2a side, the chip enable signal (EAcID) is output as 1 and the memory access of the DSP 2b is enabled.

[0153] Conversely, if any instruction is issued on the DSP2a side, the chip enable signal (EAcID) is output as 0 and the DSP2a memory access is enabled.

[0154] The configuration of the data processing device of the present invention is not limited to the above-described embodiment, and it is a matter of course that various changes can be made without departing from the scope of the present invention. .

Industrial applicability

The configuration of the data processing device according to the present invention can be applied not only to electronic musical instruments but also to a configuration in which one external memory is generally accessed by a CPU via a data processing device such as a DSP. It can be used for a circuit configuration shared by a plurality of data processing configurations in the data processing device.

Claims

The scope of the claims

[1] At least a CPU that controls the entire apparatus, a DSP that performs predetermined arithmetic processing, and an external memory that is accessed by the DSP and is accessible from the CPU via the DSP In the data processing device,

Means for determining whether the DSP has accessed the external memory;

If the data length is selected so as to access with the maximum number of nos cycles, and if the judgment means has determined that the DSP has access to the external memory, the control means also controls the CPU power to the external memory. The data length is selected so that the access is waited and the access is made with the maximum number of bus cycles. In the case where the data length is not available, the CPU can access the external memory by the control means using the empty bus cycle. A data processing device characterized in that:

[2] A CPU that controls the entire apparatus, a sound source that supplies a tone signal, a DSP that performs a predetermined arithmetic process to add an arbitrary effect to the tone signal that is supplied with the tone generator power, A data processing device having at least an external memory accessed by the CPU and accessible from the CPU via the DSP.

The DSP itself uses at least two or more bus cycles as a unit of data access for signal processing of a musical tone signal, and can select the number of bus cycles to be used in one data access unit, and data for accessing an external memory. The length can be changed, and further, means for determining whether or not the DSP accesses the external memory;

Means for controlling whether or not to access the external memory according to the presence or absence of the signal of the determination means; Means for switching the address and data of the external memory and inputting / outputting the data in accordance with a command from the control means in the DSP;

[3] A data processing device having a fixed number of memory access timings per sampling cycle and having a plurality of DSPs in the same package for accessing the same external memory,

The data processing device comprises:

The DSP includes a data acquisition control unit for acquiring data from an external memory in response to a determination signal from the access determination unit.

A data processing device comprising:

4. The data processing device according to claim 3, wherein the read / write control unit does not access the external memory when there are a plurality of instructions from the DSP.

[5] A data processing device having a plurality of DSPs in a single package having a fixed number of memory access timings per sampling cycle and storing one musical tone waveform data and accessing one external memory, The data processing device comprises:

A data processing device comprising:

6. The data processing device according to claim 5, wherein the read / write control unit does not access the external memory when there are a plurality of instructions from the DSP.