WO2005057663A2 - Procede et appareil pour la fabrication de composants de circuits integres a semi-conducteurs metal-oxyde - Google Patents

Procede et appareil pour la fabrication de composants de circuits integres a semi-conducteurs metal-oxyde Download PDF

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Publication number
WO2005057663A2
WO2005057663A2 PCT/IB2004/003992 IB2004003992W WO2005057663A2 WO 2005057663 A2 WO2005057663 A2 WO 2005057663A2 IB 2004003992 W IB2004003992 W IB 2004003992W WO 2005057663 A2 WO2005057663 A2 WO 2005057663A2
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WO
WIPO (PCT)
Prior art keywords
gate structure
layer
sidewalls
forming
semiconductor device
Prior art date
Application number
PCT/IB2004/003992
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English (en)
Other versions
WO2005057663A3 (fr
Inventor
Frédéric Salvetti
Etienne Robilliart
Alexandre Dray
François Wacquant
Damien Lenoble
Ramiro Palla
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2005057663A2 publication Critical patent/WO2005057663A2/fr
Publication of WO2005057663A3 publication Critical patent/WO2005057663A3/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • This invention relates to a method and apparatus for fabrication of metal-oxide semiconductor integrated circuit devices, and in particular to a method and apparatus for fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuit devices of the lightly doped drain (LDD) type.
  • CMOS complementary metal-oxide semiconductor
  • LDD lightly doped drain
  • LDD lightly-doped drain
  • sidewall spacers are formed to protect a portion of the lightly-doped substrate adjacent to the gate electrode during the subsequent heavy-doping implantation step.
  • LDD structures are advantageous for reducing hot-carrier effects
  • traditional methods of forming these types of structures results in increased fabrication complexity and associated costs.
  • formation of the traditional sidewall spacers requires several processing steps, for example, oxide deposition, etching and cleaning, that increase fabrication complexity and the time and costs associated with these steps.
  • a method of forming a semiconductor device comprising the steps of forming a gate structure on a semiconductor substrate, performing heavy impurity doping in portions of said semiconductor substrate not covered by said gate structure so as to partially form source and drain regions of said semiconductor device, removing a first layer from an upper surface and sidewalls of said gate structure, performing light impurity doping in portions of said semiconductor substrate not covered by said gate structure to complete said source and drain regions of said semiconductor device, removing a second layer from the upper surface and sidewalls of said gate structure, forming a spacer layer on the sidewalls of said gate structure and forming a suicide contact on the upper surface of said gate structure.
  • the present invention also extends to an apparatus for forming a semiconductor device according to the above-defined method, the apparatus comprising means for forming a gate structure on a semiconductor substrate, means for performing heavy impurity doping in portions of said semiconductor substrate not covered by said gate structure so as to partially form source and drain regions of said semiconductor device, means for removing a first layer from an upper surface and sidewalls of said gate structure, means for performing light impurity doping in portions of said semiconductor substrate not covered by said gate structure to complete said source and drain regions of said semiconductor device, means for removing a second layer from the upper surface and sidewalls of said gate structure, means for forming a spacer layer on the sidewalls of said gate structure and means for forming a suicide contact on the upper surface of said gate structure.
  • the present invention extends still further to a semiconductor device manufactured in accordance with the method defined above.
  • the step(s) of removing a first and/or second layer from the upper surface and the sidewalls of the gate structure comprises an etching process, for example, an anisotropic reactive-ion-etching process.
  • the step of removing a first and/or second layer from the upper surface and the sidewalls of the gate structure comprises an oxidation process, beneficially coupled with gas implantation, preferably Argon and/or Nitrogen implantation.
  • the step of removing a second layer from the upper surface and the sidewalls of the gate structure is followed by an annealing process.
  • Figure 1 is a schematic illustration of the process flow of a fabrication process according to the prior art
  • Figure 2 is a schematic illustration of the process flow of a fabrication process according to a first exemplary embodiment of the present invention
  • Figure 3 is a schematic illustration of the process flow of a fabrication process according to a second exemplary embodiment of the present invention.
  • a conventional integrated circuit device defined in a semiconductor wafer 10 made of silicon includes a dielectric layer 12 having a thickness of about 10 to 20 nanometres (nm). Overlying the dielectric layer 12 is a conventional heavily doped polysilicon gate 14. The exposed surface of the polysilicon gate 14 is provided with a silicon dioxide layer SiO 16 by, for example, a standard low-pressure chemical-vapour- deposition (LPCVD) process. Subsequently in, for example, a LPCVD step, a layer 18 of silicon nitride is deposited on the top surface of the structure.
  • LPCVD low-pressure chemical-vapour- deposition
  • an anisotropic reactive-ion-etching (RIE) step all of the nitride layer 18 is removed, except for the relatively thick, sloped wall portions 20.
  • exposed portions of the underlying layer 16 are also thereby etched away, as shown in Figure lb.
  • this RIE step may be carried out by utilising a known plasma derived from a standard mixture of CO 2 , CHF 3 and He. Such an etchant does not significantly affect the surface of the gate 14.
  • the structure may then be subjected to a standard O 2 plasma, so as to remove from the surface of the gate 14 any polymer formed thereon during the etching step.
  • each adjoining pair of nitride and oxide portions constitute an offset spacer 21.
  • a blanket implant step is performed to form the LDD portion 24 of the n- channel transistor.
  • this step may comprise implanting phosphorous ions at an energy of around, say, 50,000 to 70,000 electron volts, and the resultant structure is illustrated in Figure lc of the drawings.
  • a spacer 25 is formed on the sidewall of each offset spacer 21, by deposition of a layer of, for example, silicon nitride and then etching, as before, to remove the portion of that layer covering the top of the gate 14.
  • the fabrication of the offset spacers leads to four possible dispersion sources, whereas in order to ensure good process control, it is highly desirable to reduce dispersion. Moreover, with new technologies, it is crucial to achieve the shallowest possible junctions, to which over-diffusion of the dopant is not conducive. Finally, for throughput reasons, it is highly desirable to minimise the number of process steps, especially deposition steps, which are very time-consuming.
  • a method of fabricating a semiconductor device according to a first exemplary embodiment of the invention is proposed.
  • Said fabrication method is particularly advantageous for high dielectric permittivity gate oxide or metal gates comprising, for example, SiGe or TiN.
  • a semiconductor wafer 10 made of silicon and including a dielectric layer 12 having a thickness of about 10 to 20 nanometres (nm).
  • Said dielectric layer preferably includes a high dielectric permittivity layer (for example HfO 2 ).
  • a gate structure 14_including poly-silicon is an insulator.
  • the next step is an ion implanting step which is performed through the dielectric layer 12 to form a heavily doped region 126 and a gate electrode layer 15 on the top of the gate structure.
  • the heavily doped region 126 partially forms a source/drain region.
  • the ion implanting step is a conventional one comprising, for example, implanting Arsenic As ions at an energy of around 10 keV or Bore B ions at an energy of around 3 keV.
  • the heavily doped region corresponds to a concentration of doping elements higher than a predetermined threshold which equals, in general, 10 atomes/cm .
  • etching step 15 is etched, by means of, for example, an anisotropic reactive-ion-etching (RIE) step, as referred to above, to expose a small peripheral portion of the gate structure 14.
  • RIE reactive-ion-etching
  • Said first etching step is thus adapted to remove in a single step a first layer, preferably of substantially uniform thickness, from the upper surface and sidewalls of the gate structure 14.
  • a blanket implant step is then performed through the dielectric layer 12 to form the LDD portion 124 of the n-channel transistor, which completes the source/drain region of the device.
  • this step may comprise implanting phosphorous ions at an energy of around 50 to 70 keV.
  • the lightly doped portion 124 corresponds to a concentration of doping elements much lower than a predetermined threshold which equals, in general, 10 18 atomes/cm 3 .
  • the dielectric layer 12, except for the portion thereof covered by the gate structure 14, is removed by a second etching step, as is a further small peripheral portion, preferably of substantially uniform thickness, of the gate structure 14 including the gate electrode layer 15, and the resultant structure is illustrated in Figure 2d.
  • a relatively short annealing step at elevated temperatures is then carried out to fit the new atoms introduced by implantation into the substrate crystal lattice.
  • the annealing step duration is, for example, lower than one second and is applied, for example, at a temperature equal to or higher than 1000°C. Said annealing step causes diffusion of the doping elements into the substrate (and into the gate) as illustrated by the arrows in Figure 2e.
  • a spacer 125 is formed on the sidewalls of the polysilicon gate 14, by deposition of a layer of, for example, silicon nitride and then etching, as before, to remove the portion of that layer covering the top of the gate 14, as illustrated in Figure 2f. Then self-aligned suicide contacts 28 are formed for the drain, source and gate of the device, as shown in Figure 2g, as before.
  • Said suicides are, for example, of the CoSi 2 or NiSi 2 type.
  • This spacer formation step is necessary to ensure good silicidation (i.e. no bridging).
  • Another advantage of this approach is the resultant capability for implantation of further pockets after the second gate etching step, so the spacer can be accurately located relative to the LDD portions.
  • a semiconductor wafer 10 made of silicon and including a dielectric layer 12 having a thickness of about 10 to 20 nanometres (nm).
  • Said dielectric layer includes, for example, an oxide (for example SiO 2 ), an oxy-nitride (for example SiO +Si3N 4 ) or a high dielectric permittivity material (for example HfO 2 ).
  • a gate structure 14 including poly-silicon.
  • the first step is an ion implanting step which is performed to form a heavily doped region 126 and a gate electrode layer 15 on the top of the gate structure. Said doped region 126 partially forms a source/drain region.
  • the next step comprises the oxidation of the gate 14, together with Argon (Ar) and Nitrogen (N 2 ) implantation to create an oxide layer 17 around the outer walls of the gate 14, as illustrated in Figure 3b of the drawings.
  • Ar and N 2 implantation favours oxidation of the sidewalls of the gate.
  • Said oxidation step is thus adapted to oxidise in a single step a first layer, preferably of substantially uniform thickness, from the upper surface and sidewalls of the gate structure 14.
  • This oxide layer acts as a good barrier material for the subsequent LDD implantation step (as before) which completes the source/drain region of the device, and the resultant structure is illustrated in Figure 3c of the drawings. Said oxide layer is then removed thanks to a hydrofluoric acid HF cleaning.
  • the gate 14 is once again oxidised, together with Argon and nitrogen implantation to form another oxide layer 19 around the outer walls of the gate structure 14, preferably of substantially uniform thickness.
  • the oxide layer acts as a good insulator during the subsequent annealing step, as illustrated in Figure 3e.
  • Said oxide layer is then removed thanks to a HF cleaning together with the dielectric layer 12, except for the portion thereof covered by the gate structure 14.
  • a spacer 125 is formed on the sidewalls of the polysilicon gate 14, by deposition of a layer of, for example, silicon nitride and then etching, as before, to remove the portion of that layer covering the top of the gate 14, as illustrated in Figure 3f.
  • Self-aligned suicide contacts 28 are then formed for the drain, source and gate of the device, as shown in Figure 3g, as before.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé pour former un composant à semi-conducteur, ce procédé comportant les étapes séquentielles consistant à former, sur un substrat semi-conducteur (10), une structure de grille (14) comportant une couche électrode de grille (15) formant une surface supérieure de ladite structure de grille, à réaliser un fort dopage par impuretés dans des parties (126) dudit substrat semi-conducteur (10) non recouvertes par ladite structure de grille (14) en vue de former partiellement des régions de source et de drain dudit composant à semi-conducteur, à éliminer en une seule étape une première couche, d'épaisseur sensiblement uniforme, de la surface supérieure et des flancs de ladite structure de grille (14), à réaliser un faible dopage par impuretés dans des parties (124) dudit substrat semi-conducteur (10) non recouvertes par ladite structure de grille (14) en vue d'achever lesdites régions de source et de drain dudit composant à semi-conducteur, à éliminer en une seule étape une deuxième couche, d'épaisseur sensiblement uniforme, de la surface supérieure et des flancs de ladite structure de grille (14), à former une couche intercalaire (125) sur les flancs de ladite structure de grille (14) et à former un contact à base de siliciure (28) sur la surface supérieure de ladite structure de grille (14).
PCT/IB2004/003992 2003-12-10 2004-12-03 Procede et appareil pour la fabrication de composants de circuits integres a semi-conducteurs metal-oxyde WO2005057663A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03300256 2003-12-10
EP03300256.9 2003-12-10

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WO2005057663A2 true WO2005057663A2 (fr) 2005-06-23
WO2005057663A3 WO2005057663A3 (fr) 2005-10-13

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008121327A1 (fr) * 2007-03-30 2008-10-09 Advanced Micro Devices, Inc. Procédé de formation de structure de semi-conducteur
CN101770953B (zh) * 2008-12-31 2012-07-11 中芯国际集成电路制造(上海)有限公司 Pmos器件的ldd的形成方法及pmos器件的制造方法
WO2019055415A1 (fr) * 2017-09-12 2019-03-21 Applied Materials, Inc. Appareil et procédés de fabrication de structures semi-conductrices utilisant une couche barrière protectrice
US10714331B2 (en) 2018-04-04 2020-07-14 Applied Materials, Inc. Method to fabricate thermally stable low K-FinFET spacer
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
US10854483B2 (en) 2017-11-16 2020-12-01 Applied Materials, Inc. High pressure steam anneal processing apparatus
US10957533B2 (en) 2018-10-30 2021-03-23 Applied Materials, Inc. Methods for etching a structure for semiconductor applications
US10998200B2 (en) 2018-03-09 2021-05-04 Applied Materials, Inc. High pressure annealing process for metal containing materials
US11018032B2 (en) 2017-08-18 2021-05-25 Applied Materials, Inc. High pressure and high temperature anneal chamber
US11227797B2 (en) 2018-11-16 2022-01-18 Applied Materials, Inc. Film deposition using enhanced diffusion process
US11462417B2 (en) 2017-08-18 2022-10-04 Applied Materials, Inc. High pressure and high temperature anneal chamber
US11527421B2 (en) 2017-11-11 2022-12-13 Micromaterials, LLC Gas delivery system for high pressure processing chamber
US11581183B2 (en) 2018-05-08 2023-02-14 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US11610773B2 (en) 2017-11-17 2023-03-21 Applied Materials, Inc. Condenser system for high pressure processing system
US11705337B2 (en) 2017-05-25 2023-07-18 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US11749555B2 (en) 2018-12-07 2023-09-05 Applied Materials, Inc. Semiconductor processing system
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film

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US8012817B2 (en) * 2008-09-26 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance improving method with metal gate

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US6103559A (en) * 1999-03-30 2000-08-15 Amd, Inc. (Advanced Micro Devices) Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
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US6235564B1 (en) * 1999-07-27 2001-05-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing MISFET
US6528376B1 (en) * 2001-11-30 2003-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Sacrificial spacer layer method for fabricating field effect transistor (FET) device

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US5672890A (en) * 1994-09-14 1997-09-30 Sumitomo Electric Industries Field effect transistor with lightly doped drain regions
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US6103559A (en) * 1999-03-30 2000-08-15 Amd, Inc. (Advanced Micro Devices) Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
US6235564B1 (en) * 1999-07-27 2001-05-22 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing MISFET
US6528376B1 (en) * 2001-11-30 2003-03-04 Taiwan Semiconductor Manufacturing Co., Ltd. Sacrificial spacer layer method for fabricating field effect transistor (FET) device

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7727827B2 (en) 2007-03-30 2010-06-01 Globalfoundries Inc. Method of forming a semiconductor structure
WO2008121327A1 (fr) * 2007-03-30 2008-10-09 Advanced Micro Devices, Inc. Procédé de formation de structure de semi-conducteur
CN101770953B (zh) * 2008-12-31 2012-07-11 中芯国际集成电路制造(上海)有限公司 Pmos器件的ldd的形成方法及pmos器件的制造方法
US11705337B2 (en) 2017-05-25 2023-07-18 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US11462417B2 (en) 2017-08-18 2022-10-04 Applied Materials, Inc. High pressure and high temperature anneal chamber
US11694912B2 (en) 2017-08-18 2023-07-04 Applied Materials, Inc. High pressure and high temperature anneal chamber
US11018032B2 (en) 2017-08-18 2021-05-25 Applied Materials, Inc. High pressure and high temperature anneal chamber
US11469113B2 (en) 2017-08-18 2022-10-11 Applied Materials, Inc. High pressure and high temperature anneal chamber
WO2019055415A1 (fr) * 2017-09-12 2019-03-21 Applied Materials, Inc. Appareil et procédés de fabrication de structures semi-conductrices utilisant une couche barrière protectrice
US11177128B2 (en) 2017-09-12 2021-11-16 Applied Materials, Inc. Apparatus and methods for manufacturing semiconductor structures using protective barrier layer
US11756803B2 (en) 2017-11-11 2023-09-12 Applied Materials, Inc. Gas delivery system for high pressure processing chamber
US11527421B2 (en) 2017-11-11 2022-12-13 Micromaterials, LLC Gas delivery system for high pressure processing chamber
US10854483B2 (en) 2017-11-16 2020-12-01 Applied Materials, Inc. High pressure steam anneal processing apparatus
US11610773B2 (en) 2017-11-17 2023-03-21 Applied Materials, Inc. Condenser system for high pressure processing system
US10998200B2 (en) 2018-03-09 2021-05-04 Applied Materials, Inc. High pressure annealing process for metal containing materials
US11881411B2 (en) 2018-03-09 2024-01-23 Applied Materials, Inc. High pressure annealing process for metal containing materials
US10714331B2 (en) 2018-04-04 2020-07-14 Applied Materials, Inc. Method to fabricate thermally stable low K-FinFET spacer
US11581183B2 (en) 2018-05-08 2023-02-14 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US11361978B2 (en) 2018-07-25 2022-06-14 Applied Materials, Inc. Gas delivery module
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
US10957533B2 (en) 2018-10-30 2021-03-23 Applied Materials, Inc. Methods for etching a structure for semiconductor applications
US11227797B2 (en) 2018-11-16 2022-01-18 Applied Materials, Inc. Film deposition using enhanced diffusion process
US11749555B2 (en) 2018-12-07 2023-09-05 Applied Materials, Inc. Semiconductor processing system
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film

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Publication number Publication date
TW200535923A (en) 2005-11-01
WO2005057663A3 (fr) 2005-10-13

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