WO2005052612A3 - Ein- und ausgangsschaltung eines integrierten schaltkreises, verfahren zum testen eines integrierten schaltkreises sowie integrierter schaltkreis mit einer solchen ein- und ausgangsschaltung - Google Patents
Ein- und ausgangsschaltung eines integrierten schaltkreises, verfahren zum testen eines integrierten schaltkreises sowie integrierter schaltkreis mit einer solchen ein- und ausgangsschaltung Download PDFInfo
- Publication number
- WO2005052612A3 WO2005052612A3 PCT/DE2004/002588 DE2004002588W WO2005052612A3 WO 2005052612 A3 WO2005052612 A3 WO 2005052612A3 DE 2004002588 W DE2004002588 W DE 2004002588W WO 2005052612 A3 WO2005052612 A3 WO 2005052612A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- input
- circuit
- integrated switching
- switching circuit
- output
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318566—Comparators; Diagnosing the device under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318572—Input/Output interfaces
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/439,450 US7453282B2 (en) | 2003-11-24 | 2006-05-24 | Input and output circuit of an integrated circuit and a method for testing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10355116.6A DE10355116B4 (de) | 2003-11-24 | 2003-11-24 | Ein- und Ausgangsschaltung eines integrierten Schaltkreises, Verfahren zum Testen eines integrierten Schaltkreises sowie integrierter Schaltkreis mit einer solchen Ein- und Ausgangsschaltung |
DE10355116.6 | 2003-11-24 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/439,450 Continuation US7453282B2 (en) | 2003-11-24 | 2006-05-24 | Input and output circuit of an integrated circuit and a method for testing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005052612A2 WO2005052612A2 (de) | 2005-06-09 |
WO2005052612A3 true WO2005052612A3 (de) | 2005-11-17 |
Family
ID=34530309
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2004/002588 WO2005052612A2 (de) | 2003-11-24 | 2004-11-23 | Ein- und ausgangsschaltung eines integrierten schaltkreises, verfahren zum testen eines integrierten schaltkreises sowie integrierter schaltkreis mit einer solchen ein- und ausgangsschaltung |
Country Status (3)
Country | Link |
---|---|
US (1) | US7453282B2 (de) |
DE (1) | DE10355116B4 (de) |
WO (1) | WO2005052612A2 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7683607B2 (en) * | 2007-09-25 | 2010-03-23 | Himax Display, Inc. | Connection testing apparatus and method and chip using the same |
US7834640B2 (en) * | 2007-09-26 | 2010-11-16 | Nokia Corporation | System and method for testing electrical connection |
US7685484B2 (en) * | 2007-11-14 | 2010-03-23 | International Business Machines Corporation | Methods for the support of JTAG for source synchronous interfaces |
EP2093580B1 (de) | 2008-02-25 | 2012-08-15 | Dialog Semiconductor GmbH | Versorgungsstrombasierte Prüfung von CMOS-Ausgangsstufen |
US8760903B2 (en) * | 2011-03-11 | 2014-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Storage circuit |
KR20120121707A (ko) * | 2011-04-27 | 2012-11-06 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이를 포함하는 반도체 시스템 |
US9322868B2 (en) * | 2011-04-27 | 2016-04-26 | SK Hynix Inc. | Test circuit and method of semiconductor integrated circuit |
KR101212777B1 (ko) * | 2011-04-27 | 2012-12-14 | 에스케이하이닉스 주식회사 | 반도체 집적회로의 테스트 회로 및 방법 |
DE102011086626A1 (de) * | 2011-11-18 | 2013-05-23 | Continental Automotive Gmbh | Integrierte Schaltung zum Schalten von Lasten, Schaltungsanordnung mit einer integrierten Schaltung und einer angeschlossenen Last und Verfahren zum Betreiben einer solchen Schaltungsanordnung |
US9239575B2 (en) | 2012-02-17 | 2016-01-19 | Siemens Aktiengesellschaft | Diagnostics for a programmable logic controller |
US8368422B1 (en) * | 2012-05-04 | 2013-02-05 | Nanya Technology Corp. | System and method for testing off-chip driver impedance |
KR102071331B1 (ko) * | 2013-05-20 | 2020-01-30 | 에스케이하이닉스 주식회사 | 누설 전류 테스트 기능을 갖는 반도체 회로 및 누설 전류 테스트 시스템 |
US9304163B2 (en) * | 2013-11-07 | 2016-04-05 | Qualcomm Incorporated | Methodology for testing integrated circuits |
US11450613B2 (en) * | 2018-03-23 | 2022-09-20 | Intel Corporation | Integrated circuit package with test circuitry for testing a channel between dies |
US11555844B2 (en) | 2018-06-29 | 2023-01-17 | Infineon Technologies Ag | High accurate contact resistance measurement method using one or more diodes |
US10591541B2 (en) * | 2018-08-13 | 2020-03-17 | Micron Technology, Inc. | Comparator |
CN110209305B (zh) * | 2019-06-26 | 2022-07-05 | 京东方科技集团股份有限公司 | 电压输入校正电路及触控面板 |
US11313903B2 (en) * | 2020-09-30 | 2022-04-26 | Analog Devices, Inc. | Pin driver and test equipment calibration |
TWI837980B (zh) * | 2022-12-01 | 2024-04-01 | 英業達股份有限公司 | 具擴展性的傳輸線檢測系統及其方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859860A (en) * | 1994-12-16 | 1999-01-12 | Texas Instruments Incorporated | Low overhead input and output boundary scan cells |
US6199182B1 (en) * | 1997-03-27 | 2001-03-06 | Texas Instruments Incorporated | Probeless testing of pad buffers on wafer |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03143027A (ja) * | 1989-10-27 | 1991-06-18 | Fujitsu Ltd | 3値出力形d/a変換器 |
US6169420B1 (en) * | 1998-08-10 | 2001-01-02 | Motorola Inc. | Output buffer |
JP2000162284A (ja) | 1998-12-01 | 2000-06-16 | Mitsubishi Electric Corp | 半導体集積回路 |
US6397361B1 (en) * | 1999-04-02 | 2002-05-28 | International Business Machines Corporation | Reduced-pin integrated circuit I/O test |
US6262585B1 (en) | 1999-06-14 | 2001-07-17 | Intel Corporation | Apparatus for I/O leakage self-test in an integrated circuit |
US6819539B1 (en) * | 2001-08-20 | 2004-11-16 | Cypress Semiconductor Corp. | Method for circuit recovery from overstress conditions |
US7221183B2 (en) * | 2005-02-23 | 2007-05-22 | Taiwan Semiconductor Manufacturing Company | Tie-high and tie-low circuit |
-
2003
- 2003-11-24 DE DE10355116.6A patent/DE10355116B4/de not_active Expired - Fee Related
-
2004
- 2004-11-23 WO PCT/DE2004/002588 patent/WO2005052612A2/de active Application Filing
-
2006
- 2006-05-24 US US11/439,450 patent/US7453282B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859860A (en) * | 1994-12-16 | 1999-01-12 | Texas Instruments Incorporated | Low overhead input and output boundary scan cells |
US6199182B1 (en) * | 1997-03-27 | 2001-03-06 | Texas Instruments Incorporated | Probeless testing of pad buffers on wafer |
Non-Patent Citations (1)
Title |
---|
SUNTER S K ET AL: "Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost", PROCEEDINGS INTERNATIONAL TEST CONFERENCE 2002. ITC 2002. BALTIMORE, MD, OCT. 7-10, 2002, INTERNATIONAL TEST CONFERENCE, NEW YORK, NY : IEEE, US, 7 October 2002 (2002-10-07), pages 446 - 455, XP010609771, ISBN: 0-7803-7542-4 * |
Also Published As
Publication number | Publication date |
---|---|
WO2005052612A2 (de) | 2005-06-09 |
DE10355116A1 (de) | 2005-06-02 |
US7453282B2 (en) | 2008-11-18 |
US20060273820A1 (en) | 2006-12-07 |
DE10355116B4 (de) | 2016-07-14 |
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