Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
  • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
  • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

• the present application relates to integrated circuit design, and more particularly to designing integrated circuits to optimize manufacturability.
• IP intellectual property
• test chips are designed and processed in a manufacturing facility to provide information that allows for the design and creation of the library.
• the test chips contain an array of representative devices and interconnection geometries, which are analyzed to generate device models suitable for use by electrical-level simulators, such as SPICE, that are utilized in the characterization of the library design elements, to produce performance views of the corresponding library design elements.
• the test chips are also analyzed to generate design rules utilized in the design of the library design elements.
• the layout of the library design elements is described in library views that, for example, contain footprint information of the library design element.
• the test chips are also analyzed to create a design kit that provides a user interface for the design of ICs, and that includes the SPICE models, the Design Rules, and the corresponding tools for automated checking of compliance with these rules.
• test chips that are used in conventional design systems do not contain comprehensive structures that are designed for an assessment or prediction of the manufacturability for the passive or active components that are used for the construction of the library and the product ICs. Therefore, it follows that the library design elements that are created by the existing design systems have not been evaluated sufficiently with respect to a prediction of their manufacturability.
• Each cell design that is created, utilizing the Design Kit, is represented using a computer readable format, such as GDSII.
• GDSII computer readable format
• LEF is an example of a library view that describes the characteristics required by a router, and includes footprint and port location information.
• a typical library contains on the order of 500 cells. However, within the assembly of the library cells, there are multiple layout representations for a given logic function. These "variants" provide different performance characteristics that can be chosen and optimized for a specific application. For example, high performance, high power, with low density, or low performance, low power, with high density options for the same logical function, are typically available in the variant versions containing in the library. However, since no library views contain manufacturability attributes, the variants created by the existing art do not provide choices regarding specific manufacturability related factors. Also, existing commercial software applications using the typical library views are not able to extract or use manufacturability characteristics for any design element in the library.
• a high-level hardware description of the functionality of the IC is mapped into basic binary operators and logic arrays (logic decomposition) to produce a representation referred to as uncommitted logic.
• logic decomposition logic decomposition
• the uncommitted logic is mapped into a specific logic connectivity diagram, often referred to as a gate-level netlist.
• a block place and route step creates a layout at the block level, consisting of the selected standard cells, and connections in the routing levels to connect all of the elements.
• the layout is represented in various formats, e.g., GDSII.
• a final verification step ensures that all the design constraints are met.
• two or more of the steps between the high-level hardware description and the block level layout are executed simultaneously by one software application. Design flows with this type of approach are often denoted as "physical synthesis" flows.
• the selection of the library design elements is determined by specific design constraints that are limited to the optimization of metrics, such as speed and power, and area considerations. No substantial manufacturability metric is addressed; however, some area based manufacturability models are used to indirectly estimate the chip costs.
• Library design elements are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process.
• the library design elements from a library are obtained.
• Manufacturability attributes of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes.
• Library views with manufacturability attributes for the library design elements are then generated, which are utilized by an electronic design automation (EDA) tool.
• EDA electronic design automation
• FIG. 1 is an exemplary design flow
• FIG. 2 is an exemplary process to determine manufacturability attributes for library design elements
• FIG. 3 depicts an exemplary learning curve
• FIG. 4 depicts an exemplary process to generate library views of library design elements with manufacturability attributes
• FIG. 5 depicts an exemplary process to generate variant design elements
• FIG. 6 depicts an exemplary design flow
• FIG. 7 depicts another exemplary design flow.
• a library of design elements is typically used to design IC chips.
• the library includes all the required views of the library design elements, including performance related attributes of the library design elements.
• conventional libraries do not provide library views with manufacturability attributes, which include yield-related attributes, which can, for example, predict the number of good dies per wafer (GDW).
• manufacturability also includes various IC characteristics, such as defects, printability, reliability, and the like. Manufacturability ultimately determines the profitability of a design.
• library design elements are analyzed to determine manufacturability attributes of the library design elements.
• Library views are then generated for the library elements to include manufacturability attributes in addition to performance attributes. These library views with manufacturability attributes can be used in a design flow to design ICs with increased manufacturability for a given process.
• FIG. 1 an exemplary design flow 100 is depicted.
• library design elements are obtained.
• manufacturability attributes which includes yield- related attributes, are determined for the library design elements.
• variants of the library design elements are generated, where the variants have different manufacturability attributes than the library design elements.
• library views which are in a computer readable format, of the manufacturability attributes of the library design elements and variants are generated.
• a manufacturability estimate of the layout is generated.
• optimum design elements are selected for an IC design.
• test chips are designed for a specific fabrication facility and/or manufacturing process, taking into account the existing design rules, and the given target manufacturability models.
• the test chips include a representation of the layout features contained within the existing library design elements.
• the data extracted from the test chips include the random yield and systematic yield factors of the existing manufacturing process.
• an exemplary process 200 is depicted to determine manufacturability attributes for library design elements.
• mask sets for test chips are generated.
• the mask sets are used in a manufacturing process that is to be used to manufacture the IC.
• test chips are manufactured using the mask sets in the manufacturing process.
• the manufactured test chips are analyzed using an analytical tool to determine the manufacturability attributes of the manufacturing process, and the manufacturability attributes of the library design elements.
• the manufacturability attributes determined from the test chips are then utilized to calibrate various simulator software tools, such as YRS, Optissimo, and the like.
• the results of the simulations of the manufacturability of the library design elements include a number of manufacturability attributes, including limited yield (LY) of the layout, manufacturing risk factors (MRF), a quantitative description of the process window, and the relationship between LY and MRF.
• LY limited yield
• MRF manufacturing risk factors
• the results of the manufacturing simulations are summarized in library views, which can be utilized by an electronic design automation (EDA) tool.
• EDA electronic design automation
• the manufacturability attributes of the manufacturing process are estimated for various future points of process maturity.
• the manufacturability of a given design element is then simulated for various time frames, which corresponds to different process maturity projections, and are also represented in the library views for the corresponding time frames and given library design element.
• Fig. 3 depicts an exemplary learning curve 302. As depicted in Fig. 3, over a period of time, the volume of ICs produced in a manufacturing process increases. Thus, at a lower volume, a lower yield is obtained at a point 304 in learning curve 302 that corresponds to an earlier period of time than point 306.
• a model that describes the relationship between the manufacturability of the routing used to interconnect the library design elements, and the nature and logic connectivity of the library design elements is defined for a given manufacturing process and design methodology. This relationship is contained in a model, which is also included in the library views.
• the library views are contained in a computer readable matrix that tabulates that various manufacturability attributes for a given collection of library design elements for various time frames and includes various interconnect manufacturability models.
• an exemplary process 400 is depicted to generate library views of library design elements with manufacturability attributes.
• a manufacturing process that is to be used to manufacture an IC design is characterized.
• test chips are manufactured using the manufacturing process.
• the manufacturing process is characterized using the test chips to produce design rules, design kits, and SPICE models, respectively.
• library vendors produce a library of design elements for the manufacturing process using the design rules, design kits, and SPICE models, which are characterized in 414.
• a timing view describes the performance characteristics of the cell in the library as a function of cell load and input voltage slope, . which is built by performing a number of SPICE simulations.
• a layout abstract view describes the characteristics required by a router, and includes footprint and port location information.
• a functional view describes the binary logic function associated with the cell.
• Other views are used to describe power consumption, signal integrity, etc. attributes of a cell. Views are generally specific to an EDA vendor's tool - i.e., a design tool reads in a cell view in order to determine the properties of the library element that are relevant for the operation performed by the tool.
• the cell layout view is also described in a compute readable format, such as, for example, GDSII.
• test chips are used to determine a range of manufacturability parameters, many of which are expressed in various forms of yield-related data. For example, in 420, random and systematic yields are determined based on the data acquired from the test chips. In addition, other manufacturability features, such as printability metrics, process margins, and reliability features, are also extracted through the analysis of the test chip data. In 422, a simulator software tool, such as yield ramp simulator (YRS), Optissimo, and the like, is calibrated using yield-related and other manufacturability data.
• YRS yield ramp simulator
• Optissimo Optissimo
• historical yield ramp data of various layout features is used by YRS to calibrate the time dependence of such features as a function of a given manufacturability volume.
• a manufacturability simulator is used to analyze each design element in the library to describe its manufacturability attributes.
• the results of the simulations include limited yield of the layout (LY), manufacturability risk factors (MRF) to describe a process window for the layout in a relative quantitative manner, both LY and MRF vs. time, and a relationship (e.g., a weighing factor) between LY and MRFs.
• LY layout
• MRF manufacturability risk factors
• library views of the library design elements with manufacturability attributes are generated. II. Generating Variants
• variants of the library design elements can be created that allow for the enhancement of the manufacturability of the library design elements, usually at a minimal expense of other design parameters, such as area, performance, or power.
• These variants are functionally equivalent to the original library design elements, but provide specific design alternatives that can enhance the manufacturability properties of the library design elements through effective compromises, e.g., area and/or performance factors.
• an exemplary process 500 is depicted to generate variant design elements (variants).
• design rules, design kits, and SPICE models are produced for a manufacturing process.
• a library is generated with library views of cells in a computer readable format, such as GSDII.
• a typical library may contain about 100 basic logic functions, and for each of these basic functions there are a number of driving capability variants, bringing the total cell count to approximately 500.
• a layout is altered to change the manufacturability attribute of the layout.
• the manufacturability attributes of the design elements are characterized by evaluation through manufacturability simulations that trade off allowable design constraints, e.g., power, area, for increased manufacturability, within certain prescribed limitations.
• library views of the variants are generated.
• the variants are characterized to produce the library views that are required by the design tools and flows.
• manufacturing attributes of the variants are generated using manufacturability simulations.
• library views of the variants with the manufacturing attributes are generated.
• the variants are stored. For a more detailed description of generating variants, see U.S. Provisional Application Serial No. 60/437,922, titled YIELD IMPROVEMENT, filed on January 2, 2003, which is incorporated herein by reference in its entirety.
• an exemplary design flow 600 is depicted.
• a library of design elements is obtained.
• a high level specification of desired functionality of the circuit is obtained.
• the specification also includes design constraints/rules, such as performance, power, and area.
• a description of the design is produced based on the specification of desired functionality and the library of design elements.
• the description is a netlist, which is a format that contains a list of the standard cells and other building blocks, and defines the connectivity between all the elements.
• library views of the blocks such as analog, memory, I/O, etc., are generated.
• a layout is created at a block level, which includes selected library design elements, and connections in the routing levels and then all the library design elements are connected.
• all the blocks are placed and connected to create a chip layout, using, in part, the library views of the blocks.
• the chip layout is verified to confirm that all the design constraints are met and the design rules are not violated.
• a description of the design is imported.
• the description can be a netlist that describes a block or chip design at a structural level, in other words by specifying it in terms of a list of interconnected basic components, a Register Transfer Level description of desired block or chip functionality, or a layout of an existing block or chip.
• the manufacturability of the design is analyzed based on the library views of the library design elements using a manufacturability analyzer.
• a manufacturability estimate for the design is generated.
• the manufacturability estimate can be a function of the manufacturing time frame, and broken down by desired design blocks.
• manufacturability views are generated for design blocks in 614, if such views have not as yet been created.
• the manufacturability estimate in 622 provides a user with the capability to understand the manufacturability characteristics of a given IC or IP block. Additionally, in one exemplary embodiment, the manufacturability estimate can be used to project the time dependence of the manufacturability of a design.
• the characteristics of a virtual learning curve can be inputted into a simulator tool, such as YRS.
• a simulator tool such as YRS.
• the historical data formatted by a YRS tool can be used to project the yield vs. time for the specific layout features of an IC design.
• Such information can provide an additional criterion for the selection of variants, allowing for a more accurate cost/profitability projection of the design over the product life.
• such a design system allows for a prediction and optimization of the yield of the entire IC design over time, given a level of the process maturity, through the identification of the lowest yielding design elements.
• the characteristics in terms of manufacturability of the library cells also change and thus the optimal mapping of a block of a chip in terms of library cells can be dynamically adjusted.
• an exemplary design flow 700 is depicted to select optimum design elements.
• a design is optimized based on manufacturability estimates and variants of the design elements from 516.
• the design can be optimized by altering the selection-function of a synthesis tool to select cells or blocks based on the manufacturability attributes as well as other design constraints.
• an existing netlist of a design can be parsed to substitute variants while maintaining the requisite functionality and respecting other design constraints.
• the revised design is analyzed to determine if the revised design complies with design constraints. If a constraint is violated, then a design is incrementally compiled to meet the constraint or an alternative next lower yielding variant with the same functionality is substituted. As depicted in Fig. 7, this process is repeated until the constraints are met. When the constraints are met, a revised design description is generated, such as a revised netlist.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Evolutionary Computation (AREA)
• Geometry (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)

Priority Applications (6)

Applications Claiming Priority (1)

Publications (1)

Family

ID=34434210

Family Applications (1)

Country Status (5)

Cited By (5)

Families Citing this family (3)

Citations (4)

Family Cites Families (2)

• 2003
  • 2003-09-16 AU AU2003272617A patent/AU2003272617A1/en not_active Abandoned
  • 2003-09-16 JP JP2005509541A patent/JP2007529100A/ja active Pending
  • 2003-09-16 WO PCT/US2003/029758 patent/WO2005036422A1/en active Application Filing
  • 2003-09-16 DE DE10394299T patent/DE10394299T5/de not_active Withdrawn
  • 2003-09-16 CN CNB038270803A patent/CN100474311C/zh not_active Expired - Fee Related

Patent Citations (4)

Non-Patent Citations (4)

Also Published As

Similar Documents

Legal Events