WO2005034201A2 - Metal-insulator-metal capacitor and method of fabrication - Google Patents

Metal-insulator-metal capacitor and method of fabrication Download PDF

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Publication number
WO2005034201A2
WO2005034201A2 PCT/US2004/032405 US2004032405W WO2005034201A2 WO 2005034201 A2 WO2005034201 A2 WO 2005034201A2 US 2004032405 W US2004032405 W US 2004032405W WO 2005034201 A2 WO2005034201 A2 WO 2005034201A2
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WIPO (PCT)
Prior art keywords
top surface
conductive diffusion
dielectric
bottom electrode
mim
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PCT/US2004/032405
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French (fr)
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WO2005034201A3 (en
Inventor
Douglas D. Coolbaugh
Ebenezer E. Eshun
Jeffrey P. Gambino
Zhong-Xiang He
Vidhya Ramachandran
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International Business Machines Corporation
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Priority to JP2006534156A priority Critical patent/JP4829792B2/en
Priority to EP04789450A priority patent/EP1671358A4/en
Publication of WO2005034201A2 publication Critical patent/WO2005034201A2/en
Publication of WO2005034201A3 publication Critical patent/WO2005034201A3/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the field of semiconductor structures and processing; more specifically, it relates to a metal-insulator-metal (MIM) capacitor compatible with high K dielectric materials and copper metallurgy and the method of fabricating the MIM.
  • MIM metal-insulator-metal
  • MIM capacitors are increasingly being used in integrated circuits, especially those integrated circuits used in radio frequency (RF) and other high-frequency applications.
  • RF radio frequency
  • the requirements for high performance capacitors compatible with ever high frequency applications has driven the industry to use high-k dielectric materials for the insulator in the MIM capacitor.
  • high-k dielectrics have serious shortcomings when used in integrated circuits having copper interconnections, most notably the poor resistance to copper diffusion, which can lead to yield or reliability problems. Therefore, there is a need for a MIM structure and fabrication method compatible with copper interconnection technology.
  • a first aspect of the present invention is an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion banier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric.
  • a second aspect of the present invention is an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer; a conductive diffusion banier in direct contact with a top surface of the bottom electrode, the top surface of the bottom electrode recessed below a top surface of the interlevel dielectric layer, the top surface of the conductive diffusion banier co-planer with the top surface of the interlevel dielectric layer; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric.
  • a third aspect of the present invention is a method of fabricating an electronic device, comprising: (a) providing a semiconductor substrate (b) forming an interlevel dielectric layer on the semiconductor substrate; (c) forming a copper bottom electrode in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; (d) forming a conductive diffusion banier in direct contact with the top surface of the bottom electrode; (e) forming a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and (f) forming a top electrode in direct contact with a top surface of the MIM dielectric.
  • a fourth aspect of the present invention is a method of fabricating an electronic device, comprising: (a) providing a semiconductor substrate; (b) forming an interlevel dielectric layer on the semiconductor substrate; (c) forming a copper bottom electrode in the interlevel dielectric layer; (d) forming a conductive diffusion banier in direct contact with a top surface of the bottom electrode, the top surface of the bottom electrode recessed below a top surface of the interlevel dielectric layer, the top surface of the conductive diffusion banier co-planer with the top surface of the interlevel dielectric; (e) forming a MIM dielectric in direct contact with the top surface of the conductive diffusion banier; and (f) forming a top electrode in direct contact with a top surface of the MIM dielectric.
  • FIG. 1A is a cross-sectional view of an exemplary MIM capacitor according to the present invention
  • FIG. IB is a top plan view and FIG. 1C a cross-sectional view through line 1C-1C of FIG. IB, of an interconnect structure incorporating a MIM capacitor according to the present invention
  • FIGs. 2A through 2F are cross-sectional views illustrating fabrication of a MIM capacitor according to a first embodiment of the present invention
  • FIG. 3 A is a top view and FIG. 3B is a cross-sectional view through line SB- SB of FIG. 3 A, of the contact to a resistor according to the present invention
  • FIGs. 4A through 4E are cross-sectional views illustrating fabrication of a
  • FIG. 1A is a cross-sectional view of an exemplary MIM capacitor 100 according to the present invention.
  • FIG. 1A is a cross-sectional view of an exemplary MIM capacitor 100 according to the present invention.
  • MIM capacitor 100 includes a bottom electrode 105 comprising a copper core conductor 110 and a conductive liner 115.
  • MIM capacitor 100 further includes a conductive diffusion banier 120 formed on a top surface 125 of bottom electrode 105, a dielectric layer 130 formed on a top surface 135 of conductive diffusion barrier 120 and a top electrode 140 formed on a top surface 145 of MIM dielectric 130.
  • Diffusion banier 120 is intended to prevent copper diffusion out of bottom electrode 105 as well as prevent formation of CuO by reaction of copper core conductor 110 with MIM dielectric 130 when dielectric MIM 130 includes oxides.
  • Top electrode 140 includes a core conductor 155, an optional bottom conductor 160 and an optional top conductor 165. While in FIG.
  • conductive diffusion barrier 120 extends past sidewalls 150 of lower electrode 105 this feature does not occur in each and every embodiment of the present invention.
  • the geometrical relationships between bottom electrode 105, conductive diffusion banier 120, dielectric 130 and top electrode 140 are described infra in relationship to each of the various embodiments of the present invention.
  • conductive liner 115 comprises Ta, TaN or combinations of layers thereof.
  • conductive diffusion banier 120 includes a layer about 5 to 200 nm in thickness of a refractory metal such as W, Ta or TaN, a conductive material such as WN, TaN, TaSiN, Pt, IrO 2 or RuO 2 or combinations of layers thereof.
  • MIM dielectric 130 includes a layer about 2 to 20 nm in thickness of SiO 2 , Si 3 N 4 or SiC, a high K dielectric such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 or Al 2 O 3 , or combinations of layers thereof.
  • top electrode 140 has a thickness of about 50 to 300nm and core conductor 155 of top electrode 140 comprises Al or W and top and bottom conductors 160 and 165 comprise TiN or TaN. All embodiments of the present invention utilize these materials in MIM capacitors.
  • FIG. IB is a top plan view and FIG. 1C a cross-sectional view through line
  • FIG. IB 1C-1C of FIG. IB, of an interconnect structure incorporating a MIM capacitor according to the present invention.
  • FIGs. IB and 1C are exemplary of the integration of the MIM capacitor of the present invention into the damascened wiring levels of an integrated circuit device.
  • An exemplary interlevel dielectric (ILD) stack 170 is formed on a top surface 175 of a semiconductor substrate 180.
  • ILD stack 170 includes a first ILD 185 formed on top surface 175 of substrate 180 and a second ILD 190 formed on a top surface 195 of second ILD 190.
  • Formed in first ILD 185 is bottom electrode 105.
  • Bottom electrode 105 also serves as an electrical wiring connection to the MIM.
  • second ILD 190 Formed in second ILD 190 are conductive diffusion banier 120, dielectric 130 and top electrode 140. Also formed in second ILD 195 is a conductor 200 for electrical connection to top plate 140 of the MIM capacitor through via 205. Conductor 200 and via 205 comprises a copper core 210 and a conductive liner 215. While two ILD levels are illustrated in FIG. 1C, any number of ILD levels may be used in and integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels, the MIM dielectric and top electrode in the upper of the two ILD levels. The conductive diffusion banier may be located in either the upper or lower ILD level or both.
  • FIGs. 2A through 2F are cross-sectional views illustrating fabrication of a MIM capacitor according to a first embodiment of the present invention.
  • an ILD 220 is formed on a top surface 222 of semiconductor substrate 224.
  • Formed in ILD 220 are a bottom electrode 226 A and a conductor 226B.
  • Bottom electrode 226A includes a copper core conductor 228A and a conductive liner 230A.
  • Conductor 226B includes a copper core conductor 228B and a conductive liner 230B.
  • Bottom electrode 226A and conductor 226B are formed by a damascene process.
  • a damascene process trenches are formed in an ILD by photo-lithographically patterning a masking layer applied over the ILD, performing a reactive ion etch (RIE) of the ILD, removing the masking layer, depositing a conductive liner, depositing a copper seed layer deposition, copper plating to fill the trench and performing a chemical- mechanical-polish (CMP) process to co-planarize the top surfaces of the copper and conductive liner and ILD.
  • RIE reactive ion etch
  • CMP chemical- mechanical-polish
  • a conductive diffusion barrier layer is deposited, photo- lithographically patterned and an RIE process performed to form conductive diffusion barriers 232A and 232B, a resistor 232C and an alignment mark 232D on a top surface 234 of ILD 220.
  • conductive diffusion banier s 232A and 232B overlap first and second conductors 226A and 226B respectively. Conductive diffusion banier materials and thicknesses have been described supra.
  • a blanket MIM dielectric layer 236 is deposited. MIM dielectric materials and thicknesses have been described supra.
  • a conductor is deposited, photo-lithographically patterned and RIE etched to form a top electrode 238 on a top surface 240 of MIM dielectric layer 236.
  • Top electrode 238 is aligned over conductive diffusion banier 232 A and bottom electrode 226 A.
  • Top electrode 238 negatively overlaps (i.e. is smaller than) conductive diffusion banier 232A.
  • Top electrode materials and thicknesses have been described supra.
  • an optional RIE stop layer 242 is deposited on top surface 240 of MIM dielectric layer 236 and on a top surface 246 and sidewalls 248 of top electrode 238.
  • RIE stop layer 242 has a thickness of about 5 to 50 nm and comprises Si 3 N .
  • a second ILD layer 250 is deposited on a top surface 252 of RIE stop layer 242.
  • Conductors 254A, 254B and 254C having integral vias 256A, 256B and 256C respectively are formed to electrically contact top electrode 238, conductor 226B and resistor 232C respectively, through RIE stop layer 242.
  • Conductors 254A, 254B and 254C are formed by a dual damascene process.
  • conductors are formed in an ILD by photo-lithographically patterning a first masking layer applied over the ILD, performing an RIE of the ILD to etch trenches in the ILD, removing the first masking layer, photo-lithographically patterning a second masking layer applied over the ILD and trenches, performing an RIE of the ILD to etch vias in the bottom of the trenches, removing the second masking layer, depositing a conductive liner, depositing a copper seed layer deposition, copper plating to fill the trench and performing a CMP process to co-planarize the surfaces of the copper and the conductive liner and ILD. While two ILD levels are illustrated in FIG.
  • FIG. 3A is a top view and FIG. 3B is a cross-sectional view through line 3B- 3B of FIG. 3 A, of the contact to resistor 232C according to the present invention.
  • a first conductor 254C1 electrically contacts a first end 256A of resistor 232C and a second conductor 254C2 electrically contacts a second end 256B of the resistor.
  • FIGs. 4A through 4E are cross-sectional views illustrating fabrication of a
  • an ILD 320 is formed on a top surface 322 of semiconductor substrate 324.
  • Formed in ILD 320 are a bottom electrode 326A and a conductor 328A.
  • Bottom electrode 326A includes a copper core conductor 328A and a conductive liner 330A.
  • Conductor 326B includes a copper core conductor 328B and a conductive liner 330B. Conductive liner and ILD materials have been described supra.
  • Bottom electrode 326A and conductor 326B are formed by a damascene process as describes supra. Bottom electrode 326A will become the bottom electrode of a MIM capacitor and conductor 326B is a typical interconnect conductor.
  • FIG. 4A an ILD 320 is formed on a top surface 322 of semiconductor substrate 324.
  • Formed in ILD 320 are a bottom electrode 326A and a conductor 328A.
  • Bottom electrode 326A includes a copper core conductor 328A and a conductive liner 330A.
  • core conductors 328A and 328B are recessed by a wet process or an RIE process.
  • a conductive diffusion banier layer is deposited on ILD 320 of sufficient thickness to fill the recesses formed by the core etching process and a CMP process performed to form recessed conductive diffusion baniers 332A and 332B and co-planarize the conductive diffusion barriers with a top surface 334 of ILD 320. Diffusion banier materials and thicknesses have been described supra. In FIG.
  • a MIM dielectric 336 and a top electrode 338 are formed by deposition of a MIM dielectric layer on top surface 334 of ILD 320 as well as over conductive diffusion barriers 326A and 326B, deposition of a conductive layer over a top surface of the MIM dielectric layer, photo- lithographically patterning a masking layer applied over the conductive layer to define the extent of MIM dielectric 336 and top electrode 338, performing an RIE of the MIM dielectric layer and the conductive layer, and removing the masking layer.
  • Top electrode 338 is aligned over recessed conductive diffusion banier 332A and bottom electrode 326A. Top electrode 338 positively overlaps (i.e.
  • RIE stop layer 342 is deposited on a top surface 346 and sidewalls 348 of top electrode 338, exposed top surface 334 of ILD 320 and a top surface 343 of recessed conductive diffusion barrier 332B.
  • RIE stop layer 342 has a thickness of about 5 to 50 nm and comprises Si 3 N .
  • a second ILD layer 350 is deposited on a top surface 352 of RIE stop layer 342.
  • Conductors 354A and 354B having integral vias 356A and 356B respectively are formed to electrically contact top electrode 338, and recessed conductive diffusion banier 332B respectively, through RIE stop layer 342.
  • Conductors 354A and 354B are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 4E, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion barrier, MIM dielectric and top electrode in the upper of the two ILD levels.
  • FIGs. 5 A through 5F are cross-sectional views illustrating fabrication of a MIM capacitor according to a third embodiment of the present invention.
  • an ILD 420 is formed on a top surface 422 of semiconductor substrate 424. Formed in ILD 420 are a bottom electrode 426A and a conductor 426B.
  • Bottom electrode 426A includes a copper core conductor 428A and a conductive liner 430A.
  • Conductor 426B includes a copper core conductor 428B and a conductive liner 430B. Conductive liner and ILD materials have been described supra.
  • Bottom electrode 426A and conductor 426B are formed by a damascene process as describes supra. Bottom electrode 426A will become the bottom electrode of a MIM capacitor and conductor 426B is a typical interconnect conductor.
  • core conductors 428A and 428B are recessed by a wet process or an RIE process.
  • a first conductive diffusion barrier layer is deposited on ILD 420 of sufficient thickness to fill the recesses formed by the etch process and a CMP process performed to form recessed conductive diffusion barriers 432A and 432B and co- planarize the recessed conductive diffusion baniers with a top surface 434 of ILD 420.
  • Conductive diffusion banier materials and thicknesses have been described supra.
  • MIM dielectric 436A and top electrode 438A1 (on a top surface 440 of the MIM dielectric) and a cap 438B are formed as follows: First, a second conductive diffusion banier layer is deposited on top surface 434 of ILD 420 as well as over recessed conductive diffusion baniers 432A and 432B. Second, a MIM dielectric layer is deposited on top a surface of the second conductive diffusion barrier layer and a conductive layer is deposited on a top surface of the second conductive diffusion barrier layer.
  • a masking layer applied over the conductive layer is photo- lithographically patterned to define the extent of MIM dielectric 436 A, the extent of upper conductive diffusion barrier 435 A and resistor 435B, and an initial extent of top electrode 438A1 and the extent of cap 438B.
  • an RIE of the MIM dielectric layer, second conductive diffusion barrier layer and the conductive layer is performed and the masking layer removed. Conductive diffusion banier materials and thicknesses have been described supra.
  • a masking layer applied is photo-lithographically patterned and an RIE performed to define the final extent of top electrode 438A2 as well as to remove cap 438B (see FIG. 5C) from over MIM dielectric 436B.
  • Top electrode 438A2 is aligned over recessed conductive diffusion barrier 432A and upper conductive diffusion barrier 435 A and bottom electrode 426 A. Top electrode 438 A2 negatively overlaps (i.e. is smaller than) upper conductive diffusion barrier 435 A. Upper conductive diffusion banier 435 A positively overlaps (i.e. is larger than) recessed conductive diffusion banier 432A. MIM dielectric materials and thicknesses and top electrode materials and thicknesses have been described supra. In FIG.
  • an optional RIE stop layer 442 is deposited on a top surface 443 and sidewalls 444 of top electrode 438A2, a top surface 445 A and sidewalls 446 A of MIM dielectric 436A/upper conductive diffusion banier 435A, top surface 445B and sidewalls 446B of MIM dielectric 436B/resistor 435B, exposed top surface 434 of ILD 420, and a top surface 447 of recessed conductive diffusion banier 432B.
  • RIE stop layer 442 has a thickness of about 5 to 50 nm and comprises Si 3 N .
  • a second ILD layer 450 is deposited on a top surface 452 of RIE stop layer 442.
  • Conductors 454A, 454B and 454C having integral vias 456A, 456B and 456C respectively are formed to electrically contact top electrode 438A2, recessed conductive diffusion banier 432B and resistor 435B respectively, through RIE stop layer 442.
  • Conductors 454A and 454B are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 5F, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion banier, MIM dielectric and top electrode in the upper of the two ILD levels.
  • FIGs. 6A through 6F are cross-sectional views illustrating fabrication of a
  • an ILD 520 is formed on a top surface 522 of semiconductor substrate 524. Formed in ILD 520 are a bottom electrode 526A and a conductor 526 A. Bottom electrode 526A includes a copper core conductor 528A and a conductive liner 530A.
  • Conductor 526B includes a copper core conductor 528B and a conductive liner 530B.
  • Conductor 526A and conductor 526B are formed by a damascene process as described supra. Bottom electrode 526 A will become the bottom electrode of a MIM capacitor and conductor 526B is a typical interconnect conductor. In FIG. 6B, a dielectric diffusion banier layer 531 is formed on top of ILD
  • dielectric diffusion banier 531 examples include Si 3 N , SiC, SiO 2 over Si 3 N and FSG over Si3N4 having a thickness of about 5 to 50nm.
  • a conductive diffusion banier 532A is formed over bottom electrode 526A (and overlapping ILD 520) and a resistor 532B is formed on a top surface 534 of ILD 520 by a damascene process as described supra. Diffusion banier materials and thicknesses have been described supra.
  • FIG. 6C a conductive diffusion banier 532A is formed over bottom electrode 526A (and overlapping ILD 520) and a resistor 532B is formed on a top surface 534 of ILD 520 by a damascene process as described supra. Diffusion banier materials and thicknesses have been described supra.
  • FIG. 1 Diffusion banier materials and thicknesses have been described supra.
  • top electrode 538 on a top surface 540 of a MIM dielectric 536.
  • Top electrode 538 is aligned over conductive diffusion banier 532A and bottom electrode 526A.
  • Top electrode 538 positively overlaps (i.e. is larger than) conductive diffusion banier 532A.
  • Conductive diffusion banier 532A positively overlaps (i.e. is larger than) lower electrode 526A.
  • MIM dielectric materials and thicknesses and top electrode materials and thicknesses have been described supra. In FIG.
  • an optional RIE stop layer 542 is deposited on top surface 544 of top electrode 538 and sidewalls 545 of top electrode 538/MIM dielectric 536 and on a top surface 546 of resistor 532B and a top surface 547 of dielectric diffusion barrier 531.
  • RIE stop layer 542 has a thickness of about 5 to 50 nm and comprises Si 3 N 4 .
  • a second ILD layer 550 is deposited on a top surface 552 of RIE stop layer 542.
  • Conductors 554A, 554B and 554C having integral vias 556A, 556B and 556C respectively are formed to electrically contact top electrode 538, conductor 526B and resistor 532B respectively, through RIE stop layer 542.
  • Conductors 554A, 554B and 554C are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 6F, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion banier, MIM dielectric and top electrode in the upper of the two ILD levels. FIGs.
  • FIG. 7 A through 7F are cross-sectional views illustrating fabrication of a MIM capacitor according to a fifth embodiment of the present invention.
  • an ILD 620 is formed on a top surface 622 of semiconductor substrate 624.
  • Formed in ILD 620 are a bottom electrode 626A, a conductor 626B and a resistor contact 626C.
  • Bottom electrode 626A includes a copper core conductor 628A and a conductive liner 630 A.
  • Conductor 626B includes a copper core conductor 628B and a conductive liner 630B.
  • Resistor contact 626C includes a copper core conductor 628C and a conductive liner 630C.
  • Conductive liner and ILD materials have been described supra.
  • Bottom electrode 626A, conductor 626B and resistor contact 626C are formed by a damascene process as describes supra. Bottom electrode 626A will become the bottom electrode of a MIM and conductor 626B is a typical interconnect conductor.
  • core conductors 628A, 628B and 628C are recessed by a wet process or an RIE process, a first conductive diffusion banier layer is deposited on ILD 620 of sufficient thickness to fill the recesses formed by the etch process and a CMP process performed to form recessed conductive diffusion barriers 632A, 632B and 632C and co-planarize the recessed conductive diffusion barriers with a top surface 634 of ILD 620.
  • an upper conductive diffusion barrier 635 A, a resistor 635B, and an alignment mark 635C are formed by depositing a conductive diffusion barrier layer on top surface 634 of ILD 620, photo-lithographically patterning a masking layer applied to the conductive diffusion banier layer, performing an RIE process and removing the masking layer.
  • Conductive diffusion banier materials and thicknesses have been described supra.
  • FIG. 7C an upper conductive diffusion barrier 635 A, a resistor 635B, and an alignment mark 635C are formed by depositing a conductive diffusion barrier layer on top surface 634 of ILD 620, photo-lithographically patterning a masking layer applied to the conductive diffusion banier layer, performing an RIE process and removing the masking layer.
  • a MIM dielectric 636 A covering upper conductive diffusion banier 635 A, a top electrode 638 A covering MIM dielectric 636A and a dielectric cap 636B covering resistor 635B and a conductive cap 638B covering dielectric cap 636B are formed as follows: First, a MIM dielectric layer is deposited over upper conductive diffusion banier 635A, resistor 635B, alignment mark 635C and exposed top surface 634 of ILD 620. Second, a masking layer is applied over MIM dielectric layer and photo-lithographically patterned to define the extent of MIM dielectrics 636 A and 636B, an RIE of the MIM dielectric layer is performed and the masking layer removed.
  • a conductive layer is deposited over MIM dielectrics 636 A and 636B, alignment mark 635C and exposed top surface 634 of ILD 620.
  • a masking layer is applied over the conductive layer to define the extent of a top electrode 638A and a conductive cap 636B, an RIE of the conductive layer is performed and the masking layer removed.
  • Top electrode 638 is aligned over MIM dielectric 636 A and MIM dielectric is aligned over upper conductive diffusion barrier 635 A and bottom electrode 626A.
  • Top electrode 638 A positively overlaps (i.e. is larger than) MIM dielectric 636A and MIM dielectric 636A positively overlaps (I.e. is larger than) upper conductive diffusion banier 635 A.
  • an optional RIE stop layer 642 is deposited on a top surface 643 and sidewalls 644 of top electrode 638 A, top surface 645 and sidewalls 646 of conductive cap 636B, exposed top surface 634 of ILD 620, a top surface 647 of recessed conductive diffusion banier 632B and over alignment mark 635C.
  • RIE stop layer 642 has a thickness of about 5 to 50 nm and comprises Si 3 N .
  • a second ILD layer 650 is deposited on a top surface 652 of RIE stop layer 642.
  • Conductors 654A and 654B having integral vias 656A and 656B respectively are formed to electrically contact top electrode 638 A and recessed conductive diffusion banier 632B through RIE stop layer 642 respectively.
  • Conductors 654A and 654B are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 7F, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion barrier, MIM dielectric and top electrode in the upper of the two ILD levels.
  • the present invention provides a MIM structure and fabrication method compatible with copper interconnection technology as well as compatible resistor and alignment mark structures.

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Abstract

A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interievel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interievel dielectric layer, atop surface of the bottom electrode co-planer with a top surface of the interievel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

Description

METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION
TECHNICAL FIELD The present invention relates to the field of semiconductor structures and processing; more specifically, it relates to a metal-insulator-metal (MIM) capacitor compatible with high K dielectric materials and copper metallurgy and the method of fabricating the MIM.
BACKGROUND ART MIM capacitors are increasingly being used in integrated circuits, especially those integrated circuits used in radio frequency (RF) and other high-frequency applications. The requirements for high performance capacitors compatible with ever high frequency applications has driven the industry to use high-k dielectric materials for the insulator in the MIM capacitor. However, high-k dielectrics have serious shortcomings when used in integrated circuits having copper interconnections, most notably the poor resistance to copper diffusion, which can lead to yield or reliability problems. Therefore, there is a need for a MIM structure and fabrication method compatible with copper interconnection technology. DISCLOSURE OF INVENTION A first aspect of the present invention is an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion banier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. A second aspect of the present invention is an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer; a conductive diffusion banier in direct contact with a top surface of the bottom electrode, the top surface of the bottom electrode recessed below a top surface of the interlevel dielectric layer, the top surface of the conductive diffusion banier co-planer with the top surface of the interlevel dielectric layer; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. A third aspect of the present invention is a method of fabricating an electronic device, comprising: (a) providing a semiconductor substrate (b) forming an interlevel dielectric layer on the semiconductor substrate; (c) forming a copper bottom electrode in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; (d) forming a conductive diffusion banier in direct contact with the top surface of the bottom electrode; (e) forming a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and (f) forming a top electrode in direct contact with a top surface of the MIM dielectric. A fourth aspect of the present invention is a method of fabricating an electronic device, comprising: (a) providing a semiconductor substrate; (b) forming an interlevel dielectric layer on the semiconductor substrate; (c) forming a copper bottom electrode in the interlevel dielectric layer; (d) forming a conductive diffusion banier in direct contact with a top surface of the bottom electrode, the top surface of the bottom electrode recessed below a top surface of the interlevel dielectric layer, the top surface of the conductive diffusion banier co-planer with the top surface of the interlevel dielectric; (e) forming a MIM dielectric in direct contact with the top surface of the conductive diffusion banier; and (f) forming a top electrode in direct contact with a top surface of the MIM dielectric.
BRIEF DESCRIPTION OF DRAWINGS The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: FIG. 1A, is a cross-sectional view of an exemplary MIM capacitor according to the present invention; FIG. IB is a top plan view and FIG. 1C a cross-sectional view through line 1C-1C of FIG. IB, of an interconnect structure incorporating a MIM capacitor according to the present invention; FIGs. 2A through 2F are cross-sectional views illustrating fabrication of a MIM capacitor according to a first embodiment of the present invention; FIG. 3 A is a top view and FIG. 3B is a cross-sectional view through line SB- SB of FIG. 3 A, of the contact to a resistor according to the present invention; FIGs. 4A through 4E are cross-sectional views illustrating fabrication of a
MIM capacitor according to a second embodiment of the present invention; FIGs. 5 A through 5F are cross-sectional views illustrating fabrication of a MIM capacitor according to a third embodiment of the present invention; FIGs. 6A through 6F are cross-sectional views illustrating fabrication of a MIM capacitor according to a fourth embodiment of the present invention; and FIGs. 7A through 7F are cross-sectional views illustrating fabrication of a MIM capacitor according to a fifth embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1A, is a cross-sectional view of an exemplary MIM capacitor 100 according to the present invention. In FIG. 1 A, MIM capacitor 100 includes a bottom electrode 105 comprising a copper core conductor 110 and a conductive liner 115. MIM capacitor 100 further includes a conductive diffusion banier 120 formed on a top surface 125 of bottom electrode 105, a dielectric layer 130 formed on a top surface 135 of conductive diffusion barrier 120 and a top electrode 140 formed on a top surface 145 of MIM dielectric 130. Diffusion banier 120 is intended to prevent copper diffusion out of bottom electrode 105 as well as prevent formation of CuO by reaction of copper core conductor 110 with MIM dielectric 130 when dielectric MIM 130 includes oxides. Top electrode 140 includes a core conductor 155, an optional bottom conductor 160 and an optional top conductor 165. While in FIG. 1 A, conductive diffusion barrier 120 extends past sidewalls 150 of lower electrode 105 this feature does not occur in each and every embodiment of the present invention. The geometrical relationships between bottom electrode 105, conductive diffusion banier 120, dielectric 130 and top electrode 140 are described infra in relationship to each of the various embodiments of the present invention. In one example, conductive liner 115 comprises Ta, TaN or combinations of layers thereof. In one example, conductive diffusion banier 120 includes a layer about 5 to 200 nm in thickness of a refractory metal such as W, Ta or TaN, a conductive material such as WN, TaN, TaSiN, Pt, IrO2 or RuO2 or combinations of layers thereof. In one example, MIM dielectric 130 includes a layer about 2 to 20 nm in thickness of SiO2, Si3N4 or SiC, a high K dielectric such as Ta2O5, BaTiO3, HfO2, ZrO2 or Al2O3, or combinations of layers thereof. In one example, top electrode 140 has a thickness of about 50 to 300nm and core conductor 155 of top electrode 140 comprises Al or W and top and bottom conductors 160 and 165 comprise TiN or TaN. All embodiments of the present invention utilize these materials in MIM capacitors. FIG. IB is a top plan view and FIG. 1C a cross-sectional view through line
1C-1C of FIG. IB, of an interconnect structure incorporating a MIM capacitor according to the present invention. FIGs. IB and 1C are exemplary of the integration of the MIM capacitor of the present invention into the damascened wiring levels of an integrated circuit device. An exemplary interlevel dielectric (ILD) stack 170 is formed on a top surface 175 of a semiconductor substrate 180. ILD stack 170 includes a first ILD 185 formed on top surface 175 of substrate 180 and a second ILD 190 formed on a top surface 195 of second ILD 190. Formed in first ILD 185 is bottom electrode 105. Bottom electrode 105 also serves as an electrical wiring connection to the MIM. Formed in second ILD 190 are conductive diffusion banier 120, dielectric 130 and top electrode 140. Also formed in second ILD 195 is a conductor 200 for electrical connection to top plate 140 of the MIM capacitor through via 205. Conductor 200 and via 205 comprises a copper core 210 and a conductive liner 215. While two ILD levels are illustrated in FIG. 1C, any number of ILD levels may be used in and integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels, the MIM dielectric and top electrode in the upper of the two ILD levels. The conductive diffusion banier may be located in either the upper or lower ILD level or both. Examples of ILD materials include deposited oxides such as tetraethoxysilane (TEOS), fluoridated silicon oxide glass (FSG) and other chemical- vapor-deposition (CVD) oxides. FIGs. 2A through 2F are cross-sectional views illustrating fabrication of a MIM capacitor according to a first embodiment of the present invention. In FIG. 2A, an ILD 220 is formed on a top surface 222 of semiconductor substrate 224. Formed in ILD 220 are a bottom electrode 226 A and a conductor 226B. Bottom electrode 226A includes a copper core conductor 228A and a conductive liner 230A. Conductor 226B includes a copper core conductor 228B and a conductive liner 230B. Conductive liner and ILD materials have been described supra. Bottom electrode 226A and conductor 226B are formed by a damascene process. In a damascene process, trenches are formed in an ILD by photo-lithographically patterning a masking layer applied over the ILD, performing a reactive ion etch (RIE) of the ILD, removing the masking layer, depositing a conductive liner, depositing a copper seed layer deposition, copper plating to fill the trench and performing a chemical- mechanical-polish (CMP) process to co-planarize the top surfaces of the copper and conductive liner and ILD. Bottom electrode 226A will become the bottom electrode of a MIM capacitor and conductor 226B is a typical interconnect conductor. In FIG. 2B, a conductive diffusion barrier layer is deposited, photo- lithographically patterned and an RIE process performed to form conductive diffusion barriers 232A and 232B, a resistor 232C and an alignment mark 232D on a top surface 234 of ILD 220. Note conductive diffusion banier s 232A and 232B overlap first and second conductors 226A and 226B respectively. Conductive diffusion banier materials and thicknesses have been described supra. In FIG. 2C, a blanket MIM dielectric layer 236 is deposited. MIM dielectric materials and thicknesses have been described supra. In FIG. 2D, a conductor is deposited, photo-lithographically patterned and RIE etched to form a top electrode 238 on a top surface 240 of MIM dielectric layer 236. Top electrode 238 is aligned over conductive diffusion banier 232 A and bottom electrode 226 A. Top electrode 238 negatively overlaps (i.e. is smaller than) conductive diffusion banier 232A. Top electrode materials and thicknesses have been described supra. In FIG. 2E, an optional RIE stop layer 242 is deposited on top surface 240 of MIM dielectric layer 236 and on a top surface 246 and sidewalls 248 of top electrode 238. In one example, RIE stop layer 242 has a thickness of about 5 to 50 nm and comprises Si3N . In FIG. 2F, a second ILD layer 250 is deposited on a top surface 252 of RIE stop layer 242. Conductors 254A, 254B and 254C having integral vias 256A, 256B and 256C respectively are formed to electrically contact top electrode 238, conductor 226B and resistor 232C respectively, through RIE stop layer 242. Conductors 254A, 254B and 254C are formed by a dual damascene process. In a dual damascene process, conductors are formed in an ILD by photo-lithographically patterning a first masking layer applied over the ILD, performing an RIE of the ILD to etch trenches in the ILD, removing the first masking layer, photo-lithographically patterning a second masking layer applied over the ILD and trenches, performing an RIE of the ILD to etch vias in the bottom of the trenches, removing the second masking layer, depositing a conductive liner, depositing a copper seed layer deposition, copper plating to fill the trench and performing a CMP process to co-planarize the surfaces of the copper and the conductive liner and ILD. While two ILD levels are illustrated in FIG. 2F, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion banier, MIM dielectric and top electrode in the upper of the two ILD levels. FIG. 3A is a top view and FIG. 3B is a cross-sectional view through line 3B- 3B of FIG. 3 A, of the contact to resistor 232C according to the present invention. A first conductor 254C1 electrically contacts a first end 256A of resistor 232C and a second conductor 254C2 electrically contacts a second end 256B of the resistor. Vias 256C1 and 256C2 overlap, respectively, ends 256A and 256B as well as portions of sides 258A and 258B adjacent to the ends of resistor 232C. FIGs. 4A through 4E are cross-sectional views illustrating fabrication of a
MIM capacitor according to a second embodiment of the present invention. In FIG. 4A, an ILD 320 is formed on a top surface 322 of semiconductor substrate 324. Formed in ILD 320 are a bottom electrode 326A and a conductor 328A. Bottom electrode 326A includes a copper core conductor 328A and a conductive liner 330A. Conductor 326B includes a copper core conductor 328B and a conductive liner 330B. Conductive liner and ILD materials have been described supra. Bottom electrode 326A and conductor 326B are formed by a damascene process as describes supra. Bottom electrode 326A will become the bottom electrode of a MIM capacitor and conductor 326B is a typical interconnect conductor. In FIG. 4B, core conductors 328A and 328B are recessed by a wet process or an RIE process. A conductive diffusion banier layer is deposited on ILD 320 of sufficient thickness to fill the recesses formed by the core etching process and a CMP process performed to form recessed conductive diffusion baniers 332A and 332B and co-planarize the conductive diffusion barriers with a top surface 334 of ILD 320. Diffusion banier materials and thicknesses have been described supra. In FIG. 4C, a MIM dielectric 336 and a top electrode 338 (on a top surface 340 of the MIM dielectric) are formed by deposition of a MIM dielectric layer on top surface 334 of ILD 320 as well as over conductive diffusion barriers 326A and 326B, deposition of a conductive layer over a top surface of the MIM dielectric layer, photo- lithographically patterning a masking layer applied over the conductive layer to define the extent of MIM dielectric 336 and top electrode 338, performing an RIE of the MIM dielectric layer and the conductive layer, and removing the masking layer. Top electrode 338 is aligned over recessed conductive diffusion banier 332A and bottom electrode 326A. Top electrode 338 positively overlaps (i.e. is larger than) recessed conductive diffusion barrier 332 A. Conductive diffusion banier materials and thicknesses, MIM dielectric materials and thicknesses and top electrode materials and thicknesses have been described supra. In FIG. 4D, an optional RIE stop layer 342 is deposited on a top surface 346 and sidewalls 348 of top electrode 338, exposed top surface 334 of ILD 320 and a top surface 343 of recessed conductive diffusion barrier 332B. In one example, RIE stop layer 342 has a thickness of about 5 to 50 nm and comprises Si3N . In FIG. 4E, a second ILD layer 350 is deposited on a top surface 352 of RIE stop layer 342. Conductors 354A and 354B having integral vias 356A and 356B respectively are formed to electrically contact top electrode 338, and recessed conductive diffusion banier 332B respectively, through RIE stop layer 342.
Conductors 354A and 354B are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 4E, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion barrier, MIM dielectric and top electrode in the upper of the two ILD levels. FIGs. 5 A through 5F are cross-sectional views illustrating fabrication of a MIM capacitor according to a third embodiment of the present invention. In FIG. 5 A, an ILD 420 is formed on a top surface 422 of semiconductor substrate 424. Formed in ILD 420 are a bottom electrode 426A and a conductor 426B. Bottom electrode 426A includes a copper core conductor 428A and a conductive liner 430A. Conductor 426B includes a copper core conductor 428B and a conductive liner 430B. Conductive liner and ILD materials have been described supra. Bottom electrode 426A and conductor 426B are formed by a damascene process as describes supra. Bottom electrode 426A will become the bottom electrode of a MIM capacitor and conductor 426B is a typical interconnect conductor. In FIG. 5B, core conductors 428A and 428B are recessed by a wet process or an RIE process. A first conductive diffusion barrier layer is deposited on ILD 420 of sufficient thickness to fill the recesses formed by the etch process and a CMP process performed to form recessed conductive diffusion barriers 432A and 432B and co- planarize the recessed conductive diffusion baniers with a top surface 434 of ILD 420. Conductive diffusion banier materials and thicknesses have been described supra. In FIG. 5C, an upper conductive diffusion banier 435A, a resistor 435B, a
MIM dielectric 436A and top electrode 438A1 (on a top surface 440 of the MIM dielectric) and a cap 438B are formed as follows: First, a second conductive diffusion banier layer is deposited on top surface 434 of ILD 420 as well as over recessed conductive diffusion baniers 432A and 432B. Second, a MIM dielectric layer is deposited on top a surface of the second conductive diffusion barrier layer and a conductive layer is deposited on a top surface of the second conductive diffusion barrier layer. Third, a masking layer applied over the conductive layer is photo- lithographically patterned to define the extent of MIM dielectric 436 A, the extent of upper conductive diffusion barrier 435 A and resistor 435B, and an initial extent of top electrode 438A1 and the extent of cap 438B. Fourth, an RIE of the MIM dielectric layer, second conductive diffusion barrier layer and the conductive layer is performed and the masking layer removed. Conductive diffusion banier materials and thicknesses have been described supra. In FIG. 5D, a masking layer applied, is photo-lithographically patterned and an RIE performed to define the final extent of top electrode 438A2 as well as to remove cap 438B (see FIG. 5C) from over MIM dielectric 436B. The masking layer is then removed. Top electrode 438A2 is aligned over recessed conductive diffusion barrier 432A and upper conductive diffusion barrier 435 A and bottom electrode 426 A. Top electrode 438 A2 negatively overlaps (i.e. is smaller than) upper conductive diffusion barrier 435 A. Upper conductive diffusion banier 435 A positively overlaps (i.e. is larger than) recessed conductive diffusion banier 432A. MIM dielectric materials and thicknesses and top electrode materials and thicknesses have been described supra. In FIG. 5E, an optional RIE stop layer 442 is deposited on a top surface 443 and sidewalls 444 of top electrode 438A2, a top surface 445 A and sidewalls 446 A of MIM dielectric 436A/upper conductive diffusion banier 435A, top surface 445B and sidewalls 446B of MIM dielectric 436B/resistor 435B, exposed top surface 434 of ILD 420, and a top surface 447 of recessed conductive diffusion banier 432B. In one example, RIE stop layer 442 has a thickness of about 5 to 50 nm and comprises Si3N . In FIG. 5F, a second ILD layer 450 is deposited on a top surface 452 of RIE stop layer 442. Conductors 454A, 454B and 454C having integral vias 456A, 456B and 456C respectively are formed to electrically contact top electrode 438A2, recessed conductive diffusion banier 432B and resistor 435B respectively, through RIE stop layer 442. Conductors 454A and 454B are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 5F, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion banier, MIM dielectric and top electrode in the upper of the two ILD levels. FIGs. 6A through 6F are cross-sectional views illustrating fabrication of a
MIM capacitor according to a fourth embodiment of the present invention. In FIG.
6A, an ILD 520 is formed on a top surface 522 of semiconductor substrate 524. Formed in ILD 520 are a bottom electrode 526A and a conductor 526 A. Bottom electrode 526A includes a copper core conductor 528A and a conductive liner 530A.
Conductor 526B includes a copper core conductor 528B and a conductive liner 530B.
Conductive liner and ILD materials have been described supra. Bottom electrode
526A and conductor 526B are formed by a damascene process as described supra. Bottom electrode 526 A will become the bottom electrode of a MIM capacitor and conductor 526B is a typical interconnect conductor. In FIG. 6B, a dielectric diffusion banier layer 531 is formed on top of ILD
520, bottom electrode 526A and conductor 526B by deposition. Examples of suitable materials for dielectric diffusion banier 531 include Si3N , SiC, SiO2 over Si3N and FSG over Si3N4 having a thickness of about 5 to 50nm. In FIG. 6C, a conductive diffusion banier 532A is formed over bottom electrode 526A (and overlapping ILD 520) and a resistor 532B is formed on a top surface 534 of ILD 520 by a damascene process as described supra. Diffusion banier materials and thicknesses have been described supra. In FIG. 6D, first a MIM dielectric layer and then a conductive layer are deposited, photo-lithographically patterned and RIE etched to form a top electrode 538 on a top surface 540 of a MIM dielectric 536. Top electrode 538 is aligned over conductive diffusion banier 532A and bottom electrode 526A. Top electrode 538 positively overlaps (i.e. is larger than) conductive diffusion banier 532A. Conductive diffusion banier 532A positively overlaps (i.e. is larger than) lower electrode 526A. MIM dielectric materials and thicknesses and top electrode materials and thicknesses have been described supra. In FIG. 6E, an optional RIE stop layer 542 is deposited on top surface 544 of top electrode 538 and sidewalls 545 of top electrode 538/MIM dielectric 536 and on a top surface 546 of resistor 532B and a top surface 547 of dielectric diffusion barrier 531. In one example, RIE stop layer 542 has a thickness of about 5 to 50 nm and comprises Si3N4. In FIG. 6F, a second ILD layer 550 is deposited on a top surface 552 of RIE stop layer 542. Conductors 554A, 554B and 554C having integral vias 556A, 556B and 556C respectively are formed to electrically contact top electrode 538, conductor 526B and resistor 532B respectively, through RIE stop layer 542. Conductors 554A, 554B and 554C are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 6F, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion banier, MIM dielectric and top electrode in the upper of the two ILD levels. FIGs. 7 A through 7F are cross-sectional views illustrating fabrication of a MIM capacitor according to a fifth embodiment of the present invention. In FIG. 7 A, an ILD 620 is formed on a top surface 622 of semiconductor substrate 624. Formed in ILD 620 are a bottom electrode 626A, a conductor 626B and a resistor contact 626C. Bottom electrode 626A includes a copper core conductor 628A and a conductive liner 630 A. Conductor 626B includes a copper core conductor 628B and a conductive liner 630B. Resistor contact 626C includes a copper core conductor 628C and a conductive liner 630C. Conductive liner and ILD materials have been described supra. Bottom electrode 626A, conductor 626B and resistor contact 626C are formed by a damascene process as describes supra. Bottom electrode 626A will become the bottom electrode of a MIM and conductor 626B is a typical interconnect conductor. In FIG. 7B, core conductors 628A, 628B and 628C are recessed by a wet process or an RIE process, a first conductive diffusion banier layer is deposited on ILD 620 of sufficient thickness to fill the recesses formed by the etch process and a CMP process performed to form recessed conductive diffusion barriers 632A, 632B and 632C and co-planarize the recessed conductive diffusion barriers with a top surface 634 of ILD 620. Conductive diffusion banier materials and thicknesses have been described supra. In FIG. 7C, an upper conductive diffusion barrier 635 A, a resistor 635B, and an alignment mark 635C are formed by depositing a conductive diffusion barrier layer on top surface 634 of ILD 620, photo-lithographically patterning a masking layer applied to the conductive diffusion banier layer, performing an RIE process and removing the masking layer. Conductive diffusion banier materials and thicknesses have been described supra. In FIG. 7D, a MIM dielectric 636 A covering upper conductive diffusion banier 635 A, a top electrode 638 A covering MIM dielectric 636A and a dielectric cap 636B covering resistor 635B and a conductive cap 638B covering dielectric cap 636B are formed as follows: First, a MIM dielectric layer is deposited over upper conductive diffusion banier 635A, resistor 635B, alignment mark 635C and exposed top surface 634 of ILD 620. Second, a masking layer is applied over MIM dielectric layer and photo-lithographically patterned to define the extent of MIM dielectrics 636 A and 636B, an RIE of the MIM dielectric layer is performed and the masking layer removed. Third, a conductive layer is deposited over MIM dielectrics 636 A and 636B, alignment mark 635C and exposed top surface 634 of ILD 620. Fourth, a masking layer is applied over the conductive layer to define the extent of a top electrode 638A and a conductive cap 636B, an RIE of the conductive layer is performed and the masking layer removed. Top electrode 638 is aligned over MIM dielectric 636 A and MIM dielectric is aligned over upper conductive diffusion barrier 635 A and bottom electrode 626A. Top electrode 638 A positively overlaps (i.e. is larger than) MIM dielectric 636A and MIM dielectric 636A positively overlaps (I.e. is larger than) upper conductive diffusion banier 635 A. MIM dielectric materials and thicknesses and top electrode materials and thicknesses have been described supra. In FIG. 7E, an optional RIE stop layer 642 is deposited on a top surface 643 and sidewalls 644 of top electrode 638 A, top surface 645 and sidewalls 646 of conductive cap 636B, exposed top surface 634 of ILD 620, a top surface 647 of recessed conductive diffusion banier 632B and over alignment mark 635C. In one example, RIE stop layer 642 has a thickness of about 5 to 50 nm and comprises Si3N . In FIG. 7F, a second ILD layer 650 is deposited on a top surface 652 of RIE stop layer 642. Conductors 654A and 654B having integral vias 656A and 656B respectively are formed to electrically contact top electrode 638 A and recessed conductive diffusion banier 632B through RIE stop layer 642 respectively. Conductors 654A and 654B are formed by a dual damascene process as described supra. While two ILD levels are illustrated in FIG. 7F, any number of ILD levels may be used in an integrated circuit device and the MIM capacitor may be physically located in any two adjacent ILD levels, the bottom electrode in the lower of the two ILD levels and the conductive diffusion barrier, MIM dielectric and top electrode in the upper of the two ILD levels. Thus, the present invention provides a MIM structure and fabrication method compatible with copper interconnection technology as well as compatible resistor and alignment mark structures.
The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, reanangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims

What is claimed is:
1. An electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in said interlevel dielectric layer, a top surface of said bottom electrode co-planer with a top surface of said interlevel dielectric layer; a conductive diffusion barrier in direct contact with said top surface of said bottom electrode; a MIM dielectric in direct contact with a top surface of said conductive diffusion barrier; and a top electrode in direct contact with a top surface of said MIM dielectric.
2. The electronic device ofclaim 1, wherein said conductive diffusion banier and said MIM dielectric both extend past at least two sides of said bottom electrode.
3. The electronic device of claim 1, further including: a dielectric diffusion barrier layer formed on said top surface of said interlevel dielectric layer; and wherein said top surface of said conductive diffusion barrier is co-planer with a top surface of said dielectric diffusion banier layer.
4. The electronic device of claim 1, wherein said bottom electrode includes an upper portion comprising an additional conductive diffusion barrier, said upper portion in contact with said conductive diffusion barrier.
5. The electronic device ofclaim 4, wherein said additional conductive diffusion barrier comprises about 5 to 200 nm of a refractory metal, W, Ta, TaN, WN, TaN, TaSiN, Pt, hO2 or RuO2 or combinations thereof.
6. The electronic device of claim 1 , wherein said conductive diffusion banier comprises about 5 to 200 nm of a refractory metal, W, Ta, TaN, WN, TaN, TaSiN, Pt, IrO2 or RuO2 or combinations thereof.
7. The electronic device of claim 1 , wherein said MIM dielectric comprises about 2 to 20 nm of SiO2, Si3N4 or SiC, a high K dielectric, Ta2O5, BaTiO3, HfO2, ZrO2 or
Al2O3, or combinations of layers thereof.
8. The electronic device of claim 1, wherein said top electrode comprises Al or W.
9. An electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in said interlevel dielectric layer; a conductive diffusion banier in direct contact with a top surface of said bottom electrode, said top surface of said bottom electrode recessed below a top surface of said interlevel dielectric layer, said top surface of said conductive diffusion banier co-planer with said top surface of said interlevel dielectric layer; a MIM dielectric in direct contact with a top surface of said conductive diffusion banier; and a top electrode in direct contact with a top surface of said MIM dielectric.
10. The electronic device ofclaim 9, wherein said conductive diffusion banier and said MIM dielectric both extend past at least two sides of said bottom electrode.
11. The electronic device ofclaim 9, wherein said conductive diffusion banier comprises about 5 to 200 nm of a refractory metal, W, Ta, TaN, WN, TaN, TaSiN, Pt, IrO2 or RuO2 or combinations thereof.
12. The electronic device of claim 9, wherein said MIM dielectric comprises about 2 to 20 nm of SiO2, Si3N4 or SiC, a high K dielectric, Ta2O5, BaTiO3, HfO2, ZrO2 or Al2O3, or combinations thereof.
13. The electronic device of claim 9, wherein said top electrode comprises Al or W.
14. A method of fabricating an electronic device, comprising: (a) providing a semiconductor substrate (b) forming an interlevel dielectric layer on said semiconductor substrate; (c) forming a copper bottom electrode in said interlevel dielectric layer, a top surface of said bottom electrode co-planer with a top surface of said interlevel dielectric layer; (d) forming a conductive diffusion banier in direct contact with said top surface of said bottom electrode; (e) forming a MIM dielectric in direct contact with a top surface of said conductive diffusion barrier; and (f) forming a top electrode in direct contact with a top surface of said MIM dielectric.
15. The method of claim 14, wherein said conductive diffusion banier and said MIM dielectric both extend past at least two sides of said bottom electrode.
16. The method ofclaim 14, further including: (g) after step (c) forming a dielectric diffusion barrier layer on said top surface of said interlevel dielectric layer; and wherein said top surface of said conductive diffusion banier is co-planer with a top surface of said dielectric diffusion barrier layer.
17. The method ofclaim 14, wherein said bottom electrode includes an upper portion comprising an additional conductive diffusion banier, said upper portion in contact with said conductive diffusion barrier.
18. The method of claim 17, wherein said additional conductive diffusion barrier comprises about 5 to 200 nm of a refractory metal, W, Ta, TaN, WN, TaN, TaSiN, Pt, IrO2 or RuO2 or combinations thereof.
19. The method of claim 14, wherein said conductive diffusion barrier comprises about 5 to 200 nm of a refractory metal, W, Ta, TaN, WN, TaN, TaSiN, Pt, IrO2 or
RuO2 or combinations thereof.
20. The method of claim 1, wherein said MIM dielectric comprises about 2 to 20 nm of SiO2, Si3N or SiC, a high K dielectric, Ta2O5, BaTiO3, HfO2, ZrO2 or Al2O3, or combinations thereof.
21. The method ofclaim 14, wherein said top electrode comprises Al or W.
22. The method of claim 14, wherein step (d) further comprises simultaneously forming a resistor, an alignment mark or both a resistor and an alignment mark with said conductive diffusion banier.
23. The method of claim 22, wherein said resistor, said alignment mark or both said resistor and said alignment mark comprise about 5 to 200 nm of a refractory metal, W, Ta, TaN, WN, TaN, TaSiN, Pt, IrO2 or RuO2 or combinations of layers thereof.
24. The method of claim 14, further including (g) after step (f) depositing a reactive ion etch layer over all exposed surfaces of said conductive diffusion barrier, said MIM dielectric and said interlevel dielectric layer.
25. A method of fabricating an electronic device, comprising: (a) providing a semiconductor substrate; (b) forming an interlevel dielectric layer on said semiconductor substrate; (c) forming a copper bottom electrode in said interlevel dielectric layer; (d) forming a conductive diffusion barrier in direct contact with a top surface of said bottom electrode, said top surface of said bottom electrode recessed below a top surface of said interlevel dielectric layer, said top surface of said conductive diffusion banier co-planer with said top surface of said interlevel dielectric; (e) forming a MIM dielectric in direct contact with said top surface of said conductive diffusion banier; and (f) forming a top electrode in direct contact with a top surface of said MIM dielectric.
26. The method ofclaim 25, wherein said conductive diffusion banier and said MIM dielectric both extend past at least two sides of said bottom electrode.
27. The method of claim 25, wherein said conductive diffusion barrier comprises about 5 to 200 nm of a refractory metal, W, Ta, TaN, WN, TaN, TaSiN, Pt, IrO2 or RuO2 or combinations thereof.
28. The method of claim 25, wherein said MIM dielectric comprises about 2 to 20 nm of SiO2, Si3N4 or SiC, a high K dielectric, Ta2O5, BaTiO3, HfO2, ZrO2 or Al2O3, or combinations thereof.
29. The method of claim 25, wherein said top electrode comprises Al or W.
30. The method ofclaim 25, further including (g) after step (f) depositing a reactive ion etch layer over all exposed surfaces of said conductive diffusion barrier, said MIM dielectric and said interlevel dielectric layer.
PCT/US2004/032405 2003-09-30 2004-09-30 Metal-insulator-metal capacitor and method of fabrication WO2005034201A2 (en)

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