WO2005029740A1 - System ans method for remote controlled clock synthesis in transmission via a digital multimedia link - Google Patents

System ans method for remote controlled clock synthesis in transmission via a digital multimedia link Download PDF

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Publication number
WO2005029740A1
WO2005029740A1 PCT/EP2003/010524 EP0310524W WO2005029740A1 WO 2005029740 A1 WO2005029740 A1 WO 2005029740A1 EP 0310524 W EP0310524 W EP 0310524W WO 2005029740 A1 WO2005029740 A1 WO 2005029740A1
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WO
WIPO (PCT)
Prior art keywords
exceeded
side counter
predetermined number
clock
remote controlled
Prior art date
Application number
PCT/EP2003/010524
Other languages
French (fr)
Inventor
Michael Riedel
Roland Neumann
Original Assignee
Inova Semiconductors Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inova Semiconductors Gmbh filed Critical Inova Semiconductors Gmbh
Priority to EP03753443A priority Critical patent/EP1665596A1/en
Priority to PCT/EP2003/010524 priority patent/WO2005029740A1/en
Priority to AU2003271631A priority patent/AU2003271631A1/en
Publication of WO2005029740A1 publication Critical patent/WO2005029740A1/en
Priority to US11/386,559 priority patent/US20060164266A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]

Definitions

  • the present invention relates to a system and method for remote controlled clock synthesis in transmission via a digital multimedia link.
  • This multimedia data is processed digitally, and to complete the digital infrastructure the data should be transmitted and displayed digitally without any loss known from analog transmission and display technologies.
  • Using a serial data transmission technology to transmit data between a transmitter side and a receiver side requires that a clock at a transmitter side and a clock at a receiver side must be exactly synchronous with each other in order to avoid any disturbances of data or even loss of data.
  • a system for remote controlled clock synthesis in transmission via a digital multimedia link comprising clock coding means comprising a first transmitter side counter for counting up until a first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second transmitter side counter for counting up until a second predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded, and clock decoding means comprising a first receiver side counter for counting up until said first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second receiver side counter for counting up until said second predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded, clock synthesizer means for generating a remote controlled clock, and control means for controlling the clock synthesizer means such that the remote controlled clock has the same frequency and the same amount of transitions as a master
  • a system wherein said algorithm generates a first difference between a first time stamp presently valid and a first time stamp valid before said second time stamp presently valid and a second difference between a second time stamp presently valid and a second time stamp valid before said second time stamp presently valid and calculates a time offset presently valid by subtracting from a time offset valid before aid time offset presently valid a difference between the first and second difference.
  • a system wherein the algorithm determines that said remote controlled clock is to slow if said second difference is smaller than said first difference and that said remote controlled clock is to fast if said second difference is greater than said first difference.
  • a frequency of said remote controlled clock is increased if said remote controlled clock is to slow and said time offset presently valid has a value greater than zero.
  • a frequency of said remote controlled clock is decreased if said remote controlled clock is to fast and said time offset presently valid has a value smaller than zero.
  • a method for remote controlled clock synthesis in transmission via a digital multimedia link comprising the steps of counting up until a first predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a first transmitter side counter and counting up until a second predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a second transmitter side counter, counting up until said first predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a first receiver side counter and counting up until said second predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a second receiver side counter, generating a remote controlled clock, performing controlling such that the remote controlled clock has the same frequency and the same amount of transitions as a master clock input in said first transmitter side counter, generating time stamps such that said second transmitter side counter outputs its count value as a first time stamp if said first transmitter side counter is wrapped around and said second receiver side counter outputs its output as a second time stamp if said first receiver side counter is
  • a method wherein said algorithm generates a first difference between a first time stamp presently valid and a first time stamp valid before said second time stamp presently valid and a second difference between a second time stamp presently valid and a second time stamp valid before said second time stamp presently valid and calculates a time offset presently valid by subtracting from a time offset valid before aid time offset presently valid a difference between the first and second difference.
  • a system wherein the algorithm determines that said remote controlled clock is to slow if said second difference is smaller than said first difference and that said remote controlled clock is to fast if said second difference is greater than said first difference.
  • a frequency of said remote controlled clock is increased if said remote controlled clock is to slow and said time offset presently valid has a value greater than zero.
  • a frequency of said remote controlled clock is decreased if said remote controlled clock is to fast and said time offset presently valid has a value smaller than zero.
  • Fig. 1 is a block diagram of an overall structure of a system for remote controlled clock synthesis in transmission via a digital multimedia link;
  • Fig. 2 is a more detailed block diagram of block coding means and block decoding means shown in Fig. 1.
  • Fig. 1 is a block diagram of an overall structure of a system for remote controlled clock synthesis in transmission via a digital multimedia link.
  • reference sign 1 denotes a clock coding means
  • reference sign 2 denotes a serializer means comprising a PLL means
  • reference sign denotes a deserializer means comprising a clock recovery PLL means
  • reference sign 6 denotes a clock decoding means.
  • the serializer means 2 and the deserializer means 4 constitute a synchronous data transmission means which in the embodiment of the present invention performs serial data transmission.
  • the clock coding means 1 analyzes a master clock masterClock and generates control data which are called time stamps and which allow the block decoding means 6 to synthesis an remote controlled clock remoteControlledClock.
  • the time stamps are transmitted via the synchronous data transmission means. Generation and evaluation of the time stamps requires a synchronous time base of a transmitter side system clock sysClockTx and a receiver side system clock sysClockRx.
  • the master clock masterClock and the remote controlled clock remoteControlledClock have the same average frequency and the same amount of transitions over a certain period of time.
  • Fig. 2 is a more detailed block diagram of the block coding means 1 and block decoding means 6 shown in Fig. 1.
  • reference sign 7 denotes a first transmitter side counter also called CNT 1T and reference sign 8 denotes second transmitter side counter also called CNT 2T which are parts of the clock coding means 1
  • reference sign 10 denotes control means also called CTRL (ALGO1)
  • reference sign 11 denotes a first receiver side counter also called CNT 1R
  • reference sign 12 denotes a second receiver side counter also called CNT 2R
  • reference sign 13 denotes a clock synthesizer means which are parts of the clock decoding means 6.
  • a unique time base is formed at the transmitter side and the receiver side with the second transmitter side counter 8 and the second receiver side counter 12, respectively which are clocked with the transmitter side system clock sysClockTx and the receiver side system clock sysClockRx, respectively which are locked by a PLL and therefore synchronous to each other.
  • the transmitter side system clock sysClockTx is typically the serial data shift clock or a divided sub-clock and the receiver side system clock sysClockRx is the recovered serial data clock required for re-timing then serial data.
  • the second transmitter side counter 8 and the second receiver side counter 12 are both wrap-around counters which wrap around if a certain count value M is exceeded.
  • the values of the second transmitter side counter 8 and the second receiver side counter 12 are used to measure a certain period of time, i.e. a so- called time stamp, remoteTimeStamp and localTimeStamp.
  • the period of time is the value of the second transmitter side counter 8 and the second receiver side counter 12 which is present at the time the first transmitter side counter 7 and the first receiver side counter 11 , respectively exceed a certain count value N at which they wrap around.
  • the first transmitter side counter 7 is clocked with the master clock masterClock and the first receiver side counter 1 1 is clocked with the remote controlled clock remoteControlled clock.
  • the master clock masterClock is the clock at the transmitter side which shall be recovered (synthesized) at the receiver side.
  • the remote controlled clock remoteControlledClock is generated with the tunable clock synthesizer means 13.
  • a control algorithm ALGO1 continuously compares the remote time stamp remoteTimeStamp from the transmitter side with the locally calculated local time stamp localTimeStamp from the receiver side and controls the clock synthesizer means 13 according to the algorithm ALGO1 such that the remote controlled clock remoteControlledClock has the same frequency and the same amount of transistions as the master clock masterClock.
  • the control means 10 performs the algorithm ALGO1 such that there is defined a local delta localDelta as a relative value of a local time stamp localTimeStamp ⁇ at a time n and a local time stamp localTimeStamp n at a time n-1.
  • the local time stamps localTimeStamp n and localTimeStamp n _- ⁇ are present on the receiver side.
  • the control means 10 performs the algorithm ALGO1 such that there is defined a remote delta remoteDelta as a relative value of a remote time stamp remoteTimeStamp n at a time n and a remote time stamp remoteTimeStampn at a time n-1.
  • are present on the transmitter side.
  • the relative values are used due to the fact the second transmitter side counter 8 and the second receiver side counter 12 are wrap-around counters so that there is no defined absolute value derivable.
  • time offset time timeOffset n is the time Offset timeOffset n _ ⁇ minus the difference between the values of local delta localDelta and remote delta remoteDelta. It is determined on the receiver side whether the remote controlled clock is to slow or to fast by setting variables localToSlow and localToFast according to the condition defined in the algorithm ALGOL Finally the clock synthesizer means 13 is controlled to decrease the frequency of the remote controlled clock remoteControlledClock or to increase the frequency of the remote controlled clock remoteControlledClock if one of the two conditions in the last two lines of the algorithm ALGO 1 is fulfilled.
  • the remote controlled clock remoteControlledClock is controlled to have the same frequency and the same amount of transitions as the master clock masterClock.

Abstract

There is provided a system for remote controlled clock synthesis in transmission via a digital multimedia link, comprising clock coding means comprising a first transmitter side counter for counting up until a first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second transmitter side counter for counting up until a second predetermined number is exceeded and for wrapping around if said second predetermined number is exceeded, and clock decoding means comprising a first receiver side counter for counting up until said first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second receiver side counter for counting up until said second predetermined number is exceeded and for wrapping around if said second predetermined number is exceeded, clock synthesizer means for generating a remote controlled clock, and control means for controlling the clock synthesizer means such that the remote controlled clock has the same frequency and the same amount of transitions as a master clock input in said first transmit ter side counter, wherein time stamps are generated such that said second transmitter side counter outputs its count value as a first time stamp if said first transmitter side counter is wrapped around and said second receiver side counter outputs its output as a second time stamp if said first receiver side counter is wrapped around, and said first and second time stamps are processed via an algorithm in the control means for generating control signals to control said clock synthesizer means. Furthermore, there is provided a method which uses such system.

Description

SYSTEM AND METHOD FOR REMOTE CONTROLLED CLOCK SYNTHESIS IN TRANSMISSION VIA A DIGITAL MULTIMEDIA LINK TECHNICAL FIELD
The present invention relates to a system and method for remote controlled clock synthesis in transmission via a digital multimedia link. BACKGROUND ART
Digital satellite systems, DVD players, digital cameras and HDTV, combined with PC graphics, games and the Internet offer a huge amount of digital video and audio data. This multimedia data is processed digitally, and to complete the digital infrastructure the data should be transmitted and displayed digitally without any loss known from analog transmission and display technologies.
With the rapid drop in cost of digital flat panel monitors and displays, there is an increasing interest in the advantages of a digital long distance transmission technology for multimedia data.
Using a serial data transmission technology to transmit data between a transmitter side and a receiver side requires that a clock at a transmitter side and a clock at a receiver side must be exactly synchronous with each other in order to avoid any disturbances of data or even loss of data.
DISCLOSURE OF THE INVENTION
It is therefore an object of the present invention to provide a system and method for remote controlled clock synthesis in transmission via a digital multimedia link which is able to generate a clock at a receiver side which is exactly synchronous to a clock at a transmiter side.
As to the system this object is solved by the subject matter of claim 1 and as to the method this object is solved by the subject matter of claim 6. In more detail, according to a first aspect of the present invention there is provided a system for remote controlled clock synthesis in transmission via a digital multimedia link, comprising clock coding means comprising a first transmitter side counter for counting up until a first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second transmitter side counter for counting up until a second predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded, and clock decoding means comprising a first receiver side counter for counting up until said first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second receiver side counter for counting up until said second predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded, clock synthesizer means for generating a remote controlled clock, and control means for controlling the clock synthesizer means such that the remote controlled clock has the same frequency and the same amount of transitions as a master clock input in said first transmitter side counter, wherein time stamps are generated such that said second transmitter side counter outputs its count value as a first time stamp if said first transmitter side counter is wrapped around and said second receiver side counter outputs its output as a second time stamp if said first receiver side counter is wrapped around, and said first and second time stamps are processed via an algorithm in the control means for generating control signals to control said clock synthesizer means. According to a preferred embodiment of the present invention there is provided a system, wherein said algorithm generates a first difference between a first time stamp presently valid and a first time stamp valid before said second time stamp presently valid and a second difference between a second time stamp presently valid and a second time stamp valid before said second time stamp presently valid and calculates a time offset presently valid by subtracting from a time offset valid before aid time offset presently valid a difference between the first and second difference.
According to a further preferred embodiment of the present invention there is provided a system, wherein the algorithm determines that said remote controlled clock is to slow if said second difference is smaller than said first difference and that said remote controlled clock is to fast if said second difference is greater than said first difference.
According to a further preferred embodiment of the present invention there is provided a system, wherein a frequency of said remote controlled clock is increased if said remote controlled clock is to slow and said time offset presently valid has a value greater than zero.
According to a further preferred embodiment of the present invention there is provided a system, wherein a frequency of said remote controlled clock is decreased if said remote controlled clock is to fast and said time offset presently valid has a value smaller than zero.
According to a second aspect of the present invention there is provided a method for remote controlled clock synthesis in transmission via a digital multimedia link, comprising the steps of counting up until a first predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a first transmitter side counter and counting up until a second predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a second transmitter side counter, counting up until said first predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a first receiver side counter and counting up until said second predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a second receiver side counter, generating a remote controlled clock, performing controlling such that the remote controlled clock has the same frequency and the same amount of transitions as a master clock input in said first transmitter side counter, generating time stamps such that said second transmitter side counter outputs its count value as a first time stamp if said first transmitter side counter is wrapped around and said second receiver side counter outputs its output as a second time stamp if said first receiver side counter is wrapped around, and processing said first and second time stamps via an algorithm for generating control signals for performing controlling. According to a preferred embodiment of the present invention there is provided a method, wherein said algorithm generates a first difference between a first time stamp presently valid and a first time stamp valid before said second time stamp presently valid and a second difference between a second time stamp presently valid and a second time stamp valid before said second time stamp presently valid and calculates a time offset presently valid by subtracting from a time offset valid before aid time offset presently valid a difference between the first and second difference.
According to a further preferred embodiment of the present invention there is provided a system, wherein the algorithm determines that said remote controlled clock is to slow if said second difference is smaller than said first difference and that said remote controlled clock is to fast if said second difference is greater than said first difference.
According to a further preferred embodiment of the present invention there is provided a system, wherein a frequency of said remote controlled clock is increased if said remote controlled clock is to slow and said time offset presently valid has a value greater than zero.
According to a further preferred embodiment of the present invention there is provided a system, wherein a frequency of said remote controlled clock is decreased if said remote controlled clock is to fast and said time offset presently valid has a value smaller than zero.
BRIEF DESCRIPTION OF DRAWINGS These and other aspects of the present invention will be apparent from and elucidated with reference to the embodiments described hereinafter and considered in connection with the accompanying drawings, in which:
Fig. 1 is a block diagram of an overall structure of a system for remote controlled clock synthesis in transmission via a digital multimedia link; and
Fig. 2 is a more detailed block diagram of block coding means and block decoding means shown in Fig. 1.
BEST MODE FOR CARRYING OUT THE INVENTION First of all it should be noted that the present invention can be advantageously used in combination with a system and a method disclosed in the application "SYSTEM AND METHOD FOR FORMING A BIDIRECTIONAL
MULTIMEDIA LINK" from the assignee of the present application, simultaneously filed herewith, representative's file number IN0424.
However, the present invention is not limited to such application and, therefore, there is merely given a short abstract of the technology described in the aforementioned application in order to enhance intelligibility of the background of the present invention.
In the aforementioned application there is disclosed a reliable, high-speed, long distance, serial Gigabit/s and digital multimedia link for video data, audio data and other digital data such as sideband data which is due its serial nature highly scalable and which supports video formats ranging from VGA to UXGA panel technologys for true color support (16.7 million colors).
Multiplexing video data, audio data and sideband data about for example two independent links simplifies the interconnection technology dramatically. No skew between transmission channels needs to be controlled (de-skewing) and no data clock needs to be transmitted.
Fig. 1 is a block diagram of an overall structure of a system for remote controlled clock synthesis in transmission via a digital multimedia link.
In Fig. 1 reference sign 1 denotes a clock coding means, reference sign 2 denotes a serializer means comprising a PLL means, reference sign denotes a deserializer means comprising a clock recovery PLL means and reference sign 6 denotes a clock decoding means.
The serializer means 2 and the deserializer means 4 constitute a synchronous data transmission means which in the embodiment of the present invention performs serial data transmission. The clock coding means 1 analyzes a master clock masterClock and generates control data which are called time stamps and which allow the block decoding means 6 to synthesis an remote controlled clock remoteControlledClock. The time stamps are transmitted via the synchronous data transmission means. Generation and evaluation of the time stamps requires a synchronous time base of a transmitter side system clock sysClockTx and a receiver side system clock sysClockRx. The master clock masterClock and the remote controlled clock remoteControlledClock have the same average frequency and the same amount of transitions over a certain period of time.
Fig. 2 is a more detailed block diagram of the block coding means 1 and block decoding means 6 shown in Fig. 1.
As is obvious from Fig. 1 the serializer means 2 and the deserializer means 4 shown in Fig. 1 have been replaced by a single box denoted with reference sign 9.
Furthermore, in Fig. 2 reference sign 7 denotes a first transmitter side counter also called CNT 1T and reference sign 8 denotes second transmitter side counter also called CNT 2T which are parts of the clock coding means 1 , reference sign 10 denotes control means also called CTRL (ALGO1), reference sign 11 denotes a first receiver side counter also called CNT 1R, reference sign 12 denotes a second receiver side counter also called CNT 2R and reference sign 13 denotes a clock synthesizer means which are parts of the clock decoding means 6.
A unique time base is formed at the transmitter side and the receiver side with the second transmitter side counter 8 and the second receiver side counter 12, respectively which are clocked with the transmitter side system clock sysClockTx and the receiver side system clock sysClockRx, respectively which are locked by a PLL and therefore synchronous to each other. Within a synchronous serial data transmission means the transmitter side system clock sysClockTx is typically the serial data shift clock or a divided sub-clock and the receiver side system clock sysClockRx is the recovered serial data clock required for re-timing then serial data.
The second transmitter side counter 8 and the second receiver side counter 12 are both wrap-around counters which wrap around if a certain count value M is exceeded. The values of the second transmitter side counter 8 and the second receiver side counter 12 are used to measure a certain period of time, i.e. a so- called time stamp, remoteTimeStamp and localTimeStamp. The period of time is the value of the second transmitter side counter 8 and the second receiver side counter 12 which is present at the time the first transmitter side counter 7 and the first receiver side counter 11 , respectively exceed a certain count value N at which they wrap around. The first transmitter side counter 7 is clocked with the master clock masterClock and the first receiver side counter 1 1 is clocked with the remote controlled clock remoteControlled clock.
The master clock masterClock is the clock at the transmitter side which shall be recovered (synthesized) at the receiver side. The remote controlled clock remoteControlledClock is generated with the tunable clock synthesizer means 13. A control algorithm ALGO1 continuously compares the remote time stamp remoteTimeStamp from the transmitter side with the locally calculated local time stamp localTimeStamp from the receiver side and controls the clock synthesizer means 13 according to the algorithm ALGO1 such that the remote controlled clock remoteControlledClock has the same frequency and the same amount of transistions as the master clock masterClock.
The algorithm ALGO1 is mentioned below in detail. ALGQ1 localDelta := localTimeStampn - localTimeStampn.-| remoteDelta := remoteTimeStampn - remoteTimeStampn.-| timeOffsetn := timeOffsetn_-|- [localDelta - remoteDelta] localToSlow := "True" if remoteDelta < localDelta localToFast := "True" //remoteDelta > localDelta slower <= "1" /7(timeOffsetn > 0 and localToFast = "True") faster <= "1" if (timeOffsetn < 0 and localToSlow = "True")
The control means 10 performs the algorithm ALGO1 such that there is defined a local delta localDelta as a relative value of a local time stamp localTimeStampπ at a time n and a local time stamp localTimeStampn at a time n-1. As is obvious from Fig. 2 the local time stamps localTimeStampn and localTimeStampn_-ι are present on the receiver side. Furthermore, the control means 10 performs the algorithm ALGO1 such that there is defined a remote delta remoteDelta as a relative value of a remote time stamp remoteTimeStampn at a time n and a remote time stamp remoteTimeStampn at a time n-1. As is obvious from Fig. 2 the remote time stamps remoteTimeStampη and remoteTimeStampn_-| are present on the transmitter side.
The relative values are used due to the fact the second transmitter side counter 8 and the second receiver side counter 12 are wrap-around counters so that there is no defined absolute value derivable.
Thereafter, there is defined that the time offset time timeOffsetn is the time Offset timeOffsetn_ι minus the difference between the values of local delta localDelta and remote delta remoteDelta. It is determined on the receiver side whether the remote controlled clock is to slow or to fast by setting variables localToSlow and localToFast according to the condition defined in the algorithm ALGOL Finally the clock synthesizer means 13 is controlled to decrease the frequency of the remote controlled clock remoteControlledClock or to increase the frequency of the remote controlled clock remoteControlledClock if one of the two conditions in the last two lines of the algorithm ALGO 1 is fulfilled.
Consequently, the remote controlled clock remoteControlledClock is controlled to have the same frequency and the same amount of transitions as the master clock masterClock.
Although the present invention has been described by way of a specific embodiment of the present invention it is not intended to delimit the present invention the specific embodiment described above. Rather, the present invention is intended to include all modifications and amendments which fall within the scope of the present invention as defined in the appended claims.

Claims

Claims
1. System for remote controlled clock synthesis in transmission via a digital multimedia link, comprising: clock coding means comprising a first transmitter side counter for counting up until a first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second transmitter side counter for counting up until a second predetermined number is exceeded and for wrapping around if said second predetermined number is exceeded; and clock decoding means comprising a first receiver side counter for counting up until said first predetermined number is exceeded and for wrapping around if said first predetermined number is exceeded and a second receiver side counter for counting up until said second predetermined number is exceeded and for wrapping around if said second predetermined number is exceeded, clock synthesizer means for generating a remote controlled clock, and control means for controlling the clock synthesizer means such that the remote controlled clock has the same frequency and the same amount of transitions as a master clock input in said first transmitter side counter, wherein: time stamps are generated such that said second transmitter side counter outputs its count value as a first time stamp if said first transmitter side counter is wrapped around and said second receiver side counter outputs its output as a second time stamp if said first receiver side counter is wrapped around, and said first and second time stamps are processed via an algorithm in the control means for generating control signals to control said clock synthesizer means.
2. System according to claim 1 , wherein said algorithm generates a first difference between a first time stamp presently valid and a first time stamp valid before said first time stamp presently valid and a second difference between a second time stamp presently valid and a second time stamp valid before said second time stamp presently valid and calculates a time offset presently valid by subtracting from a time offset valid before aid time offset presently valid a difference between the first and second difference.
3. System according to claim 2, wherein the algorithm determines that said remote controlled clock is to slow if said second difference is smaller than said first difference and that said remote controlled clock is to fast if said second difference is greater than said first difference.
4. System according to claim 3, wherein a frequency of said remote controlled clock is increased if said remote controlled clock is to slow and said time offset presently valid has a value smaller than zero.
5. System according to claim 3 or 4, wherein a frequency of said remote controlled clock is decreased if said remote controlled clock is to fast and said time offset presently valid has a value greater than zero.
6. Method for remote controlled clock synthesis in transmission via a digital multimedia link, comprising the steps of: counting up until a first predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a first transmitter side counter and counting up until a second predetermined number is exceeded and wrapping around if said second predetermined number is exceeded by a second transmitter side counter, counting up until said first predetermined number is exceeded and wrapping around if said first predetermined number is exceeded by a first receiver side counter and counting up until said second predetermined number is exceeded and wrapping around if said second predetermined number is exceeded by a second receiver side counter, generating a remote controlled clock, performing controlling such that the remote controlled clock has the same frequency and the same amount of transitions as a master clock input in said first transmitter side counter, generating time stamps such that said second transmitter side counter outputs its count value as a first time stamp if said first transmitter side counter is wrapped around and said second receiver side counter outputs its output as a second time stamp if said first receiver side counter is wrapped around, and processing said first and second time stamps via an algorithm for generating control signals for performing controlling.
7. Method according to claim 6, wherein said algorithm generates a first difference between a first time stamp presently valid and a first time stamp valid before said first time stamp presently valid and a second difference between a second time stamp presently valid and a second time stamp valid before said second time stamp presently valid and calculates a time offset presently valid by subtracting from a time offset valid before aid time offset presently valid a difference between the first and second difference.
8. Method according to claim 7, wherein the algorithm determines that said remote controlled clock is to slow if said second difference is smaller than said first difference and that said remote controlled clock is to fast if said second difference is greater than said first difference.
9. Method according to claim 8, wherein a frequency of said remote controlled clock is increased if said remote controlled clock is to slow and said time offset presently valid has a value smaller than zero.
10. Method according to claim 8 or 9, wherein a frequency of said remote controlled clock is decreased if said remote controlled clock is to fast and said time offset presently valid has a value greater than zero.
PCT/EP2003/010524 2003-09-22 2003-09-22 System ans method for remote controlled clock synthesis in transmission via a digital multimedia link WO2005029740A1 (en)

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EP03753443A EP1665596A1 (en) 2003-09-22 2003-09-22 System ans method for remote controlled clock synthesis in transmission via a digital multimedia link
PCT/EP2003/010524 WO2005029740A1 (en) 2003-09-22 2003-09-22 System ans method for remote controlled clock synthesis in transmission via a digital multimedia link
AU2003271631A AU2003271631A1 (en) 2003-09-22 2003-09-22 System ans method for remote controlled clock synthesis in transmission via a digital multimedia link
US11/386,559 US20060164266A1 (en) 2003-09-22 2006-03-22 Synthesizing a remote controlled clock for data transmission via a digital multimedia link

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