AU2003271631A1 - System ans method for remote controlled clock synthesis in transmission via a digital multimedia link - Google Patents

System ans method for remote controlled clock synthesis in transmission via a digital multimedia link

Info

Publication number
AU2003271631A1
AU2003271631A1 AU2003271631A AU2003271631A AU2003271631A1 AU 2003271631 A1 AU2003271631 A1 AU 2003271631A1 AU 2003271631 A AU2003271631 A AU 2003271631A AU 2003271631 A AU2003271631 A AU 2003271631A AU 2003271631 A1 AU2003271631 A1 AU 2003271631A1
Authority
AU
Australia
Prior art keywords
transmission via
digital multimedia
remote controlled
controlled clock
clock synthesis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003271631A
Inventor
Roland Neumann
Michael Riedel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inova Semiconductors GmbH
Original Assignee
Inova Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inova Semiconductors GmbH filed Critical Inova Semiconductors GmbH
Publication of AU2003271631A1 publication Critical patent/AU2003271631A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Selective Calling Equipment (AREA)
AU2003271631A 2003-09-22 2003-09-22 System ans method for remote controlled clock synthesis in transmission via a digital multimedia link Abandoned AU2003271631A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2003/010524 WO2005029740A1 (en) 2003-09-22 2003-09-22 System ans method for remote controlled clock synthesis in transmission via a digital multimedia link

Publications (1)

Publication Number Publication Date
AU2003271631A1 true AU2003271631A1 (en) 2005-04-11

Family

ID=34354392

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003271631A Abandoned AU2003271631A1 (en) 2003-09-22 2003-09-22 System ans method for remote controlled clock synthesis in transmission via a digital multimedia link

Country Status (3)

Country Link
EP (1) EP1665596A1 (en)
AU (1) AU2003271631A1 (en)
WO (1) WO2005029740A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1665809B1 (en) 2003-09-22 2007-11-14 INOVA Semiconductors GmbH System and method for forming a bidirectional multimedia link

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260978A (en) * 1992-10-30 1993-11-09 Bell Communications Research, Inc. Synchronous residual time stamp for timing recovery in a broadband network
GB2285201B (en) * 1993-12-22 1997-12-10 Roke Manor Research Timing recovery apparatus
US6144714A (en) * 1998-01-06 2000-11-07 Maker Communications, Inc. Programmable fractional frequency digital frequency synthesizer for synchronous residual time stamp service clock regenerator phase locked loop
US20010055354A1 (en) * 2000-03-03 2001-12-27 Danny Fung Method & apparatus for data rate synchronization
US7106758B2 (en) * 2001-08-03 2006-09-12 Adc Telecommunications, Inc. Circuit and method for service clock recovery

Also Published As

Publication number Publication date
EP1665596A1 (en) 2006-06-07
WO2005029740A1 (en) 2005-03-31

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase