WO2005020650A2 - Carte de circuit - Google Patents

Carte de circuit Download PDF

Info

Publication number
WO2005020650A2
WO2005020650A2 PCT/AT2004/000271 AT2004000271W WO2005020650A2 WO 2005020650 A2 WO2005020650 A2 WO 2005020650A2 AT 2004000271 W AT2004000271 W AT 2004000271W WO 2005020650 A2 WO2005020650 A2 WO 2005020650A2
Authority
WO
WIPO (PCT)
Prior art keywords
circuit board
printed circuit
loss layers
loss
layers
Prior art date
Application number
PCT/AT2004/000271
Other languages
German (de)
English (en)
Other versions
WO2005020650A3 (fr
Inventor
Dietrich Juran
Gerald Eckl
Original Assignee
Siemens Ag Österreich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag Österreich filed Critical Siemens Ag Österreich
Publication of WO2005020650A2 publication Critical patent/WO2005020650A2/fr
Publication of WO2005020650A3 publication Critical patent/WO2005020650A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0233—Filters, inductors or a magnetic substance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core

Definitions

  • the invention relates to a printed circuit board, consisting of an insulating carrier material and of conductive structures on the free surfaces and / or in the interior of the carrier material.
  • the problem on which the invention is based is electromagnetic interference emissions which originate from electronic assemblies or which have been interspersed in such assemblies, with assemblies being considered here which use printed circuit boards as circuit carriers.
  • An object of the invention is to provide a printed circuit board with which the problems mentioned can be effectively countered.
  • the loss layers can have dielectric losses and / or hysteresis and / or eddy current losses.
  • the loss layers consist of a ferrite polymer which, in the sense of the invention, has particularly good dissipative properties.
  • the loss layers are advantageously arranged in the area of • conductor structures which, when the printed circuit board is used in an electrical device, have potential courses that trigger disturbances.
  • FIGS. 2 and 3 show a section through a section of a printed circuit board, along the line I - 1 in FIGS. 2 and
  • FIG. 2 shows a plan view of the circuit board section according to FIG. 1.
  • Fig. 1 and Fig. 2 represent in a schematic, simplified and not to scale a circuit board 1, which consists of a suitable insulating material, which is available to the person skilled in the art depending on the requirements for dielectric strength, thermal properties, etc.
  • the circuit board has conductive structures in the usual way, generally conductor tracks, which are designated here with the reference numbers 3a to 3h. These structures consist, for example and in a known manner, of copper, a through-contact 3d also being drawn here, which interconnects interconnects on the surfaces of the printed circuit board or in its interior.
  • the circuit board also has structured loss layers 4a to 4c, in the present case a strip 4a of such a loss layer on the upper surface of the circuit board, a strip 4c on the inside.
  • the printed circuit board below a conductor track 3g or above a conductor track 3h and an annular loss layer 4b which bypasses the through-hole 3d.
  • the loss layers can consist of a ferrite polymer with a high power loss density, such materials being known to the person skilled in the art under the name FPC (ferrite polymer composite). Ferrite particles are embedded in a polymer matrix and, depending on the fill factor, permeabilities in the size of 10 to 30 are initially obtained. The material is also commercially available in foils with thicknesses of 0.2 to 0.4 mm.
  • the loss layers dampen both in an active and in a passive way. If, for example, a strongly jumping potential occurs at the via 3d, the ring-shaped loss layer 4b dampens this via and the interference radiation is reduced.
  • the energy from interference source ⁇ can be continuously reduced with the help of the loss layers with increasing spatial distance up to, for example, connected system interfaces, without additional discrete components, such as filters, being necessary.
  • the damping properties of the printed circuit board with its loss layers absorb passive interference in the system and thus the effects of the interference spectrum on the circuitry applied to the circuit board are greatly reduced.
  • FIGS. 1 and 2 are purely schematic, and is only intended to show a few possibilities for introducing or applying loss layers.
  • a circuit board will still be equipped with components and the arrangement of the loss layers will be optimized, which is possible, for example, by calculating field strengths, etc. using suitable programs available to the person skilled in the art.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

L'invention concerne une carte de circuit /1) comprenant un matériau support isolant (2) et des structures conductrices (3a, , 3h) au niveau des surfaces libres et/ou à l'intérieur du matériau support, sur lequel et/ou dans lequel des couches de dissipation structurées (4a, , 4c) à base de matériau sujet aux déperditions sont appliquées/introduites.
PCT/AT2004/000271 2003-08-20 2004-07-26 Carte de circuit WO2005020650A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ATA1311/2003 2003-08-20
AT13112003 2003-08-20

Publications (2)

Publication Number Publication Date
WO2005020650A2 true WO2005020650A2 (fr) 2005-03-03
WO2005020650A3 WO2005020650A3 (fr) 2005-06-09

Family

ID=34200459

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AT2004/000271 WO2005020650A2 (fr) 2003-08-20 2004-07-26 Carte de circuit

Country Status (1)

Country Link
WO (1) WO2005020650A2 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5966294A (en) * 1996-12-20 1999-10-12 Nec Corporation Printed circuit board for prevention of unintentional electromagnetic interference
US20030062965A1 (en) * 2001-09-27 2003-04-03 Stephen Jensen Circuit board having ferrite containing layer
US20040018658A1 (en) * 2002-07-27 2004-01-29 Yasuhiko Mano Noise shield type multi-layered substrate and munufacturing method thereof
US20040121652A1 (en) * 2002-12-20 2004-06-24 Gailus Mark W. Interconnection system with improved high frequency performance

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5966294A (en) * 1996-12-20 1999-10-12 Nec Corporation Printed circuit board for prevention of unintentional electromagnetic interference
US20030062965A1 (en) * 2001-09-27 2003-04-03 Stephen Jensen Circuit board having ferrite containing layer
US20040018658A1 (en) * 2002-07-27 2004-01-29 Yasuhiko Mano Noise shield type multi-layered substrate and munufacturing method thereof
US20040121652A1 (en) * 2002-12-20 2004-06-24 Gailus Mark W. Interconnection system with improved high frequency performance

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"ELECTROMAGNETIC NOISE SUPPRESSION FOR ELECTRONICS CARDS AND BOARDS" IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, Bd. 33, Nr. 7, 1. Dezember 1990 (1990-12-01), Seiten 243-246, XP000108425 ISSN: 0018-8689 *
WAFFENSCHMIDT E ET AL: "Embedded passives integrated circuits for power converters" 33RD.ANNUAL IEEE POWER ELECTRONICS SPECIALISTS CONFERENCE. PESC 2002. CONFERENCE PROCEEDINGS. CAIRNS, QUEENSLAND, AUSTRALIA, JUNE 23 - 27, 2002, ANNUAL POWER ELECTRONICS SPECIALISTS CONFERENCE, NEW YORK, NY : IEEE, US, Bd. VOL. 2 OF 4. CONF. 33, 23. Juni 2002 (2002-06-23), Seiten 12-17, XP010596058 ISBN: 0-7803-7262-X *

Also Published As

Publication number Publication date
WO2005020650A3 (fr) 2005-06-09

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