WO2005017998A2

WO2005017998A2 - Bipolar transistor with a heterojunction with improved thermal transfer

Info

Publication number: WO2005017998A2
Application number: PCT/EP2004/051478
Authority: WO
Inventors: Jean-Claude Jacquet; Raphaël Aubry; Sylvain Delage; Nicole Caillas
Original assignee: Thales
Priority date: 2003-07-15
Filing date: 2004-07-13
Publication date: 2005-02-24
Also published as: FR2857781A1; WO2005017998A3; FR2857781B1

Abstract

The invention relates to an electronic component with a heat sink, comprising one or several bipolar transistors on the active face of the substrate, each transistor embodied in a stack of semiconductor layers in the form of mesas, with at least one collector mesa. A diamond layer covers the form of the stack, which favours a thermal transfer via the flanks of the collector mesa towards the diamond layer and the heat sink is arranged on the diamond layer.

Description

BIPOLAR HETEROJUNCTION TRANSISTOR WITH IMPROVED THERMAL TRANSFER

The present invention relates to a structure of a bipolar transistor with a vertical structure, in particular hetero-junction transistors, in which the heat transfer is improved. Bipolar hetero-junction transistors or HBT transistors for Heterojunction Bipolar Transistor are of great interest in microwave applications. These transistors result from a vertical technology, which consists of a stack of semiconductor layers in the form of a mesa, in which the current flows perpendicular to the surface plane of the substrate, through the emitter, the base and the collector. . The current densities that these transistors can control are very high, for example they can reach 2.10 ⁵ A.cm ^"2. Depending on whether the layers are made from the same semiconductor material or not, we speak of bipolar homo transistors -junction or hetero-junctions. In the latter, we exploit in particular the differences in gap between the materials, which make it possible to improve the power performance of these transistors. These bipolar transistors in vertical technology pose significant problems of heat dissipation Indeed, the collector, which is the seat of a very high electric field, undergoes a strong heating. The heat which is released is all the more difficult to evacuate that the structure is vertical and that the semiconductor materials used , generally materials of group III-V, are very poor thermal conductors. To ensure the proper functioning of the transistors, and above all obtain ir good operational performance, with a significant improvement in the power available per unit of semiconductor surface for a given operating temperature, a heat sink is generally integrated on the active face, to dissipate the heat through the active face. Such a heat sink is described in patent EP0756322. It is a metallic heat sink, with an aerial part in the form of a bridge (air bridge), which is supported in particular on the upper mesas of the transistors. It is made of thick metal, of the order of 10 microns, in a metal that is a good thermal conductor, typically gold or copper. according to The teaching of this patent, this heat sink is obtained by spraying a thin layer of metal over a layer of resin previously deposited on the stack. This thin layer of metal then serves as an electrode for achieving growth of this metal, in order to obtain a determined thickness. The resin is then removed by any known means. This gives a transistor structure schematically represented in transverse view in FIG. 1. This figure corresponds to a semiconductor component structure which comprises several bipolar transistors in parallel on a substrate s, which is generally the case in all power applications. Two transistors of this structure are shown in the figure. Each transistor is produced from the substrate s in a stack 1 of semiconductor layers in the form of mesas. More particularly, the stack comprises in the example, starting from the substrate s, a sub-collector buried in the substrate, a first mesa which constitutes the collector C, a base layer B, and a second mesa which is the upper mesa of the stack and which constitutes the emitter E. On either side of the collector mesa, metallizations m _G are made allowing contact to be made at the collector. On either side of the emitter mesa, metallizations of base m are carried out. The emitter mesa E is covered with a metalization m _e . The whole is protected by a passivation layer P. A metal bridge PI covers the structure. Legs 5 of the bridge rest on the passivation layer at the base and emitter metallizations. The passivation layer can be opened on the emitter metalization, bringing it into electrical contact with the bridge. FIG. 1b shows a top view of this structure, which highlights the base bus bB and the collector bus bC which allow the contacts to be made laterally at the bases and the collectors of the transistors in parallel. The points cEi and cE ₂ represent electrical contacts taken from the emitters of the transistors. The heat sink PI thus formed can be connected with a ground plane arranged on the rear face of the substrate by a metalization hole made in a region not covering the transistors (not shown). The metal used to make this heat sink is gold or copper, or any other metal with good thermal properties (low thermal resistance). Reference will usefully be made to the aforementioned patent for the details of construction. In this structure, heat transfer from the heat source, located in the collector at the base collector junction, takes place essentially through the substrate, towards the rear face of the component and via the base B and the emitter E, and their metallizations, to the PI heat sink. In the invention, it has been sought to improve this structure in terms of thermal efficiency. In the invention, a structure of a semiconductor component with integrated heat sink has been sought by which the microwave performance of the component is improved. In the invention, the shortest and most efficient path possible has been sought in terms of thermal resistance between the heat source, located at the heart of each transistor and the heat sink. An idea underlying the invention is the use of a layer of electrical insulating material and good thermal conductor, to cover the shape of the stack, so that the heat transfer can take place laterally via the sides of the collector, seat of the heat source, towards this layer of material, the heat sink being disposed on this layer. Thanks to this structure, the heat emitted by the heat source at the heart of the transistor can diffuse laterally towards this layer of material, through the sides of the collector mesa, the layer acting as a heat sink towards the dissipator. Thus, as claimed, the invention relates to an electronic component with heat sink, comprising on the active face of a substrate, one or more bipolar transistors, each transistor being produced in a stack of semiconductor layers in the form of mesas, with at least one collector mesa. According to the invention, a layer of heat sink in an electrically insulating and thermally conductive material covers the shape of the stack, favoring a heat transfer via the sides of the collector mesa to the heat drain layer. In addition, the structure of the assembly, component and integrated heat sink is mechanically stiffened. It then lends itself advantageously to a transfer upside down on a plate such as a polycrystalline diamond plate or AIN, improving the thermal performance of this component. Preferably, the layer of electrically insulating and thermally conductive material is a layer of diamond, polycrystalline and / or of DLC type. In addition, by providing a sufficient layer thickness, of the order of one to a few microns, this layer of material, which is a dielectric, advantageously makes it possible to increase the value of the capacities which determine the microwave performance of HBT transistors, typically the parasitic base-emitter capacitances, in the case of a top emitter transistor structure, or parasitic collector-base capacitance in the case of a top collector bipolar transistor structure. According to another aspect of the invention, for a bipolar hetero junction transistor with emitter at the top, the collector mesa is etched. In this way the layer of material on the sides of this mesa are as close as possible to the very source of the heat, improving the efficiency of the heat transfer device. According to one embodiment of the invention, the heat sink preferably comprises a form of metal bridge resting on the upper mesas. Alternatively, it is in electrical contact with the metalization of the upper emitter or collector mesas.

Other advantages and characteristics of the invention will appear more clearly on reading the description which follows, given by way of nonlimiting illustration of the invention and with reference to the appended drawings, in which: - Figures 1a and 1b already described represent a bipolar transistor component structure with vertical structure, with an integrated heat sink according to the state of the art; - Figures 2a and 2b show in cross section alternative embodiments of a component structure with bipolar transistors with emitter at the top, according to the invention; - Figures 3a and 3b show in cross section alternative embodiments of a bipolar transistor component structure of the top collector type according to the invention.

FIG. 2a comprises, in addition to all the elements represented in FIG. 1a, and which bear the same references, a layer 100 of an electrically insulating material having good thermal conductivity, at least greater than 100 W / ° Cm (watts per degree celsius.meter), which covers the shape of the stack. One can also choose as electrically insulating material having good thermal conductivity, a material among AIN, A ^ Ox ^ SiC, or a compound AlχGaι _-x N. Preferably, it is a layer of diamond 100. This layer of diamond is a material which has an excellent thermal conductivity, higher than 100 W / ° Cm A layer of diamond of type "DLC", according to the acronym for "Diamond like Carbon" also offers good performances. It was thus possible to obtain conductivities of the order of 300 W / ° Cm with DLC. This layer 100 is obtained for example by vacuum deposition techniques, at low temperature, typically below 300 ° C. It can be deposited over stack 1 in the form of mesas. This layer 100 follows the complex shapes of the structure. This layer 100 can then be etched locally, to allow contact resumption. In the example shown, the layer 100 and the passivation layer P are etched to release the metalization of the emitter m _θ , allowing electrical contact between the metal bridge PI and the emitter E. As shown in FIG. 2a, this layer 100 which envelops the stack makes it possible to provide lateral paths of thermal diffusion, from the heat source S " _ι located at the heart of the transistor, in the collector, at the base-collector junction, towards layer 100. In particular, the heat will diffuse via the sides 2 _a , 2 _b of the collector mesa. This diffusion path improves the efficiency of the heat transfer, since it crosses only the material of the collector mesa, laterally and vertically, to end up in the material of the layer 100 which has a very low thermal resistance. FIG. 3a represents a similar structure according to the invention, applied to a bipolar transistor with collector at the top. We find the lateral diffusion channels via the sides 2 _a , 2 _b of the collector mesa. The thickness of the layer 100 is a function of the height of the stack 1 to be covered. If the material of layer 100 is polycrystalline diamond, the thickness of this layer can be less than 1 micron. Such a thickness is sufficient in terms of its thermal properties taking into account the very good thermal conductivity of this material, and makes it possible not to be penalized by the deposition rate of this material which, at temperatures below 300 ° C., with the disadvantage of being very slow, of the order of 0.1 micrometer / hour. If we want to benefit from a diamond layer which offers good flatness, in particular to be used as a passivation layer, we can then plan to deposit over the polycrystalline diamond DLC type diamond which will not have this drawback, for complete the thickness to 1 micron or a few microns. In this variant, the layer 100 is then a mixed polycrystalline diamond / DLC diamond layer. If the material of layer 100 is DLC type diamond, its thickness is of the order of 1 to a few microns. According to the invention, this thickness is also determined so as to have a parasitic capacity between the base metalization and the metalization of the upper mesa as small as possible. In the example of a bipolar transistor with emitter at the top as shown in FIGS. 2a and 2b, it is the stray base-emitter _capacitance C _P ( _bθ ) - This stray capacitance has a value inversely proportional to the thickness of dielectric e1 between the base and emitter metalization. The higher e1, the lower the stray capacitance, and the better the microwave behavior of the transistor. Compared to the structure of the state of the art represented in the FIG. 1a, the parasitic capacitance is reduced as a first approximation, in a ratio close to the ratio between the thickness e1 of the part of the layer 100 between the base and the upper mesa and the thickness of the passivation layer P. This s applies equally well to the stray base-collector capacitance in the bipolar transistor with top collector shown in FIGS. 3a and 3b. According to the invention, the thickness of the layer 100 is of the order of 1 to a few microns. For example, it is of the order of three microns. In Figure 2a, there are shown two possible embodiments of the invention. On the left, this is the embodiment described above. On the right, an improvement is shown. Of course, in practice, the component is produced either in its entirety according to the variant shown on the left part of the figure or in its entirety according to the right option. This improvement represented on the right-hand side consists in etching the sides 2 _a , 2 _b of the collector mesa, so as to make it thinner: the layer 100 is thus brought closer to the heat source, which makes the structure more efficient, with the shortest possible lateral thermal path up to the material of layer 100. In the case of a structure according to the invention where the upper mesa is the collector mesa, as shown in FIG. 3a, the upper mesa having already optimal dimensions, defined by the technology considered, the lateral thermal path via the sides of the collector is optimal.

In FIGS. 2a and 3a, the mesa-shaped stack is first of all passive: a thin passivation layer P is deposited on the active face of the substrate and the stack. In a variant shown in FIGS. 2b and 3b, the layer 100 ensures the passivation of the structure, eliminating the specific passivation layer P. The manufacturing process is simplified. Preferably, and as shown in FIGS. 2a, 2b, 3a, 3b, a bonding layer 3 _a of the layer 100 is provided on the active surface of the stack (FIGS. 2b, 3b) or, where appropriate, on the passivation layer P (Figures 2a, 3a). For a diamond layer 100, this bonding layer will typically be made of a material chosen from W, Mo, WC, SiC, III-N, SiN compounds allowing the formation of an alloy with carbon. A method of manufacturing a semiconductor device structure according to the invention uses a low temperature deposition of the layer of material 100, for example a CVD deposition, or any other known method. The deposition temperature is typically less than 300 ° C., which is compatible with most semiconductor materials, in particular III-V materials, as well as with Shottky contacts and ohmic contacts. The step of depositing this layer is carried out after the stack of semiconductor layers in the form of mesas has been formed. The layer 100 thus deposited covers the surface of the stack and the sides of the mesas. This deposition step is preferably deposited after the metallizations of emitter m _e , collector m ₀ and base m have been completed and covers these metallizations. The layer 100 is preferably used as the passivation layer of the active face, as shown in FIGS. 2b and 3b. The structure then does not have a specific passivation layer P.

According to an embodiment of the invention for a bipolar transistor with emitter at the top, according to which the flanks 2 _a , 2 _b of the collector mesa are etched, as represented on the right part of FIG. 2a, the manufacturing process comprises the following steps: -realization of a stack of semiconductor layers in the form of mesas, with a collector mesa, a base layer on the collector mesa, and an upper emitter mesa; -engraving of the sides of the collector mesa under the base. The flanks of the collector mesa are etched by any known method, for example by chemical etching. In the example, this etching goes to the surface 7 of collector / sub-collector junction (or emitter / sub-emitter), but it can stop earlier, as soon as the source area has been reached. of heat Sth. The dimensions of the collector mesa are then reduced. In an alternative embodiment, provision is made for carrying out the basic metallizations after etching of the sides of the collector, but before the deposition of the layer 100. Preferably, a first step of deposition of the layer 100 is provided, after the step of etching of the manifold sides, to stiffen the structure; then the realization of these metallizations. A second step of depositing the layer 100 is then carried out, in order to obtain the determined layer thickness. Thus, the process for manufacturing a semiconductor device is little disturbed by the additional steps planned to implement the invention. These steps are integrated at the end of the process, and can replace certain steps, in particular, in the case where the layer 100 also serves as passivation. The semiconductor device according to the invention incorporates a heat sink 4 on the active face, disposed on the layer 100. The thick layer 100 thus acts as a heat sink, draining the heat towards the sink, with a large surface for exchanging heat, since it rests on the layer 100. a primer layer 3 _b may be provided between the layer 100 and the heat sink 4. We have seen that for a 100 diamond layer, the primer layer is made of a material chosen from W, Mo, C, SiC, III-N, SiN compounds, which makes it possible to produce an alloy with carbon. In a preferred embodiment, and as shown in FIGS. 2a, 2b, 3a, 3c, this heat sink 4 is formed from a thick layer of a metal which is a good thermal conductor, such as gold or copper. It is typically obtained by electrolysis, with a spray deposition of a thin layer 4a of this metal which then serves as an electrode for obtaining the layer 4b by electrolytic growth (FIG. 2a, 2b). In the end, the metal layer 4 (4a + 4b) has the required thickness, of the order of 10 microns. In one embodiment, this layer has the shape of a bridge, with legs 5 resting on the upper mesas, promoting the heat transfer at this location from the upper mesa to the heat sink. There may be openings in the passivation layer P and / or the layer 100 for releasing the metallizations from the upper mesa, for electrically bringing the metallic layer 4 forming the bridge into contact with these metallizations. This variant is represented in FIG. 2a, for the metalization of emitter m _θ of the bipolar transistor with emitter at the top. It applies equally well to the metallization of collector m _c of a bipolar transistor with top collector (not shown). In addition to the thermal contact, there is then an electrical contact. Layer 4 then forms the emitter bus, in the case of a top emitter transistor, or the collector bus, in the case of a top emitter transistor. In this structure, the bridge is not aerial: it rests on the layer

100, offering a large heat exchange surface, and great mechanical rigidity. The mechanically stiffened structure is favorable for brazing the component upside down (flip-chip mounting) on a plate 6 made of a material which is a good thermal conductor, such as AIN, of copper, or preferably, of polycrystalline diamond, for its excellent thermal conductivity. . The heat sink then has a composite structure, formed by the metal bridge PI and the plate. The thermal efficiency of dissipation is greatly improved. The process is also simplified because the metal layer 4 of the heat sink no longer needs to be as thick (of the order of 10 microns). It is then possible to deposit a thin layer of metal, without using an electrolytic growth process. The plate 6 made of a material which is a good thermal conductor can be in the form of blocks, each block being soldered individually on a transistor of the semiconductor component. A semiconductor component according to the invention thus sees its thermal and microwave performance improved. The process steps relating to the invention are easily integrated into the process. They are compatible with most semi-conductor materials, the deposition temperature of the diamond layer being less than 300 ° C. The layer 100 which envelops the stack offers particularly efficient lateral and active side heat transfer channels. A semiconductor component is thus obtained with good thermal performance, at low cost. Microwave performance is also improved. The invention applies very particularly to components with hetero-junction bipolar transistors, very particularly used in power applications, in particular in microwave applications.

Claims

1. Electronic component with heat sink (4), comprising, on the active face of a substrate, one or more bipolar transistors, each transistor being produced in a stack of semiconductor layers in the form of mesas, with at least one collector mesa (C), characterized in that it comprises a thermal drain layer (100) in an electrically insulating and thermally conductive material, disposed between the heat sink and the shape of the stack which it covers, promoting thermal transfer via the sides (2a, 2b) of the collector mesa towards said layer (100).

2. Component according to claim 1, characterized in that the material of said heat sink layer (100) is chosen from AIN, AI ₂ O ₃ , SiC, Al _x Gaι _-x N.

3. Component according to claim 1, characterized in that the material of said heat sink layer (100) is a diamond layer.

4. Component according to claim 3, characterized in that said diamond layer comprises DLC diamond.

5. Component according to claim 3 or 4, characterized in that said diamond layer comprises polycrystalline diamond.

6. Component according to any one of claims 1 to 5, comprising an upper emitter mesa, characterized in that the flanks (2a, 2b) of the collector mesa (C) are etched.

7. Component according to any one of claims 1 to 6, characterized in that said heat drain layer (100) is a passivation layer of the component.

8. Component according to any one of claims 1 to 6, characterized in that it comprises a passivation layer (P), said heat drain layer (100) being deposited on top.

9. Component according to any one of the preceding claims, characterized in that it comprises a bonding layer (3a) between said heat drain layer (100) and the structure located below.

10. Component according to any one of claims 1 to 9, characterized in that it comprises a bonding layer (3b) between said thermal drain layer (100) and the heat sink (4).

11. Component according to claim 9 or 10, in combination with one of claims 2, 3 or 4, characterized in that the bonding layer (3a, 3b) is made of a material chosen from W, Mo, WC , SiC, compounds III-N, SiN.

12. Component according to any one of claims 1 to 11, characterized in that the heat sink comprises a metal layer (4).

13. Component according to claim 12, the upper mesa (E) of the stack being coated with a metalization (m _e ), characterized in that said metal layer is in electrical contact (5) with said metalization (m _e ) .

14. Component according to any one of claims 1 to 13, characterized in that the heat sink comprises a plate (6) of a material which is a good thermal conductor.

15. Component according to the preceding claim, characterized in that said plate is made of polycrystalline diamond.

16. Component according to claim 14 or 15, characterized in that said plate (6) is brazed on the metal layer (4).

17. Component according to any one of the preceding claims with heterojunction bipolar transistors.

18. A method of manufacturing a semiconductor component with a heat sink (4), comprising one or more bipolar transistors, each transistor being produced from a substrate by a stack of semiconductor layers in the form of mesas, at less a collector mesa (C), characterized in that it comprises a step of depositing a heat drain layer (100) in an electrically insulating and thermally conductive material on the shape of the stack which it covers, the heat sink being disposed over the heat sink layer.

19. The manufacturing method according to claim 18, characterized in that said heat drain layer (100) is deposited after the metallization of emitter (m _θ ), collector (m _c ) and base (m _b ) bipolar transistors.

20. The manufacturing method according to claim 19, characterized in that the heat drain layer (100) is used as the passivation layer of the component.

21. The manufacturing method according to claim 18, characterized in that it comprises the following steps: -realization from a substrate of a stack of semiconductor layers in the form of mesas, with an upper emitter mesa (E) resting on a base layer (B), and a collector mesa below; -engraving of the sides of the collector mesa (C) under the base (B).

22. The manufacturing method according to the preceding claim, characterized in that it comprises a first step of depositing the heat drain layer (100) after etching the collector sides, to stiffen the structure.

23. The manufacturing method according to the preceding claim, characterized in that the step of producing the base metallizations occurs after the deposition of the heat drain layer (100).

24. The method of claim 22 or 23, characterized in that it comprises a second step of depositing the heat drain layer (100).

25. Method according to any one of claims 18 to 24, characterized in that the material of said thermal drain layer (100) is chosen from AIN, AI ₂ O ₃ , SiC, Al _x Ga- |. _x N.

26. Method according to any one of claims 18 to 24, characterized in that the material of said heat sink layer (100) is a diamond layer.

27. The method of claim 26, characterized in that said diamond layer comprises DLC diamond.

28. The method of claim 26 or 27, characterized in that said diamond layer comprises polycrystalline diamond.