WO2005013129A1 - Information processing device, instruction processing control device, instruction processing control method, instruction processing control program, and computer readable recording medium containing the instruction processing control program - Google Patents

Information processing device, instruction processing control device, instruction processing control method, instruction processing control program, and computer readable recording medium containing the instruction processing control program Download PDF

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Publication number
WO2005013129A1
WO2005013129A1 PCT/JP2003/009635 JP0309635W WO2005013129A1 WO 2005013129 A1 WO2005013129 A1 WO 2005013129A1 JP 0309635 W JP0309635 W JP 0309635W WO 2005013129 A1 WO2005013129 A1 WO 2005013129A1
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WIPO (PCT)
Prior art keywords
priority
instruction
request
unit
information processing
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Application number
PCT/JP2003/009635
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French (fr)
Japanese (ja)
Inventor
Mariko Sakamoto
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Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2003/009635 priority Critical patent/WO2005013129A1/en
Publication of WO2005013129A1 publication Critical patent/WO2005013129A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Definitions

  • the present invention relates to an information processing device, an instruction processing control device, an instruction processing control method, an instruction processing control program, and a computer-readable recording medium storing the instruction processing control program.
  • the present invention relates to a technique for realizing an improvement in throughput by controlling an instruction output to a decoder in an information processing apparatus that executes two or more processes in parallel.
  • FIG. 12 is a block diagram showing a functional configuration of an information processing device adopting a general multi-thread method.
  • the information processing device shown in FIG. 12 includes an instruction address generator 1, a primary instruction cache memory 2, It is composed of an instruction buffer 3, a selector 4, a decoder 5, an arithmetic unit 6, a register 7, a primary data cache memory 8, a secondary cache memory 9, and a buffer 10. It is configured to execute a plurality of instructions based on the obtained plurality of processes in parallel.
  • the processing refers to a program or an instruction flow generated from a certain program (one or more instructions corresponding to the processing flow of instruction fetch and decode).
  • This information processing device is communicably connected to an external memory (main storage unit) 11 via a network or the like.
  • the instruction address generation unit 1 generates an address on the instruction area of the external memory 11 in which an instruction word group of an instruction resulting from the generated processing is stored, and the address generation is independent for each processing. To be done.
  • Primary instruction cache memory 2 is a copy of part of the instruction area on external memory 1 1. And outputs an instruction corresponding to the instruction address generated by the instruction address generation unit 1 from the copy to the instruction buffer 3 at the subsequent stage.
  • the primary data cache memory 8 A part of the data area on the external memory 11 is stored, and data required for the operation in the operation unit 6 is output in response to a request from the operation unit 6.
  • the secondary cache memory 9 stores a copy of the instruction area and a part of the data area on the external memory 11, and an instruction corresponding to the instruction address generated by the address generation unit 1 is a primary instruction. If the data does not exist in the cache memory 2 or the data required for the operation in the operation unit 6 does not exist in the primary data cache memory 8, the secondary cache memory 9 is searched.
  • the instruction buffer 3 temporarily stores instruction words fetched from the primary instruction cache memory 2, the secondary cache memory 9, or the external memory 11 by the instruction address generation unit 1, and in accordance with an instruction from the selector 4, An instruction is issued to the decoder 5.
  • the instruction buffer 3 is configured to temporarily store eight instructions (instruction word groups). To maximize the benefits of the multi-thread system, the instruction buffer 3 is used for multiple processing. Fetching of these instructions is performed independently of each other.
  • the selector 4 functions to control the operation of issuing instructions from the instruction buffer 3 to the decoder 5, and selects at least one of the instructions stored in the instruction buffer 3 and outputs the selected instruction to the decoder 5. It is. In the device shown in FIG. 12, since four decoders 5 are provided, the selector 4 is configured to issue a maximum of four instructions to the decoder 5 at the same time. In addition, the selector 4 is used to maximize the advantages of the multi-thread method. Normally, when a plurality of instructions are stored in the instruction buffer 3, regardless of which processing is based on the plurality of instructions, In other words, as many instructions as possible, that is, the maximum number of instructions that can be issued simultaneously (four instructions in the device shown in Fig. 12) are selected and issued without specifying the processing.
  • the decoder 5 is provided with four of D1, D2, D3 and D4. These decoders Dl, D2, D3 and D4 are issued simultaneously from the instruction buffer 3.
  • the decoder 5 receives each instruction and decodes it in parallel.
  • Each decoder 5 has a format that allows the operation unit (instruction processing unit) 6 to actually recognize the contents of the instruction from the received instruction.
  • the operation resources of the opcode and the operand are secured.
  • the arithmetic unit 6 is configured to include a plurality of arithmetic units in order to process a plurality of instructions in parallel.
  • the arithmetic unit 6 sequentially executes arithmetic processing based on the instructions decoded by the decoder 5, and outputs a result of the arithmetic processing to a subsequent stage.
  • the buffer 10 functions as an interface to the external memory 11.
  • the instruction words related to the instruction for the generated processing are not stored in either the primary instruction cache memory 2 or the secondary cache memory 9 and cannot be fetched from these cache memories.
  • an instruction cache miss When a miss occurs in the cache memory 2 or the secondary cache memory 9 (hereinafter, referred to as an instruction cache miss), or when the arithmetic unit 6 executes an instruction, the data used for the instruction is 1
  • the external memory 11 is referred to via the buffer 10.
  • the instruction group and data is fetched in the primary instruction cache memory 2, the primary data key Yasshu memory 8, 2 Tsugiki Yasshumemori 9 via the buffer 1 0.
  • An information processing device that employs the multi-thread method processes a plurality of processes in parallel, but the unit of the execution environment that executes one process is called a workload.
  • the workload is the usage status of each function of the information processing device (eg, instruction buffer, cache memory, selector, decoder, arithmetic unit, register, knocker, etc.) used when a certain process is executed.
  • each function used by multiple processes is shared between workloads.
  • a plurality of instructions based on a plurality of processes are decoded in parallel and executed in parallel.
  • Resources that is, multiple computing units
  • cache misses when no distinction is made between instruction cache misses and data cache misses
  • results in the free time of computational resources data from external memory 11
  • the instruction execution in the operation unit 6 is stopped due to the long latency, and no processing is performed using the operation resources of the operation unit 6), or the instruction is re-fetched when the branch prediction fails.
  • the idle time of the computational resources generated by this is reduced.
  • the total time for performing a plurality of processes is reduced, and the throughput can be improved.
  • the user of the information processing apparatus may preferentially execute a specific process while executing a plurality of processes in parallel. Even if desired, the workload characteristics of each process cannot be manipulated, so specific processes cannot be prioritized and the user's will cannot be reflected.
  • the present invention has been made in view of such a situation.
  • the present invention provides an information processing apparatus that can effectively use arithmetic resources according to an actual instruction execution situation.
  • the purpose is to achieve a significant improvement in throughput by more reliably reducing the idle time of computational resources.
  • Patent Document 1
  • an information processing device of the present invention is an information processing device that executes two or more processes in parallel, and executes an instruction address for executing the two or more processes.
  • An instruction address generation unit that is generated each time, and temporarily stores a copy of a part of the instruction area on the main memory, and from the copy, the instruction address generation unit
  • An instruction cache memory for outputting an instruction corresponding to the generated instruction address; an instruction buffer for holding a plurality of instructions output from the instruction cache memory; and at least one of the instructions held in the instruction buffer
  • a selector for selecting and outputting an instruction, a decoder for decoding an instruction from the selector, an operation unit for executing an operation in accordance with a result of decoding by the decoder, and a temporary copy of a part of the data area on the main memory.
  • Data cache memory for storing data necessary for the operation in the operation unit in response to a request from the operation unit, and reducing the free time of operation resources in the operation unit
  • a priority calculation unit that calculates / changes the priority of each process so as to perform the processing, and refers to the priority of each process calculated / changed by the priority calculation unit.
  • a control unit for controlling the operation of the selector so as to preferentially select an instruction for the most recent process and output the selected instruction to the decoder.
  • the information processing apparatus further includes a request management unit that manages information related to a request transmitted from the information processing apparatus to the outside in accordance with the execution of the two or more processes for each of the processes. It is preferable that the priority of each process is calculated / changed based on the information on the request managed by the management unit.
  • the priority calculation unit is controlled by the request management unit and waits for a response from the outside. It is preferable to calculate / change the priority of the process that is the source of the request according to the number of requests in the request.
  • the priority calculation unit changes the priority of the process that is the source of the request to be lower than the current level.
  • the priority calculation unit upon receiving a response to the request transmitted along with the execution of any one of the two or more processes, performs a history of the request managed by the request management unit. It is preferable to calculate / change the priority of the process that is the source of the request according to the request.
  • the request is managed by the request management unit, If the request is the oldest of all the requests waiting for the response, it is preferable that the priority calculation unit changes the priority of the process that is the source of the request to be higher than the current level. .
  • the priority calculation unit determines the type of the request managed by the request management unit. It is preferable to calculate / change the priority of the process that is the source of the request according to the request.
  • the priority calculation unit sets the priority of the process that is the source of the request to be lower than the current level. It is preferable to change it to be higher.
  • the priority calculation unit determines, based on the type of the request managed by the request management unit, the process of the transmission source of the request. It is preferable to calculate / change the priority.
  • the priority calculation unit lowers the priority of the process that is the source of the request from the current level. It is preferable to change as follows.
  • the arithmetic unit further includes a sampling unit for sampling the usage status of the computation resources for each of the processes, wherein the priority calculation unit determines each of the processing resources according to the usage status of the computation resources sampled by the sampling unit. It is preferable to calculate / change the processing priority.
  • the priority calculation unit may It is preferable to change the priority so as to be lower than the current state.
  • a request management unit that manages information related to a request transmitted from the information processing apparatus to the outside in accordance with the execution of the two or more processes for each of the processes;
  • a collecting unit that collects information on each of the requests managed by the request managing unit; and a use status of the computation resources collected by the collecting unit. And depending on It is preferable to calculate / change the priority of each process.
  • the priority calculation unit is waiting for a response from the outside, which is managed by the request management unit.
  • the priority of the process that is the source of the request is calculated and changed according to the number of requests and the usage status of the processing resource collected by the collection unit for the process that is the source of the request. Is preferred.
  • the priority calculation unit changes the priority of the process that is the transmission source of the request so as to be lower than the current level. Further, when the number of the requests exceeds a predetermined value, it is preferable that the priority calculation unit changes the priority of the process that is the source of the request to be lower than the current level.
  • the reference value (the initial value of the priority) may be set according to the characteristics of the workload as one or more execution environments used when executing the two or more processes in the information processing device, or according to a user's request.
  • the execution status of a workload as one or more execution environments used when executing the two or more processes in the information processing device, and a reference value (an initial value of the priority) according to the execution status.
  • an instruction processing control device includes an instruction address generation unit, an instruction cache memory, an instruction buffer, a selector, a decoder, a calculation unit, and a data cache memory.
  • An information processing apparatus for executing processing in parallel comprising: an instruction processing control apparatus for controlling an execution state of each instruction for the two or more processings, wherein the idle time of operation resources in the operation unit is reduced. Calculate the priority of each process.Refer to the priority calculation unit that changes Z and the priority of each process calculated and changed by the priority calculation unit, and give priority to the instruction for the process with the higher priority. And a control unit for controlling the operation of the selector so as to select and output the data to the decoder.
  • an instruction processing control method in an information processing apparatus that executes two or more processes described above in parallel, executes an execution state of each instruction for the two or more processes.
  • An instruction processing control method for controlling wherein a priority of each processing is calculated so as to reduce an idle time of a processing resource in the processing unit; a priority calculating step of changing Z; and a calculation / change in the priority calculating step And controlling the operation of the selector so as to preferentially select an instruction for the high-priority processing and output the instruction to the decoder with reference to the priority of each processing performed.
  • an instruction processing control program in an information processing apparatus that executes two or more processes in parallel, controls an execution state of each instruction for the two or more processes.
  • An instruction processing control program for causing a computer to execute a function to perform, the priority calculating unit calculating / changing the priority of each processing so as to reduce the idle time of the processing resources in the processing unit; and
  • the operation of the selector is controlled so as to refer to the priority of each processing calculated / changed by the degree calculation unit and to preferentially select an instruction for the processing with the higher priority and output the instruction to the decoder.
  • the computer is caused to function as a control unit.
  • an information processing apparatus that executes the above-described two or more processes in parallel.
  • An instruction processing control program for causing a computer to execute the function of controlling the execution state of each instruction for the A computer-readable recording medium, wherein the instruction processing control program calculates and changes the priority of each processing so as to reduce the idle time of the processing resources in the processing section;
  • the operation of the selector is controlled by referring to the priority of each process whose Z has been changed by the priority calculation unit and preferentially selecting an instruction for the process with the higher priority and outputting it to the decoder. It is characterized in that the computer functions as a control unit.
  • FIG. 1 is a block diagram illustrating a functional configuration of the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 2 is a diagram showing a request management table in the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 3 is a diagram showing a priority storage table in the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 4 is a flowchart for explaining a procedure of calculating a priority variable at a first timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 5 is a flowchart for explaining a procedure of calculating a priority variable at a second timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 6 is a flowchart for explaining a procedure of calculating a priority variable at a third timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 7 is a flowchart illustrating a procedure of calculating a priority variable at a fourth timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 8 is a flowchart for explaining the procedure of the instruction control method of the information processing apparatus according to the first embodiment of the present invention.
  • FIG. 9 is a block diagram showing a functional configuration of the information processing apparatus according to the second embodiment of the present invention.
  • FIG. 10 is a block diagram showing a functional configuration of an information processing apparatus according to the third embodiment of the present invention.
  • FIG. 11 is a diagram showing a table in the information processing device according to the third embodiment of the present invention.
  • FIG. 12 is a block diagram showing a functional configuration of an information processing apparatus employing a general multi-thread method.
  • FIG. 1 is a block diagram showing a functional configuration of the information processing apparatus according to the first embodiment.
  • the information processing apparatus according to the first embodiment of the present invention has the same configuration as that shown in FIG.
  • An instruction address generator 1 a primary instruction cache memory 2, an instruction buffer 3, a selector 4, a decoder 5, an arithmetic unit 6, an arithmetic unit 6, registers 7, 1 similar to an information processing device employing a general multi-thread system.
  • a secondary data cache memory 8 and a secondary cache memory 9 are provided, and a request management unit 12, a priority calculation unit 13, a control unit 14, and a sampling unit 15 are further provided.
  • the request management unit 12 functions as an interface to the external memory 11.
  • the request management unit 12 refers to the external memory 11 via the request management unit 12, Data is fetched.
  • the request management unit 12 manages the request transmitted by the instruction or data in which the cache miss has occurred in order to refer to the external memory 11, and temporarily stores the information related to the transmitted request. It has a management table 12a.
  • the request management unit 12 uses the request management tape ⁇ 12 a Is associated with the request ID of the request sent to the outside (ie, the external memory 11), the process ID of the process that is the source of the request, and a response waiting flag of the request (the response of the request). (A flag indicating the presence / absence of the request) and the time when the entry of the request is created in the request management table 12a.
  • the priority calculation unit 13 is configured by the information processing apparatus based on the information managed by the request management unit 12 and the usage status of the calculation resources in the calculation unit 6 (the collection result by the collection unit 15 described above).
  • the priority of each process (thread, strand) to be executed is calculated and changed.
  • a priority variable (hereinafter referred to as a priority initial value) set in advance for each process (here, each process ⁇ , ⁇ )
  • Calculating unit 13a that calculates a new priority variable from the above-mentioned priority initial value according to the situation related to the data cache miss, and the priority for each process calculated by this calculating unit 13a. It has a priority storage table 13b for storing degree variables.
  • the situation related to the data cache miss refers to the timing (hereinafter also referred to as the first timing) at which the read (reference) request is sent to the outside via the request management unit 12.
  • the timing at which the request management unit 12 receives a response to the request (hereinafter, also referred to as a second timing) and the timing at which the response to the request is entered into the primary data cache memory 8 (hereinafter, referred to as a third timing). Timing), and the timing at which a data cache miss occurs (hereinafter, also referred to as the fourth timing).
  • the calculating unit 13a of the priority calculating unit 13 converts the priority variable of the process that is the transmission source of the request at the above-described first to fourth timings with reference to FIGS. It is configured to calculate according to the following procedure.
  • the priority variables [P (A), P (B)] are stored for each process ID (here, processes A and B).
  • the priority variables calculated at the above-mentioned first to fourth timings are changed (rewritten) each time, and the latest calculated priority variables are always stored as the priority of each process.
  • control unit 14 refers to the priority variables of the respective processes stored in the priority storage table 13b of the priority calculation unit 13, and based on the priority variables, executes the process with the higher priority.
  • the operation of the selector 4 is controlled so that an instruction for processing is preferentially selected and output to the decoder 5.
  • sampling unit 15 is for sampling the usage status of the computing resources in the arithmetic unit 6 for each process, and based on the usage status of the computing resources sampled in the sampling unit 15, a priority calculation unit described later. Calculation of a priority variable at the first timing in 13 is performed.
  • the usage status of the processing resources is, for example, the entry usage rate of the instruction window, the usage rate of the renaming register, the entry usage rate of the fetch port, and the entry usage rate of the reservation station.
  • the function as the instruction processing control device of the present invention is realized by at least the priority calculation unit 13 and the control unit 14 among the functions of the information processing device.
  • step S10 it is determined whether or not a request to read the external memory 11 has been sent from the request management unit 13 in accordance with the occurrence of a cache miss of data used when executing the instruction from the process A (step S10). Whether or not this request has been sent (first timing) is determined by the calculation unit 13a of the priority calculation unit 13 based on the response waiting flag in the request management table 12a of the request management unit 12. to decide.
  • Step S11 If the request has not been sent (N route of step S10), the priority variable P (A) of the process A that is the source of the request is not changed and is stored in the priority storage table 13b.
  • Step S11 If 1 request 1 is transmitted (YE S route of step S10; first timing), the request is sent to processing A that has transmitted the request.
  • the number of requests waiting for a response from the outside (external memory 11) that is, the request for process A for which an entry has already been made on the request management tape ⁇ / le 12a before the request) W ( 'When the request is sent and received, it is determined whether the value managed by increasing / decreasing the counter) is equal to or more than the predetermined number X1 and smaller than the predetermined number X2 (step S12).
  • XI and X2 are natural numbers that are appropriately set, and the number of requests W is calculated based on the request management table 12a of the request management unit 12, and is calculated by the calculation unit 13a of the priority calculation unit 13.
  • Step S 13 if the number of requests W is not within the range of the predetermined number X1 or more and less than X2 (N route of step S12), it is determined whether the request number W is the predetermined number X2 or more.
  • step S14 if the number of requests W is equal to or more than the predetermined number X 2 (YE S route of step S 13), the correction number i 2 (> 0) preset in the current priority variable P (A) is In addition, the priority variable P (A) of the process A is changed (step S14).
  • step S12 If the number of requests W is in the range of a predetermined number X1 or more and less than X2 (YE S route in step S12), other instructions related to process A, which is the source of the request, are executed. It is determined whether or not the instruction currently uses the computing resources of the computing unit 6 for a predetermined value Y (usage rate) or more (step S15).
  • the calculation unit 13 a of the priority calculation unit 13 determines using the use status of the calculation resources of the calculation unit 6 for the process A collected by the collection unit 15 (the various usage rates described above). . If the utilization rate of the operation resources of the operation unit 6 of the process A is smaller than Y (NO route in step S15), the priority variable P (A) of the process A is not changed, and the priority is stored.
  • the priority stored in the table 13b remains (step S11). Conversely, if the usage rate of the processing resources of the processing unit 6 of the processing A is equal to or more than ⁇ (YES route in step S15), the trapping set in advance to the current priority variable P (A) is performed.
  • the priority variable P (A) of the process A is changed by adding a positive number i 1 (> 0) (step S 16).
  • the priority variable P (A) calculated in this way is changed in the priority storage table 13b of the priority calculation unit 13 each time.
  • the use status of the instruction window entry, the renaming register, the fetch port entry, and the reservation station entry are used as the operation resources of the operation unit 6 as described above.
  • the priority calculation unit 13 uses one of the above four usage rates as the usage status of the computing resources used in the processing at the first timing, and the reference value corresponding to the computing resource is used.
  • the condition for judging the usage status of the computational resource may be set by employing all of the above four computing resources, or the condition may be satisfied if at least one of the four computing resources clears such a determination condition. You may comprise.
  • the request management Regarding the process that is the source of the request managed in the request management table 12a of Part 1 2, according to the number W of requests for which entries have been made in the request management table 12a, the request The priority variable P (A) of the process which is the transmission source is calculated, and the priority variable of the process already stored in the priority storage table 13 b is changed. Note that this change The priority is lower than the priority.
  • step S14 By performing such a change (step S14), execution of processing other than the processing in which many data cache misses occur is prioritized, and the free time for the processing resources of the processing unit 6 is reduced. Can be suppressed.
  • the priority calculation unit 13 calculates the priority variable of the process that is the transmission source of the request in accordance with the usage status (usage rate) of the calculation resource of the calculation unit 6 collected by the collection unit 15. Then, the priority variable of the process that has already been stored in the priority storage table 13 b is changed. This change is also made so that the priority is lower than the current status.
  • step S16 By making such a change (step S16), the execution of other processings other than the processing with a high usage rate is given priority, and the arithmetic unit by a plurality of processings (here, processings A and B) is executed.
  • the use balance of the computing resources of No. 6 can be maintained, and a plurality of processes can be executed efficiently.
  • step S20 the calculation procedure of the priority variable at the second timing in the priority calculation unit 13 will be described with reference to the flowchart (steps S20 to S22) shown in FIG.
  • the received response is due to a data cache miss that occurred in process A, and is the oldest of all requests due to a data cache miss that occurred in process A while waiting for an external response. Is determined (step S20).
  • the request management unit 12 receives the response from the external memory 11 (second timing)
  • the entry of the request management table 12 a of the request management unit 12 becomes This is the timing of invalidation, which can be grasped by sending a signal to the priority calculation unit 13 at this time.
  • the history of the request (whether it is the oldest or not) is calculated by the calculation unit 13a of the priority calculation unit 13 based on the time when the entry was created in the request management table 12a. to decide.
  • the response received from the outside is the data cache miss that occurred in process A. If the request is the oldest of all the requests waiting for the response to the data cache miss caused by the process A (YES route in step S20), the current priority variable P ( The preset correction number i 3 (> 0) is subtracted from A), and the priority variable P (A) of the process A is changed (step S 21). Conversely, the response received from the outside is not due to the data cache miss that occurred in process A, or is included in all requests that are waiting for a data cache miss response due to process A. If it is not the oldest (NO route of step S20), the priority variable P (A) of the process A is not changed, and the current priority stored in the priority storage template 13b is not changed. (Step S22).
  • the calculation unit 13 a of the priority calculation unit 13 performs request management.
  • the priority variable of the process that is the source of the request is calculated in accordance with the history of the request managed by the unit 12, and the priority variable of the process already stored on the priority storage tape is calculated. change. This change is made so that the priority is higher than the current status.
  • step S 21 the process which is the oldest instruction among the instructions stopped by the data cache miss and the source of the instruction is executed with priority. The execution of such processing is performed smoothly.
  • the priority is increased only when the response received from the outside is the oldest of all the requests waiting for a response due to the data cache miss of the process. If the response received is not the oldest but the response received is somehow old, the priority may be increased.
  • Step S30 If it is determined that this response has been entered in the primary data cache memory 8 (YES route of step S30; third timing), The correction number i 4 (> 0) preset for the current priority variable P (A) is reduced, and the priority variable P (A) of the process A is changed (step S31).
  • the priority variable P (A) of the process A is not changed, and the priority is not changed.
  • the priority stored in the degree storage table 13b remains (step S32).
  • the response is a response to the request managed by the request management unit 12.
  • the priority variable of the process that is the transmission source of the request is calculated, and the priority is already stored. Change the priority variable of the process stored in the table. This change is made so that the priority is higher than the current status.
  • step S31 By performing such a change (step S31), the priority is set high when the instruction stopped by the data cache miss is executed, and the instruction is stopped by the data cache miss.
  • the instruction belonging to the process from which the instruction is sent is preferentially sent to the decoder, and the execution is performed smoothly.
  • step S40 it is determined whether or not a data cache miss has occurred along with the execution of the process A (step S40). If a data cache miss has occurred (YES route in step S40; Timing), a preset capture number i 5 (> 0) is added to the current priority variable P (A), and the priority variable P (A) of the process A is changed (step S41). Conversely, if a data cache miss has not occurred (N route of step S40), the priority variable P (A) of the process A is not changed and is stored in the priority storage table 13b. The current priority set remains (step S42).
  • the priority calculation unit 13 calculates the priority variable of the process that is the source of the data cache miss, and calculates the priority variable that has already been stored in the priority storage tape. Change the processing priority variable. This change Is done so that the priority is lower than the current status.
  • step S41 execution of processing other than the processing in which the data cache miss occurred is given priority, and free time is generated in the operation resources of the arithmetic unit 6. Can be suppressed.
  • the priority variables are independently calculated / changed at the above-described first to fourth timings, and the calculation results are Each time, it is stored in the priority storage table 13b of the priority calculation unit 13.
  • the calculation Z of the priority variable is changed for the process B as in the process A.
  • the priority calculation step S50 for calculating the priority of each process in the priority calculation unit 13 and the control unit 14 include a priority calculation step.
  • Degree calculation step Controls the operation of selector 4 so as to refer to the priority of each processing calculated / changed in S50 and preferentially select the instruction for the processing with higher priority and output it to decoder 5.
  • the instruction processing control is performed by the control step S51.
  • the priority calculation step S50 the priority of each process is calculated / changed in the priority calculation unit 13 in the procedure described above with reference to FIGS.
  • the priority calculation step S50 is considered so as not to become a volt-neck for the clock cycle of the arithmetic unit.
  • the control unit 14 controls the power selector 4, and among the instructions held in the instruction buffer 3, the high-priority processing is performed by the priority storage table 1 of the priority calculation unit 13. 3 Based on the priority variables of processes A and B stored in b, compare the priority variables of each process, select the instruction for the process with the higher priority first, and send it to the decoder 5 at most. Outputs four instructions.
  • instruction buffer 3 If there is no high-priority processing instruction in instruction buffer 3, An instruction belonging to a process with a higher priority is selected. If the number of instructions sent from the instruction buffer 3 to the decoder 5 is smaller than the number of decoders (here, four), instructions for each processing are selected one after another in descending order of priority and sent to the decoder 5. Can be In this case, multiple processing instructions are decoded in one cycle.
  • control unit 14 is configured to operate once in a predetermined period in which the selector 4 outputs an instruction to the decoder 5 to switch processing. This is because if the control unit 14 is activated every time the selector 4 outputs an instruction to the decoder 5 and the processing is switched based on the priority, the cost of switching the processing is increased, and the throughput is rather increased. This will hinder the improvement of the quality.
  • the control unit 14 sets the priority variables of the processes A and B stored in the priority storage table 13 b of the priority calculation unit 13 every cycle in which the selector 4 outputs the instruction to the decoder 5. If the difference between the priority variables of the processing A and the processing B is equal to or larger than a preset threshold value, the instruction of the processing with the higher priority is preferentially selected and output to the decoder 5. May be configured. As a result, the cost increase associated with the above-described process switching is suppressed, and the process can be switched efficiently, so that the throughput can be reliably improved. .
  • the priority of each process is calculated according to the Z.
  • the instruction held in the instruction buffer 3 is output to the decoder 5 based on the priority and is executed in the arithmetic unit 6, so that the actual instruction execution status is changed.
  • the computing resources of the computing unit 6 are used efficiently in a plurality of processes, and it is ensured that free time is generated in the computing resources. Indeed, the throughput is greatly improved.
  • the priority calculation unit 13 is configured to calculate the priority variables at the first to fourth timings. For the calculation at the third timing, either It may be configured as follows.
  • FIG. 9 is a block diagram illustrating a functional configuration of the information processing apparatus according to the second embodiment. Note that, in FIG. 9, the same reference numerals as those described above indicate the same or almost the same portions, and thus detailed description thereof will be omitted.
  • the information processing apparatus according to the second embodiment of the present invention has the same configuration as the information processing apparatus of the above-described first embodiment, and further includes operation means 16, monitor means 18, It is provided with display means 20.
  • the operation means 16 is for manually operating the characteristic of the workload as the execution environment of a certain process or the value (also referred to as a reference value) for determining the priority of a certain process.
  • the monitoring means 18 is for monitoring the execution status of the work module for each process executed by the information processing apparatus.
  • the usage status of each function of the information processing device such as the usage status of the information processing device is monitored.
  • the display means 20 displays the execution status of the workload of each process monitored by the monitor means 18 on a monitor or the like connected to the information processing apparatus.
  • the value (reference value) for determining the priority of a specific process is, specifically, the calculation unit 13a of the priority calculation unit 13 calculates the priority of the process first applied.
  • the operation hand Step 16 includes hardware such as a keyboard and a mouse, and software for reflecting information (numerical values and the like) input by operating the hardware to values used in the calculator 13a. It is a man machine interface.
  • the priority of the process A can be increased.
  • the priority initial value of the process A is made smaller than the priority initial values of the other processes B. As a result, the priority variable of the process A can be relatively reduced, and the priority of the process A can be increased.
  • the priority calculation unit 13 increases the values of the correction values i3 and i4 used for calculating the priority variable of the process A.
  • the priority of the process A can be made higher than that of the other process B.
  • the reference value is changed by the operation means 16 in the above (1) to (5), the user can freely operate the change width.
  • the operating unit 16 uses the criteria used to calculate / change the priority in the priority calculating unit 13. Since the value can be manipulated so that the priority of a specific process is made higher, the specific process can be executed with priority and the user's intention can be reflected.
  • the reference value for the process B is set to the relative value of the priority of the process B by performing the operation reverse to the above operations (1) to (5). May be set so that process A is executed with priority.
  • the execution status of the workload for each process is monitored by the monitor unit 18 and the monitoring result is displayed on a monitor or the like by the display unit 20. Workload execution status can be visually checked. Therefore, after recognizing the execution status of the workload for each process, the user can operate the reference value used for calculating / changing the priority in the priority calculation unit 13 by the operation means 16 using the operation means 16. Depending on the workload status of each process, specific processes can be executed preferentially.
  • FIG. 10 is a block diagram illustrating a functional configuration of the information processing apparatus according to the third embodiment.
  • FIG. 10 since the same reference numerals as those described above indicate the same or almost the same parts, detailed description thereof will be omitted.
  • the information processing apparatus has the same configuration as the information processing apparatus of the above-described first embodiment, and further includes the execution of a workload as an execution environment.
  • a change that dynamically changes the reference value of such processing to a value according to the execution status of the workload monitored by the monitoring means 18 by referring to the table 17 in response to the result of the moeta by the means 18 means It is composed with 19. '
  • the table 17 is configured to be able to hold a specific workload and a reference value corresponding to the workload according to the user's intention and the like. As an example, as shown in Fig. 11, the workload execution status of case 1 to case 3 and the reference value according to the execution status of each workload are held.
  • Case 1 in Table 17 shows the hit rates in the primary instruction cache memory 2 and the primary data cache memory 8 (that is, the rate at which the instruction group based on the instruction is stored in the primary instruction cache memory 2). And the rate at which data used for instructions are stored in the primary data cache memory 8) is 97% or more, and the first priority in the calculation unit 13a of the priority calculation unit 13
  • the value 1 of the reference value X 2 (see steps S 12 and S 13 in FIG. 4) used for calculating / changing the priority variable at the timing of is held in association with each other.
  • Case 2 in Table 17 shows the workload execution status where the number of data fetch requests when executing instructions for such processing is 300000 or less, and the calculation unit of the priority calculation unit 13 13 The priority value at the first timing in 3a The value 1 of the reference value X2 (see steps S12 and S13 in Fig. 4) used for calculating / changing the variable is held in association with Have been.
  • a cache miss based on such processing occurs at least once in 500 instructions, and the execution time of the processing in the arithmetic unit 6 is executed in parallel with this processing.
  • the execution status of the workload which is 70% or less of the execution time of the other processing, is caused by the calculation Z of the priority variable at the first timing in the calculation unit 13a of the priority calculation unit 13.
  • the value of the correction value i 1 used (see step S 16 in FIG. 4) is decremented by 1, and the correction value i 3 used to change the priority variable Z at the second timing (step S 16 in FIG. 5) 2 1 ′) or the correction value i 4 (see step S 31 in FIG. 6) used to calculate / change the priority variable at the third timing. Is held.
  • the monitoring means 18 monitors the execution status of the first load for each process. Specifically, the monitoring means 18 determines whether the usage status of the processing resources of each process, the usage status of the cache memory, and the like. The usage status of each function of the information processing device is monitored.
  • the control unit 14 and the power priority calculation unit 13 calculate each Z-changed process.
  • the selector 4 is controlled so that a process having a higher priority is preferentially selected on the basis of the priority and output from the instruction buffer 3 to the decoder 5.
  • the monitoring status of the processing workload execution status is constantly monitored, and the changing means 19 receives the monitoring result of the monitoring means 18, refers to the tape hole 17, and holds the monitoring result in the table 17.
  • the reference values in the priority calculation unit 13 are set so that the reference values corresponding to the workload execution status stored in Table 17 are obtained. To change.
  • the monitoring result of the workload of the processing A by the monitoring means 18 is shown in Case 1 of Table 17. If it corresponds to the workload execution status, the change unit 19 sets the reference value X2 of the process A of the priority calculation unit 13 to 1. As a result, if a cache miss has hardly occurred, or if a cache miss has occurred in process A, the priority of process A can be set to be lower (step S 14 in FIG. 4). ), And it is possible to maintain a good execution balance with process B.
  • the changing means 19 performs the processing of the priority calculation unit 13
  • the reference value X 2 of A is set to 1.
  • the priority of process A can be set to be low (see step S14 in FIG. 4).
  • the execution balance (computation resource sharing balance) can be maintained well.
  • the monitoring result of the workload of process A by the monitoring means 18 corresponds to the workload execution status shown in Case 3 of Table 17, cache misses occur frequently and other processes (here, Use of computing resources compared to process B)
  • the priority can be set to be higher for the process A having a small ratio (see step S16 in FIG. 4 and step S21 in FIG. 5 or step S31 in FIG. 6). This makes it possible to change the priority of the processing A, which does not use the computational resources of the processing unit 6 as much as compared with the other processing B, and is not executed smoothly, to a higher priority. Can be kept good.
  • the changing unit 19 is configured to change the workload execution status based on the workload execution status held in the table 17 and the reference value corresponding to the workload execution status. Since the reference value of the priority calculation unit 13 is dynamically changed, the priority of such processing is dynamically changed according to the workload execution status. As a result, a plurality of processes can be executed according to the workload execution status, and the intention of the user can be reflected according to the workload execution status.
  • the workload execution status, the contents of the reference values corresponding thereto, and specific numerical values stored in the table 17 according to the present embodiment are shown as examples, and are not limited thereto. .
  • the workload execution status and the corresponding reference value stored in Table 17 are changed depending on the user's intention, the execution status of the process in the information processing device, and the like.
  • the present invention is not limited to this.
  • the present invention is applied similarly to the above-described embodiments even when three or more processes are executed in parallel, and the same operation and effect as the above-described embodiments can be obtained.
  • the type of request handled by the request management unit 12 covers a type other than a data cache miss. In such a case, it is conceivable to prepare individual reference values depending on the type of request. Furthermore, the maximum value and the minimum value of the priority variable for such processing are set according to the type of the request, and when these values are exceeded, May be configured to stop the process of increasing / decreasing priority variables (calculation / change process of priority variables).
  • the functions of the request management unit 12, the priority calculation unit 13 (calculation unit 13a), the control unit 14, the collection unit 15, the operation unit 16, the monitor unit 18, and the change unit 19 described above are implemented by a computer (CPU , An information processing device, and various terminals) by executing a predetermined application program (command processing control program).
  • the program is provided in a form recorded on a computer-readable recording medium such as a flexible disk, a CD-ROM, a CD-R, a CD-RW, and a DVD.
  • the computer reads the instruction processing control program from the recording medium, transfers it to the internal storage device or the external storage device, stores it, and uses it.
  • the program may be recorded on a storage device (recording medium) such as a magnetic disk, an optical disk, or a magneto-optical disk, and provided to the computer from the storage device via a communication line. ,.
  • the computer is a concept including hardware and an OS (operating system), and means hardware that operates under the control of the OS.
  • OS operating system
  • the hardware itself corresponds to a computer.
  • the hardware has at least a microprocessor such as a CPU and a means for reading a computer program recorded on a recording medium.
  • the application program as the instruction processing control program includes a request management unit 12, a priority calculation unit 13, a control unit 14, a sampling unit 15, an operation unit 16, a monitoring unit 18, It includes a program code for realizing the function as the changing means 19.
  • some of the functions may be realized by OS instead of application programs.
  • the recording medium includes an IC card, a ROM cartridge, a magnetic tape, and a magnetic disk.
  • IC card computer internal storage (memory such as RAM and ROM), external storage
  • RAM random access memory
  • ROM read-only memory
  • external storage Various computer-readable media, such as storage devices and printed materials on which codes such as bar codes are printed, can also be used.
  • the priority of each process is set so that the computing resources can be effectively used according to the actual instruction execution status. Since the calculation / change is performed and the processing is executed based on this priority, it is possible to more surely reduce the idle time of the computational resources and achieve a significant improvement in the throughput.
  • the present invention is suitable for use in an information processing device such as a computer employing a multi-thread system, and its usefulness is considered to be extremely high.

Abstract

In an information processing device executing two or more processes in parallel, a calculation resource is used effectively according to an actual instruction execution condition and an empty time of calculation resource is surely reduced so as to realize a significant increase of throughput. The information processing device includes a priority calculation section (13) for calculating/modifying the priority of each process so as to reduce the calculation resource empty time in a calculation section (6), and a control section (14) for referencing the priority of each process calculated/modified by the priority calculation section (13) and controlling operation of a selector (4) so as to select an instruction of a higher priority by priority and output it to a decoder (5).

Description

情報凊理装眮䞊びに呜什凊理制埡装眮 呜什凊理制埡方法 呜什凊理制埡プログ ラム及び呜什凊理制埡プログラムを蚘録したコンピュヌタ読取可胜な蚘録媒䜓 技術分野 TECHNICAL FIELD The present invention relates to an information processing device, an instruction processing control device, an instruction processing control method, an instruction processing control program, and a computer-readable recording medium storing the instruction processing control program.
本発明は、 2以䞊の凊理を䞊列的に実行する情報凊理装眮においお、 デコヌダ ぞ出力される呜什を制埡しおスルヌプットの向䞊を実珟するための技術に関する。 背景技術 明  The present invention relates to a technique for realizing an improvement in throughput by controlling an instruction output to a decoder in an information processing apparatus that executes two or more processes in parallel. Background art
埓来から䞀぀のプロセッサ 挔算郚 内で耇数の凊理 スレッ ド ス トラン ド を䞊列的に実行するマルチスレッド方匏曞を採甚した情報凊理装眮がある。 こ のマルチスレッド方匏に぀いおは、 䟋えば、 䞋蚘特蚱文献 1に詳现に述べられお いる。  Conventionally, there is an information processing apparatus that employs a multi-thread system that executes a plurality of processes (threads, strands) in parallel within one processor (arithmetic unit). This multi-thread method is described in detail in, for example, Patent Document 1 below.
図 1 2は䞀般的なマルチスレッド方匏を採甚した情報凊理装眮の機胜構成を瀺 すプロック図で、 この図 1 2に瀺す情報凊理装眮は、 呜什ァドレス生成郚 1 1 次呜什キダッシュメモリ 2 , 呜什バッファ 3 , セレクタ 4 デコヌダ 5 , 挔算郚 6 , レゞスタ 7 , 1次デヌタキャッシュメモリ 8 2次キャッシュメモリ 9及び バッファ 1 0をそなえお構成され、 挔算郚 6においお、 コマンド入力等で発生さ れた耇数の凊理に基づく耇数の呜什を䞊列的に実行するように構成されおいる。 ここで、 凊理ずは、 プログラム、 もしくは、 あるプログラムから発生する呜什 流 呜什フェッチずデコヌドずの凊理の流れに察応した 1以䞊の呜什 のこずを いう。  FIG. 12 is a block diagram showing a functional configuration of an information processing device adopting a general multi-thread method. The information processing device shown in FIG. 12 includes an instruction address generator 1, a primary instruction cache memory 2, It is composed of an instruction buffer 3, a selector 4, a decoder 5, an arithmetic unit 6, a register 7, a primary data cache memory 8, a secondary cache memory 9, and a buffer 10. It is configured to execute a plurality of instructions based on the obtained plurality of processes in parallel. Here, the processing refers to a program or an instruction flow generated from a certain program (one or more instructions corresponding to the processing flow of instruction fetch and decode).
この情報凊理装眮は、 ネットワヌク等を介しお倖郚メモリ 䞻蚘憶郚 1 1ず 通信可胜に接続されおいる。  This information processing device is communicably connected to an external memory (main storage unit) 11 via a network or the like.
呜什ァドレス生成郚 1は、 発生された凊理から生じる呜什に぀いおの呜什語矀 が蚘憶されおいる倖郚メモリ 1 1の呜什領域䞊のアドレスを生成するものであり、 ァドレス生成は各凊理毎に独立しお行なわれるようにな぀おいる。  The instruction address generation unit 1 generates an address on the instruction area of the external memory 11 in which an instruction word group of an instruction resulting from the generated processing is stored, and the address generation is independent for each processing. To be done.
1次呜什キャッシュメモリ 2は、 倖郚メモリ 1 1䞊の呜什領域の䞀郚のコピヌ を栌玍し、 そのコピヌの䞭から呜什ァドレス生成郚 1によっお生成された呜什ァ ドレスに応じた呜什を埌段の呜什バッファ 3ぞ出力するものであり、 これに察し お、 1次デヌタキャッシュメモリ 8は、 倖郚メモリ 1 1䞊のデヌタ領域の䞀郚の コピヌを栌玍し、 挔算郚 6での挔算に必芁なデヌタを挔算郚 6からの芁求に応じ お出力するものである。 たた、 2次キャッシュメモリ 9は、 倖郚メモリ 1 1䞊の 呜什領域及びデヌタ領域の䞀郚のコピヌを栌玍するもので、 ァドレス生成郚 1に よっお生成された呜什ァドレスに応じた呜什が 1次呜什キャッシュメモリ 2に存 圚しない堎合や、 挔算郚 6での挔算に必芁なデヌタが 1次デヌタキャッシュメモ リ 8に存圚しない堎合、 この 2次キャッシュメモリ 9が怜玢されるようになっお いる。 Primary instruction cache memory 2 is a copy of part of the instruction area on external memory 1 1. And outputs an instruction corresponding to the instruction address generated by the instruction address generation unit 1 from the copy to the instruction buffer 3 at the subsequent stage. On the other hand, the primary data cache memory 8 A part of the data area on the external memory 11 is stored, and data required for the operation in the operation unit 6 is output in response to a request from the operation unit 6. The secondary cache memory 9 stores a copy of the instruction area and a part of the data area on the external memory 11, and an instruction corresponding to the instruction address generated by the address generation unit 1 is a primary instruction. If the data does not exist in the cache memory 2 or the data required for the operation in the operation unit 6 does not exist in the primary data cache memory 8, the secondary cache memory 9 is searched.
呜什バッファ 3は、 呜什ァドレス生成郚 1により 1次呜什キャッシュメモリ 2 2次キャッシュメモリ 9もしくは倖郚メモリ 1 1からフェッチされた呜什語矀を 䞀時的に蓄え、 セレクタ 4からの指瀺に応じお埌段のデコヌダ 5ぞ呜什を発行す るものである。 ここでは、 呜什バッファ 3は 8぀の呜什 呜什語矀 を䞀時的に 蓄えられるように構成されおおり、 マルチスレッ ド方匏のメリットを最倧限に発 揮させるベく、 耇数の凊理にかかる耇数の呜什のフェツチがそれぞれ独立しお行 なわれるようになっおいる。  The instruction buffer 3 temporarily stores instruction words fetched from the primary instruction cache memory 2, the secondary cache memory 9, or the external memory 11 by the instruction address generation unit 1, and in accordance with an instruction from the selector 4, An instruction is issued to the decoder 5. Here, the instruction buffer 3 is configured to temporarily store eight instructions (instruction word groups). To maximize the benefits of the multi-thread system, the instruction buffer 3 is used for multiple processing. Fetching of these instructions is performed independently of each other.
セレクタ 4は、 呜什バッファ 3からデコヌダ 5ぞの呜什発行動䜜を制埡する機 胜を果すもので、 呜什バッファ 3に蓄積されおいる呜什のうちの少なくずも䞀぀ を遞択しおデコヌダ 5ぞ出力するものである。 図 1 2に瀺す装眮では、 デコヌダ 5が 4぀そなえられおいるので、 セレクタ 4は、 最倧で同時に 4぀の呜什をデコ ヌダ 5ぞ発行するように構成されおいる。 たた、 セレクタ 4は、 マルチスレッ ド 方匏のメリットを最倧限に発揮させるベく、 通垞、 呜什バッファ 3に呜什が耇数 蓄積されおいるずきには、 耇数の呜什がどの凊理に基づくものかに関わらず、 ぀ たり、 凊理を特定するこずなく、 なるべく倚くの呜什、 ぀たり、 同時発行可胜な 最倧数の呜什 図 1 2に瀺す装眮では 4぀の呜什 を遞択しお発行するようにな ぀おいる。  The selector 4 functions to control the operation of issuing instructions from the instruction buffer 3 to the decoder 5, and selects at least one of the instructions stored in the instruction buffer 3 and outputs the selected instruction to the decoder 5. It is. In the device shown in FIG. 12, since four decoders 5 are provided, the selector 4 is configured to issue a maximum of four instructions to the decoder 5 at the same time. In addition, the selector 4 is used to maximize the advantages of the multi-thread method. Normally, when a plurality of instructions are stored in the instruction buffer 3, regardless of which processing is based on the plurality of instructions, In other words, as many instructions as possible, that is, the maximum number of instructions that can be issued simultaneously (four instructions in the device shown in Fig. 12) are selected and issued without specifying the processing.
デコヌダ 5ずしおは、 D l D 2 , D 3 , D 4の 4぀がそなえられおいる。 こ れらのデコヌダ D l D 2 , D 3 , D 4は、 呜什バッファ 3から同時に発行され た呜什をそれぞれ受信しお䞊列的にデコヌドするもので、 各デコヌダ 5は、 受信 した呜什から、 実際に挔算郚 呜什凊理郚 6が呜什の内容を認識するこずの可 胜な圢匏であるォペコヌドずその呜什の察象であるオペランドずの抜出を行なう ずずもに、 これらォペコヌドずオペランドずの挔算資源を確保するものである。 挔算郚 6は、 耇数の呜什を䞊列的に凊理するため、 耇数の挔算噚をそなえお構 成され、 デコヌダ 5でデコヌドされた呜什に基づく挔算凊理を順次実行し、 その 挔算凊理の結果を埌段のレゞスタ 7に送るものである。 The decoder 5 is provided with four of D1, D2, D3 and D4. These decoders Dl, D2, D3 and D4 are issued simultaneously from the instruction buffer 3. The decoder 5 receives each instruction and decodes it in parallel. Each decoder 5 has a format that allows the operation unit (instruction processing unit) 6 to actually recognize the contents of the instruction from the received instruction. In addition to extracting the opcode and the operand that is the target of the instruction, the operation resources of the opcode and the operand are secured. The arithmetic unit 6 is configured to include a plurality of arithmetic units in order to process a plurality of instructions in parallel. The arithmetic unit 6 sequentially executes arithmetic processing based on the instructions decoded by the decoder 5, and outputs a result of the arithmetic processing to a subsequent stage. To register 7.
バッファ 1 0は、 倖郚メモリ 1 1に察するむンタヌフェヌスずしお機胜するも のである。 発生された凊理に぀いおの呜什にかかる呜什語矀が、 1次呜什キダッ シュメモリ 2 2次キャッシュメモリ 9のいずれにも栌玍されおおらず、 これら キャッシュメモリからはフェッチできない珟象、 ぀たり、 1次呜什キャッシュメ モリ 2 2次キダッシュメモリ 9でのミスヒット (以䞋、 呜什キャッシュミスず いう が発生した堎合や、 挔算郚 6においお呜什を実行する際に、 圓該呜什に䜿 甚されるデヌタが 1次デヌタキャッシュメモリ 8 , 2次キャッシュメモリ 9のい ずれにも栌玍されおおらず、 これらキャッシュメモリからはフェッチできない珟 象、 ぀たり、 1次デヌタキダッシュメモリ 8 2次キャッシュメモリ 9でのミス ヒット (以䞋、 デヌタキャッシュミスずいう) が発生した堎合には、 バッファ 1 0を介しお倖郚メモリ 1 1が参照され、 バッファ 1 0を経由しお圓該呜什語矀や デヌタが 1次呜什キャッシュメモリ 2 1次デヌタキダッシュメモリ 8 , 2次キ ャッシュメモリ 9にフェッチされる。  The buffer 10 functions as an interface to the external memory 11. The instruction words related to the instruction for the generated processing are not stored in either the primary instruction cache memory 2 or the secondary cache memory 9 and cannot be fetched from these cache memories. When a miss occurs in the cache memory 2 or the secondary cache memory 9 (hereinafter, referred to as an instruction cache miss), or when the arithmetic unit 6 executes an instruction, the data used for the instruction is 1 An event that is not stored in either the secondary data cache memory 8 or the secondary cache memory 9 and cannot be fetched from these cache memories, that is, a miss hit in the primary data cache memory 8 or the secondary cache memory 9 (Hereinafter referred to as a data cache miss), the external memory 11 is referred to via the buffer 10. , The instruction group and data is fetched in the primary instruction cache memory 2, the primary data key Yasshu memory 8, 2 Tsugiki Yasshumemori 9 via the buffer 1 0.
なお、 マルチスレツ ド方匏を採甚した情報凊理装眮は耇数の凊理を䞊列的に凊 理するが、 䞀぀の凊理を実行する実行環境の単䜍をワヌクロヌドずいう。 ぀たり、 ワヌクロヌドずは、 ある凊理が実行されるこずにより䜿甚される情報凊理装眮の 各機胜 䟋えば、 呜什バッファ キャッシュメモリ セレクタ デコヌダ 挔算 郚 レゞスタ ノくッファ等 の䜿甚状況にかかる実行環境であり、 耇数の凊理に より䜿甚される各機胜はワヌクロヌド間で共有されるこずになる。  An information processing device that employs the multi-thread method processes a plurality of processes in parallel, but the unit of the execution environment that executes one process is called a workload. In other words, the workload is the usage status of each function of the information processing device (eg, instruction buffer, cache memory, selector, decoder, arithmetic unit, register, knocker, etc.) used when a certain process is executed. In this environment, each function used by multiple processes is shared between workloads.
このように、 䞀般的なマルチスレッド方匏を採甚した情報凊理装眮では、 耇数 の凊理に基づく耇数の呜什が䞊列的にデコヌドされ、 䞊列的に実行されるように なっおおり、 挔算郚 6の挔算資源 即ち、 耇数の挔算噚 を耇数の凊理で共有利 甚するこずにより、 呜什キャッシュミスやデヌタキャッシュミス 以䞋、 呜什キ ャッシュミスずデヌタキダッシュミスずを区別しない堎合は単にキダッシュミス ずいう に䌎っお発生する挔算資源の空き時間 倖郚メモリ 1 1からデヌタをフ ゚ッチするレむテンシが長いこずで挔算郚 6での呜什実行が停止しお挔算郚 6の 挔算資源で䜕も凊理を行なわない時間 や、 分岐予枬を倱敗したずきに呜什をフ ゚ッチしなおすこずで発生する挔算資源の空き時間を枛らすようにな぀おいる。 これにより、 耇数の凊理を行なう トヌタルの時間が短瞮され、 スルヌプットを向 䞊させるこずができる。 As described above, in an information processing apparatus employing a general multi-thread method, a plurality of instructions based on a plurality of processes are decoded in parallel and executed in parallel. Resources (that is, multiple computing units) can be shared by multiple processes. The use of instruction cache misses and data cache misses (hereinafter, simply referred to as cache misses when no distinction is made between instruction cache misses and data cache misses) results in the free time of computational resources (data from external memory 11 The instruction execution in the operation unit 6 is stopped due to the long latency, and no processing is performed using the operation resources of the operation unit 6), or the instruction is re-fetched when the branch prediction fails. As a result, the idle time of the computational resources generated by this is reduced. As a result, the total time for performing a plurality of processes is reduced, and the throughput can be improved.
し力 しながら、 単に耇数の呜什を䞊列的に実行するだけでは、 挔算郚 6の挔算 資源を有効に共有利甚するこずができないため、 実際の呜什実行状況に応じお挔 算資源を有効に共有利甚できるようにしお、 より確実に挔算資源の空き時間を削 枛するこずが望たれおいる。  However, simply executing a plurality of instructions in parallel cannot effectively share and use the operation resources of the operation unit 6, so that the operation resources are effectively shared according to the actual instruction execution status. It is hoped that it will be available to reduce the free time of computing resources more reliably.
たた、 䞊蚘のような䞀般的なマルチスレツド方匏を採甚した情報凊理装眮では、 圓該情報凊理装眮を䜿甚するナヌザが、 耇数の凊理の䞊列実行䞭に、 特定の凊理 を優先的に実行するこずを望む堎合でも、 各凊理のワヌクロヌド特性を操䜜でき ないため、 特定の凊理を優先させるこずはできず、 ナヌザの意思を反映させるこ ずができない。  Also, in the information processing apparatus employing the general multi-thread method as described above, the user of the information processing apparatus may preferentially execute a specific process while executing a plurality of processes in parallel. Even if desired, the workload characteristics of each process cannot be manipulated, so specific processes cannot be prioritized and the user's will cannot be reflected.
本発明は、 このような状況に鑑み創案されたもので、 2以䞊の凊理を䞊列的に 実行する情報凊理装眮においお、 実際の呜什実行状況に応じお挔算資源を有効に 利甚できるようにしお、 より確実に挔算資源の空き時間を削枛しおスルヌプット の倧幅な向䞊を実珟するこずを目的ずする。  The present invention has been made in view of such a situation. In an information processing apparatus that executes two or more processes in parallel, the present invention provides an information processing apparatus that can effectively use arithmetic resources according to an actual instruction execution situation. The purpose is to achieve a significant improvement in throughput by more reliably reducing the idle time of computational resources.
特蚱文献 1  Patent Document 1
米囜特蚱第 6 0 7 3 1 5 9号明现曞 発明の開瀺  U.S. Pat.No. 6,073,159 Description of the Invention
䞊蚘目的を達成するために、 本発明の情報凊理装眮は、 2以䞊の凊理を䞊列的 に実行する情報凊理装眮であっお、 前蚘 2以䞊の凊理を実行するための呜什ァド レスを前蚘凊理毎に生成する呜什ァドレス生成郚ず、 䞻蚘憶䞊の呜什領域の䞀郚 のコピヌを䞀時的に栌玍し、 該コピヌの䞭から、 該呜什アドレス生成郚によっお 生成された前蚘呜什ァドレスに応じた呜什を出力する呜什キャッシュメモリず、 該呜什キダッシュメモリから出力された耇数の呜什を保持する呜什バッファず、 該呜什バッファに保持された呜什のうちの少なくずも䞀぀を遞択しお出力するセ レクタず、 該セレクタからの呜什をデコヌドするデコヌダず、 該デコヌダによる デコヌド結果に応じた挔算を実行する挔算郚ず、 䞻蚘憶䞊のデヌタ領域の䞀郚の コピヌを䞀時的に栌玍し、 該コピヌの䞭から、 該挔算郚での挔算に必芁なデヌタ を該挔算郚からの芁求に応じお出力するデヌタキャッシュメモリず、 該挔算郚に おける挔算資源の空き時間を削枛するように各凊理の優先床を算出/倉曎する優 先床算出郚ず、 該優先床算出郚によ぀お算出/倉曎された各凊理の優先床を参照 し、 前蚘優先床の高い凊理に぀いおの呜什を優先的に遞択しお該デコヌダぞ出力 するように該セレクタの動䜜を制埡する制埡郚ずをそなえたこずを特城ずしおい'」 る。 In order to achieve the above object, an information processing device of the present invention is an information processing device that executes two or more processes in parallel, and executes an instruction address for executing the two or more processes. An instruction address generation unit that is generated each time, and temporarily stores a copy of a part of the instruction area on the main memory, and from the copy, the instruction address generation unit An instruction cache memory for outputting an instruction corresponding to the generated instruction address; an instruction buffer for holding a plurality of instructions output from the instruction cache memory; and at least one of the instructions held in the instruction buffer A selector for selecting and outputting an instruction, a decoder for decoding an instruction from the selector, an operation unit for executing an operation in accordance with a result of decoding by the decoder, and a temporary copy of a part of the data area on the main memory. Data cache memory for storing data necessary for the operation in the operation unit in response to a request from the operation unit, and reducing the free time of operation resources in the operation unit A priority calculation unit that calculates / changes the priority of each process so as to perform the processing, and refers to the priority of each process calculated / changed by the priority calculation unit. And a control unit for controlling the operation of the selector so as to preferentially select an instruction for the most recent process and output the selected instruction to the decoder.
たた、 前蚘 2以䞊の凊理の実行に䌎い圓該情報凊理装眮から倖郚に察しお送出 されたリク゚ストに関する情報を前蚘凊理毎に管理するリク゚スト管理郚をさら にそなえ、 該優先床算出郚が、 該リク゚スト管理郚で管理されおいる前蚘リクェ ストに関する情報に基づいお、 各凊理の前蚘優先床を算出/倉曎するこずが奜た しい。  The information processing apparatus further includes a request management unit that manages information related to a request transmitted from the information processing apparatus to the outside in accordance with the execution of the two or more processes for each of the processes. It is preferable that the priority of each process is calculated / changed based on the information on the request managed by the management unit.
さらに、 䞻蚘憶デヌタの読出しリク゚ストが前蚘リク゚ストずしお圓該情報凊 理装眮から倖郚に察しお送出された際に、 該優先床算出郚が、 該リク゚スト管理 郚で管理されおいる、 倖郚からの応答埅ち䞭のリク゚ストの数に応じお、 圓該リ ク゚ス卜の送出元である凊理の前蚘優先床を算出/倉曎するこずが奜たしい。  Further, when the main memory data read request is sent from the information processing device to the outside as the request, the priority calculation unit is controlled by the request management unit and waits for a response from the outside. It is preferable to calculate / change the priority of the process that is the source of the request according to the number of requests in the request.
たた、 前蚘リク゚ストの数が所定倀を超えおいる堎合、 該優先床算出郚が、 圓 該リク゚ストの送出元である凊理の前蚘優先床を珟状よりも䜎くするように倉曎 するこずが奜たしい。  Further, when the number of the requests exceeds a predetermined value, it is preferable that the priority calculation unit changes the priority of the process that is the source of the request to be lower than the current level.
なお、 前蚘 2以䞊の凊理のいずれか䞀぀の実行に䌎っお送出された前蚘リクェ ストに察する応答を受け取った際に、 該優先床算出郚が、 該リク゚スト管理郚で 管理されおいる圓該リク゚ストの履歎に応じお、 圓該リク゚ストの送出元である 凊理の前蚘優先床を算出/倉曎するこずが奜たしい。  Note that upon receiving a response to the request transmitted along with the execution of any one of the two or more processes, the priority calculation unit performs a history of the request managed by the request management unit. It is preferable to calculate / change the priority of the process that is the source of the request according to the request.
さらに、 圓該リク゚ストが、 該リク゚スト管理郚で管理されおいる、 倖郚から の応答埅ち䞭の党おのリク゚ストの䞭で最も叀いものである堎合、 該優先床算出 郚が、 圓該リク゚ストの送出元である凊理の前蚘優先床を珟状よりも高くするよ うに倉曎するこずが奜たしい。 Further, the request is managed by the request management unit, If the request is the oldest of all the requests waiting for the response, it is preferable that the priority calculation unit changes the priority of the process that is the source of the request to be higher than the current level. .
なお、 前蚘 2以䞊の凊理のいずれか䞀぀の実行に䌎っお送出された前蚘リクェ ストに察する応答を受け取った際に、 該優先床算出郚が、 該リク゚スト管理郚で 管理されおいる圓該リク゚ストの皮別に応じお、 圓該リク゚ストの送出元である 凊理の前蚘優先床を算出/倉曎するこずが奜たしい。  Note that upon receiving a response to the request transmitted along with execution of any one of the two or more processes, the priority calculation unit determines the type of the request managed by the request management unit. It is preferable to calculate / change the priority of the process that is the source of the request according to the request.
さらに、 圓該リク゚ストが、 該デヌタキャッシュメモリでのミスヒットに䌎぀ お送出されたものである堎合、 該優先床算出郚が、 圓該リク゚ストの送出元であ る凊理の前蚘優先床を珟状よりも高くするように倉曎するこずが奜たしい。  Further, when the request is transmitted in response to a mishit in the data cache memory, the priority calculation unit sets the priority of the process that is the source of the request to be lower than the current level. It is preferable to change it to be higher.
なお、 圓該情報凊理装眮から倖郚に察するリク゚ストが発生した際に、 該優先 床算出郚が、 該リク゚スト管理郚で管理されおいる圓該リク゚ストの皮別に応じ お、 圓該リク゚ストの送出元である凊理の前蚘優先床を算出/倉曎するこずが奜 たしい。  Note that when a request to the outside is generated from the information processing device, the priority calculation unit determines, based on the type of the request managed by the request management unit, the process of the transmission source of the request. It is preferable to calculate / change the priority.
たた、 圓該リク゚ストが、 該デヌタキャッシュメモリでのミスヒットに䌎っお 送出されたものである堎合、 該優先床算出郚が、 圓該リク゚ストの送出元である 凊理の前蚘優先床を珟状よりも䜎くするように倉曎するこずが奜たしい。  Further, when the request is sent in response to a mishit in the data cache memory, the priority calculation unit lowers the priority of the process that is the source of the request from the current level. It is preferable to change as follows.
なお、 該挔算郚における挔算資源の䜿甚状況を前蚘凊理毎に採取する採取郚を さらにそなえ、 該優先床算出郚が、 該採取郚によっお採取された該挔算資源の䜿 甚状況に応じお、 各凊理の優先床を算出/倉曎するこずが奜たしい。  It is to be noted that the arithmetic unit further includes a sampling unit for sampling the usage status of the computation resources for each of the processes, wherein the priority calculation unit determines each of the processing resources according to the usage status of the computation resources sampled by the sampling unit. It is preferable to calculate / change the processing priority.
さらに、 前蚘 2以䞊の凊理のいずれか䞀぀に぀いお該採取郚によっお採取され た該挔算資源の䜿甚状況ずしおの䜿甚率が所定倀を超えおいる堎合、 該優先床算 出郚が、 圓該凊理の前蚘優先床を珟状よりも䜎くするように倉曎するこずが奜た しい。  Further, when the usage rate as the usage status of the computation resource collected by the collection unit for any one of the two or more processes exceeds a predetermined value, the priority calculation unit may It is preferable to change the priority so as to be lower than the current state.
なお、 前蚘 2以䞊の凊理の実行に䌎い圓該情報凊理装眮から倖郚に察しお送出 されたリク゚ストに関する情報を前蚘凊理毎に管理するリク゚スト管理郚ず、 該 挔算郚における挔算資源の䜿甚状況を前蚘凊理毎に採取する採取郚ずをさらにそ なえ、 該優先床算出郚が、 該リク゚スト管理郚で管理されおいる前蚘リク゚スト に関する情報ず、 該採取郚によ぀お採取された該挔算資源の䜿甚状況ずに応じお、 各凊理の優先床を算出/倉曎するこずが奜たしい。 A request management unit that manages information related to a request transmitted from the information processing apparatus to the outside in accordance with the execution of the two or more processes for each of the processes; A collecting unit that collects information on each of the requests managed by the request managing unit; and a use status of the computation resources collected by the collecting unit. And depending on It is preferable to calculate / change the priority of each process.
たた、 䞻蚘憶デヌタの読出しリク゚ストが前蚘リク゚ストずしお圓該情報凊理 装眮から倖郚に察しお送出された際に、 該優先床算出郚が、 該リク゚スト管理郚 で管理されおいる、 倖郚からの応答埅ち䞭のリク゚ストの数ず、 圓該リク゚スト の送出元である凊理に぀いお該採取郚によっお採取された該挔算資源の䜿甚状況 ずに応じお、 圓該リク゚ストの送出元である凊理の前蚘優先床を算出 z倉曎する こずが奜たしい。  Also, when the read request of the main memory data is sent from the information processing device to the outside as the request, the priority calculation unit is waiting for a response from the outside, which is managed by the request management unit. The priority of the process that is the source of the request is calculated and changed according to the number of requests and the usage status of the processing resource collected by the collection unit for the process that is the source of the request. Is preferred.
たた、 前蚘リク゚ス トの数が所定範囲内にあり、 䞔぀、 圓該リク゚ストの送出 元である凊理に぀いお該採取郚によっお採取された該挔算資源の䜿甚状況ずしお の䜿甚率が所定倀を超えおいる堎合、 該優先床算出郚が、 圓該リク゚ストの送出 元である凊理の前蚘優先床を珟状よりも䜎くするように倉曎するこずが奜たしレ、。 たた、 前蚘リク゚ストの数が所定倀を超えおいる堎合、 該優先床算出郚が、 圓 該リク゚ストの送出元である凊理の前蚘優先床を珟状よりも䜎くするように倉曎 するこずが奜たしい。  In addition, when the number of the requests is within a predetermined range, and the usage rate as the usage status of the operation resources collected by the collection unit for the process from which the request is transmitted exceeds a predetermined value. It is preferable that the priority calculation unit changes the priority of the process that is the transmission source of the request so as to be lower than the current level. Further, when the number of the requests exceeds a predetermined value, it is preferable that the priority calculation unit changes the priority of the process that is the source of the request to be lower than the current level.
なお、 圓該情報凊理装眮においお前蚘 2以䞊の凊理を実行する際に䜿甚される 1以䞊の実行環境ずしおのワヌクロヌドの特性、 もしくは、 ナヌザの芁望に応じ お、 基準倀 前蚘優先床の初期倀 前蚘リク゚ストの数ず比范される前蚘所定倀, 前蚘リク゚ストの数ず比范される前蚘所定範囲 前蚘䜿甚率ず比范される前蚘所 定倀 該優先床算出郚による前蚘優先床の倉曎幅のうちの少なくずも䞀぀ を手 動で操䜜するための操䜜手段をさらにそなえるこずが奜たしい。  The reference value (the initial value of the priority) may be set according to the characteristics of the workload as one or more execution environments used when executing the two or more processes in the information processing device, or according to a user's request. The predetermined value to be compared with the number of requests, the predetermined range to be compared to the number of requests, the predetermined value to be compared to the usage rate, and a change range of the priority by the priority calculation unit. It is preferable to further provide an operation means for manually operating at least one of the above.
たた、 圓該情報凊理装眮においお前蚘 2以䞊の凊理を実行する際に䜿甚される 1以䞊の実行環境ずしおのワヌクロヌドの実行状況ず、 その実行状況に応じた基 準倀 前蚘優先床の初期倀 前蚘リク゚ストの数ず比范される前蚘所定倀 前蚘 リク゚ストの数ず比范される前蚘所定範囲 前蚘䜿甚率ず比范される前蚘所定倀 該優先床算出郚による前蚘優先床の倉曎幅のうちの少なくずも䞀぀ ずの組み合 わせを保持するテヌブルず、 前蚘ワヌクロヌドの実行状況をモニタするモニタ手 段ず、 該モニタ手段によるモニタ結果を受けお該テヌブルを参照し、 前蚘基準倀 を、 該モ゚タ手段によっおモニタされた前蚘ワヌクロヌドの実行状況に応じたも のに動的に倉曎する倉曎手段ずをさらにそなえるこずが奜たしい。 たた、 䞊蚘目的を達成するために、 本発明の呜什凊理制埡装眮は、 䞊述した呜 什ァドレス生成郚, 呜什キダッシュメモリ 呜什バッファ セレクタ デコヌダ, 挔算郚 デヌタキャッシュメモリをそなえ、 2以䞊の凊理を䞊列的に実行する情 報凊理装眮においお、 前蚘 2以䞊の凊理に぀いおの各呜什の実行状態を制埡する 呜什凊理制埡装眮であっお、 該挔算郚における挔算資源の空き時間を削枛するよ うに各凊理の優先床を算出 Z倉曎する優先床算出郚ず、 該優先床算出郚によっお 算出ノ倉曎された各凊理の優先床を参照し、 前蚘優先床の高い凊理に぀いおの呜 什を優先的に遞択しお該デコヌダぞ出力するように該セレクタの動䜜を制埡する 制埡郚ずをそなえたこずを特城ずしおいる。 In addition, the execution status of a workload as one or more execution environments used when executing the two or more processes in the information processing device, and a reference value (an initial value of the priority) according to the execution status. , The predetermined value to be compared with the number of requests, the predetermined range to be compared to the number of requests, the predetermined value to be compared to the usage rate, and a change range of the priority by the priority calculation unit. A table holding a combination of the following: a monitoring means for monitoring the execution status of the workload; and a table obtained by monitoring the monitoring result by the monitoring means, referring to the table, and setting the reference value to: It is preferable to further include a change unit that dynamically changes according to the execution status of the workload monitored by the monitor unit. In order to achieve the above object, an instruction processing control device according to the present invention includes an instruction address generation unit, an instruction cache memory, an instruction buffer, a selector, a decoder, a calculation unit, and a data cache memory. An information processing apparatus for executing processing in parallel, comprising: an instruction processing control apparatus for controlling an execution state of each instruction for the two or more processings, wherein the idle time of operation resources in the operation unit is reduced. Calculate the priority of each process.Refer to the priority calculation unit that changes Z and the priority of each process calculated and changed by the priority calculation unit, and give priority to the instruction for the process with the higher priority. And a control unit for controlling the operation of the selector so as to select and output the data to the decoder.
たた、 䞊蚘目的を達成するために、 本発明の呜什凊理制埡方法は、 䞊述した 2 以䞊の凊理を䞊列的に実行する情報凊理装眮においお、 前蚘 2以䞊の凊理に぀い おの各呜什の実行状態を制埡する呜什凊理制埡方法であっお、 該挔算郚における 挔算資源の空き時間を削枛するように各凊理の優先床を算出 Z倉曎する優先床算 出ステップず、 該優先床算出ステップにおいお算出/倉曎された各凊理の優先床 を参照し、 前蚘優先床の高い凊理に぀いおの呜什を優先的に遞択しお該デコヌダ ぞ出力するように該セレクタの動䜜を制埡する制埡ステップずを含むこずを特城 ずしおいる。  In order to achieve the above object, an instruction processing control method according to the present invention, in an information processing apparatus that executes two or more processes described above in parallel, executes an execution state of each instruction for the two or more processes. An instruction processing control method for controlling, wherein a priority of each processing is calculated so as to reduce an idle time of a processing resource in the processing unit; a priority calculating step of changing Z; and a calculation / change in the priority calculating step And controlling the operation of the selector so as to preferentially select an instruction for the high-priority processing and output the instruction to the decoder with reference to the priority of each processing performed. I have.
たた、 䞊蚘目的を達成するために、 本発明の呜什凊理制埡プログラムは、 䞊述 した 2以䞊の凊理を䞊列的に実行する情報凊理装眮においお、 前蚘 2以䞊の凊理 に぀いおの各呜什の実行状態を制埡する機胜をコンピュヌタに実行させるための 呜什凊理制埡プログラムであっお、 該挔算郚における挔算資源の空き時間を削枛 するように各凊理の優先床を算出/倉曎する優先床算出郚、 および、 該優先床算 出郚によっお算出/倉曎された各凊理の優先床を参照し、 前蚘優先床の高い凊理 に぀いおの呜什を優先的に遞択しお該デコヌダぞ出力するように該セレクタの動 䜜を制埡する制埡郚ずしお、 該コンピュヌタを機胜させるこずを特城ずしおいる。 たた、 䞊蚘目的を達成するために、 本発明の呜什凊理制埡プログラムを蚘録し たコンピュヌタ読取可胜な蚘録媒䜓は、 䞊述した 2以䞊の凊理を䞊列的に実行す る情報凊理装眮においお、 前蚘 2以䞊の凊理に぀いおの各呜什の実行状態を制埡 する機胜をコンピュヌタに実行させるための呜什凊理制埡プログラムを蚘録した コンピュヌタ読取可胜な蚘録媒䜓であっお、 該呜什凊理制埡プログラムが、 該挔 算郚における挔算資源の空き時間を削枛するように各凊理の優先床を算出 z倉曎 する優先床算出郚、 および、 該優先床算出郚によっお算出 Z倉曎された各凊理の 優先床を参照し、 前蚘優先床の高い凊理に぀いおの呜什を優先的に遞択しお該デ コヌダぞ出力するように該セレクタの動䜜を制埡する制埡郚ずしお、 該コンビュ ヌタを機胜させるこずを特城ずしおいる。 図面の簡単な説明 In order to achieve the above object, an instruction processing control program according to the present invention, in an information processing apparatus that executes two or more processes in parallel, controls an execution state of each instruction for the two or more processes. An instruction processing control program for causing a computer to execute a function to perform, the priority calculating unit calculating / changing the priority of each processing so as to reduce the idle time of the processing resources in the processing unit; and The operation of the selector is controlled so as to refer to the priority of each processing calculated / changed by the degree calculation unit and to preferentially select an instruction for the processing with the higher priority and output the instruction to the decoder. The computer is caused to function as a control unit. According to another aspect of the present invention, there is provided an information processing apparatus that executes the above-described two or more processes in parallel. An instruction processing control program for causing a computer to execute the function of controlling the execution state of each instruction for the A computer-readable recording medium, wherein the instruction processing control program calculates and changes the priority of each processing so as to reduce the idle time of the processing resources in the processing section; The operation of the selector is controlled by referring to the priority of each process whose Z has been changed by the priority calculation unit and preferentially selecting an instruction for the process with the higher priority and outputting it to the decoder. It is characterized in that the computer functions as a control unit. Brief Description of Drawings
図 1は本発明の第 1実斜圢態にかかる情報凊理装眮の機胜構成を瀺すプロック 図である。  FIG. 1 is a block diagram illustrating a functional configuration of the information processing apparatus according to the first embodiment of the present invention.
図 2は本発明の第 1実斜圢態にかかる情報凊理装眮におけるリク゚スト管理テ ヌブノレを瀺す図である。  FIG. 2 is a diagram showing a request management table in the information processing apparatus according to the first embodiment of the present invention.
図 3は本発明の第 1実斜圢態にかかる情報凊理装眮における優先床蚘憶テヌプ ルを瀺す図である。  FIG. 3 is a diagram showing a priority storage table in the information processing apparatus according to the first embodiment of the present invention.
図 4は本発明の第 1実斜圢態にかかる情報凊理装眮の優先床算出郚における第 1のタむミングでの優先床倉数の算出手順を説明するためのフロヌチダ䞀トであ る。  FIG. 4 is a flowchart for explaining a procedure of calculating a priority variable at a first timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
図 5は本発明の第 1実斜圢態にかかる情報凊理装眮の優先床算出郚における第 2のタむミングでの優先床倉数の算出手順を説明するためのフロヌチャヌトであ る。  FIG. 5 is a flowchart for explaining a procedure of calculating a priority variable at a second timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
図 6は本発明の第 1実斜圢態にかかる情報凊理装眮の優先床算出郚における第 3のタむミングでの優先床倉数の算出手順を説明するためのフロヌチャヌトであ る。  FIG. 6 is a flowchart for explaining a procedure of calculating a priority variable at a third timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
図 7は本発明の第 1実斜圢態にかかる情報凊理装眮の優先床算出郚における第 4のタむミングでの優先床倉数の算出手順を説明するためのフロヌチャヌトであ る。  FIG. 7 is a flowchart illustrating a procedure of calculating a priority variable at a fourth timing in the priority calculation unit of the information processing apparatus according to the first embodiment of the present invention.
図 8は本発明の第 1実斜圢態にかかる情報凊理装眮の呜什制埡方法の手順を説 明するためのフロヌチダ䞀トである。  FIG. 8 is a flowchart for explaining the procedure of the instruction control method of the information processing apparatus according to the first embodiment of the present invention.
図 9は本発明の第 2実斜圢態にかかる情報凊理装眮の機胜構成を瀺すプロック 図である。 FIG. 9 is a block diagram showing a functional configuration of the information processing apparatus according to the second embodiment of the present invention. FIG.
図 1 0は本発明の第 3実斜圢態にかかる情報凊理装眮の機胜構成を瀺すプロッ ク図である。  FIG. 10 is a block diagram showing a functional configuration of an information processing apparatus according to the third embodiment of the present invention.
図 1 1は本発明の第 3実斜圢態にかかる情報凊理装眮におけるテヌブルを瀺す 図である。  FIG. 11 is a diagram showing a table in the information processing device according to the third embodiment of the present invention.
図 1 2は䞀般的なマルチスレツド方匏を採甚した情報凊理装眮の機胜構成を瀺 すブロック図である。 発明を実斜するための最良の圢態  FIG. 12 is a block diagram showing a functional configuration of an information processing apparatus employing a general multi-thread method. BEST MODE FOR CARRYING OUT THE INVENTION
以䞋、 図面を参照しお本発明の実斜の圢態を説明する。  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
〔1〕 第 1実斜圢態  [1] First embodiment
たず、 本発明の第 1実斜圢態における情報凊理装眮に぀いお説明する。 図 1は 第 1実斜圢態における情報凊理装眮の機胜構成を瀺すプロック図であり、 この図 1に瀺すように、 本発明の第 1実斜圢態にかかる情報凊理装眮は、 図 1 2で瀺し たような䞀般的なマルチスレツド方匏を採甚した情報凊理装眮ず同様の呜什ァド レス生成郚 1 1次呜什キャッシュメモリ 2 , 呜什バッファ 3 , セレクタ 4 , デ コヌダ 5 , 挔算郚 6 , レゞスタ 7 , 1次デヌタキャッシュメモリ 8 2次キダッ シュメモリ 9をそなえるずずもに、 リク゚スト管理郚 1 2 優先床算出郚 1 3 , 制埡郚 1 4 , 採取郚 1 5をさらにそなえお構成されおいる。  First, an information processing device according to the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a functional configuration of the information processing apparatus according to the first embodiment. As shown in FIG. 1, the information processing apparatus according to the first embodiment of the present invention has the same configuration as that shown in FIG. An instruction address generator 1, a primary instruction cache memory 2, an instruction buffer 3, a selector 4, a decoder 5, an arithmetic unit 6, an arithmetic unit 6, registers 7, 1 similar to an information processing device employing a general multi-thread system. A secondary data cache memory 8 and a secondary cache memory 9 are provided, and a request management unit 12, a priority calculation unit 13, a control unit 14, and a sampling unit 15 are further provided.
なお、 図 1䞭、 既述の笊号ず同䞀の笊号は、 同䞀の郚分もしくはほが同䞀の郚 分を瀺しおいるので、 その詳现な説明は省略する。  Note that, in FIG. 1, the same reference numerals as those described above indicate the same or almost the same portions, and thus detailed description thereof will be omitted.
リク゚スト管理郚 1 2は、 倖郚メモリ 1 1に察するむンタヌフェヌスずしお機 胜するものであり、 キャッシュミスが発生した堎合、 リク゚スト管理郚 1 2を介 しお倖郚メモリ 1 1を参照し、 圓該呜什語矀やデヌタがフェッチされる。 この際、 リク゚スト管理郚 1 2は、 キャッシュミスを発生した呜什もしくはデヌタが倖郚 メモリ 1 1を参照するために送出したリク゚ストを管理するため、 送出されたリ ク゚ストに関する情報を䞀時的に蚘憶するリク゚スト管理テヌブル 1 2 aをそな えおいる。 · 図 2に瀺すように、 リク゚スト管理郚 1 2のリク゚スト管理テヌプ^^ 1 2 aで は、 倖郚 即ち、 倖郚メモリ 1 1 ) ぞ送出されたリク゚ス トのリク゚スト I Dに 察応させお、 圓該リク゚ストの送出元である凊理の凊理 I Dず、 圓該リク゚スト の応答埅ちフラグ 圓該リク゚ストに察する応答の有無を瀺すフラグ ず、 リク ゚スト管理テヌブル 1 2 aに圓該リク゚ストのェントリが䜜成された時間ずが保 持されるように構成されおいる。 The request management unit 12 functions as an interface to the external memory 11. When a cache miss occurs, the request management unit 12 refers to the external memory 11 via the request management unit 12, Data is fetched. At this time, the request management unit 12 manages the request transmitted by the instruction or data in which the cache miss has occurred in order to refer to the external memory 11, and temporarily stores the information related to the transmitted request. It has a management table 12a. · As shown in Fig. 2, the request management unit 12 uses the request management tape ^^ 12 a Is associated with the request ID of the request sent to the outside (ie, the external memory 11), the process ID of the process that is the source of the request, and a response waiting flag of the request (the response of the request). (A flag indicating the presence / absence of the request) and the time when the entry of the request is created in the request management table 12a.
ここで、 本実斜圢態の情報凊理装眮においお、 凊理 I Dをそれぞれ 「AJ 「B」 ずする 2぀の凊理が䞊列的に実行されおいるずするず、 図 2に瀺すリクェ ス ト管理郚 1 2のリク゚スト管理テヌブル 1 2 aには、 リク゚スト I D (「1 J 〜 「3 J ) 毎に凊理 I Dずしお 「Aj もしくは 「B」 が蚭定され、 応答埅ちフラ グには、 圓該リク゚ス トが応答埅ち リク゚ス ト送出枈み であれば 「1」、 応 答埅ちでなければ リク゚ス ト未送出 「0」 が蚭定される。 さらに、 リク゚ス ト I D毎に応答埅ちフラグが成立しおからの経過時間を算出するために、 リタ゚ ス ト管理テヌブル 1 2 aに゚ントリが䜜成された時間 「T 1」 〜 「΀ 3」 が蚭 定される。  Here, in the information processing apparatus according to the present embodiment, assuming that two processes whose process IDs are “AJ” and “B” are respectively executed in parallel, the request management unit 12 shown in FIG. In the request management table 12a, "Aj" or "B" is set as the processing ID for each request ID ("1J to" 3J) ", and the response waiting flag indicates that the request is waiting for a response. If no response has been sent, “1” is set. If no response is waiting (request has not been sent), “0” is set. Furthermore, in order to calculate the elapsed time since the response wait flag was established for each request ID, the time when the entry was created in the request management table 12a ("T1" to "΀3") Is set.
たた、 優先床算出郚 1 3は、 リク゚スト管理郚 1 2によっお管理される情報や 挔算郚 6における挔算資源の䜿甚状況 䞊述する採取郚 1 5による採取結果 に 基づいお、 本情報凊理装眮で実行される各凊理 スレッ ド ストランド の優先 床を算出 Ζ倉曎するもので、 凊理毎 ここでは凊理 Α Β毎 に予め蚭定された 優先床倉数 以䞋、 優先床初期倀ずいう を保持するずずもに、 デヌタキダッシ ュミスに関連する状況に応じお䞊蚘優先床初期倀から新たな優先床倉数を算出す る算出郚 1 3 aず、 この算出郚 1 3 aで算出された凊理毎の優先床倉数を蚘憶す る優先床蚘憶テヌブル 1 3 bずをそなえおいる。  Further, the priority calculation unit 13 is configured by the information processing apparatus based on the information managed by the request management unit 12 and the usage status of the calculation resources in the calculation unit 6 (the collection result by the collection unit 15 described above). The priority of each process (thread, strand) to be executed is calculated and changed. A priority variable (hereinafter referred to as a priority initial value) set in advance for each process (here, each process Α, Β) Calculating unit 13a that calculates a new priority variable from the above-mentioned priority initial value according to the situation related to the data cache miss, and the priority for each process calculated by this calculating unit 13a. It has a priority storage table 13b for storing degree variables.
なお、 本実斜圢態においお、 デヌタキャッシュミスに関連する状況ずは、 リク ゚スト管理郚 1 2を介しお倖郚ぞ読み出し 参照 リク゚ストが送出されたタむ ミング 以䞋、 第 1のタむミングずもいう ず、 圓該リク゚ス トに察する応答を リク゚スト管理郚 1 2が受け取ったタむミング 以䞋、 第 2のタむミングずもい う ず、 圓該リク゚ストに察する応答が 1次デヌタキャッシュメモリ 8にェント リされたタむミング (以䞋、 第 3のタむミングずもいう) ず、 デヌタキャッシュ ミスが発生したタむミング 以䞋、 第 4のタむミングずもいう ずのこずを蚀レ、、 優先床算出郚 1 3の算出郚 1 3 aは、 䞊蚘の第 1〜第 4のタむミングで、 圓該リ ク゚ストの送出元である凊理の優先床倉数を、 図 4〜図 7を参照しながら埌述す る手順に埓っお算出するように構成されおいる。 In this embodiment, the situation related to the data cache miss refers to the timing (hereinafter also referred to as the first timing) at which the read (reference) request is sent to the outside via the request management unit 12. The timing at which the request management unit 12 receives a response to the request (hereinafter, also referred to as a second timing) and the timing at which the response to the request is entered into the primary data cache memory 8 (hereinafter, referred to as a third timing). Timing), and the timing at which a data cache miss occurs (hereinafter, also referred to as the fourth timing). The calculating unit 13a of the priority calculating unit 13 converts the priority variable of the process that is the transmission source of the request at the above-described first to fourth timings with reference to FIGS. It is configured to calculate according to the following procedure.
そしお、 図 3に瀺すように、 優先床蚘憶テヌブル 1 3 bでは、 凊理 I D (ここ では、 凊理 A, B ) 毎に優先床倉数 [ P (A) , P (B ) ] を保持するように構成 されおおり、 䞊蚘の第 1〜第 4のタむミングで算出される優先床倉数がその郜床 倉曎 曞き換え され、 各凊理の優先床ずしお垞に最新の算出された優先床倉数 が蚘憶される。  Then, as shown in FIG. 3, in the priority storage table 13b, the priority variables [P (A), P (B)] are stored for each process ID (here, processes A and B). The priority variables calculated at the above-mentioned first to fourth timings are changed (rewritten) each time, and the latest calculated priority variables are always stored as the priority of each process.
たた、 制埡郚 1 4は、 優先床算出郚 1 3の優先床蚘憶テヌブル 1 3 bに蚘憶さ れた各凊理の優先床倉数を参照し、 その優先床倉数に基づいお、 優先床の高い凊 理に぀いおの呜什を優先的に遞択しおデコヌダ 5ぞ出力するようにセレクタ 4の 動䜜を制埡するものである。  Further, the control unit 14 refers to the priority variables of the respective processes stored in the priority storage table 13b of the priority calculation unit 13, and based on the priority variables, executes the process with the higher priority. The operation of the selector 4 is controlled so that an instruction for processing is preferentially selected and output to the decoder 5.
さらに、 採取郚 1 5は、 挔算郚 6における挔算資源の䜿甚状況を凊理毎に採取 するものであり、 採取郚 1 5で採取された挔算資源の䜿甚状況に基づいお、 埌述 する優先床算出郚 1 3における第 1のタむミングでの優先床倉数の算出等が行な われる。  Further, the sampling unit 15 is for sampling the usage status of the computing resources in the arithmetic unit 6 for each process, and based on the usage status of the computing resources sampled in the sampling unit 15, a priority calculation unit described later. Calculation of a priority variable at the first timing in 13 is performed.
ここで、 挔算資源の䜿甚状況ずは、 䟋えば、 呜什りィンドりの゚ントリ䜿甚率, リネヌミングレゞスタの䜿甚率 フェッチポヌトの゚ントリ䜿甚率 リザべヌシ ョンステ䞀ションのェントリ䜿甚率が採取される。  Here, the usage status of the processing resources is, for example, the entry usage rate of the instruction window, the usage rate of the renaming register, the entry usage rate of the fetch port, and the entry usage rate of the reservation station.
なお、 本情報凊理装眮の各機胜のうちの少なくずも優先床算出郚 1 3及び制埡 郚 1 4により、 本発明の呜什凊理制埡装眮ずしおの機胜が実珟される。  The function as the instruction processing control device of the present invention is realized by at least the priority calculation unit 13 and the control unit 14 among the functions of the information processing device.
次に、 図 4〜図 7を参照しながら優先床算出郚 1 3における第 1〜第 4のタむ ミングでの優先床倉数算出手順に぀いお説明する。 なお、 ここでは凊理 Aに぀い お優先床倉数の算出 Z倉曎が行なわれる堎合を説明する。 たた、 各凊理には予め 優先床初期倀が蚭定されおおり、 埌述する優先床倉数の算出ノ倉曎が初めお行な われる堎合は、 この優先床初期倀が珟状の優先床倉数ずしお甚いられるようにな ぀おいる。 なお、 優先床倉数は、 その数倀が小さい皋、 優先床が高いこずずする。 図 4に瀺すフロヌチャヌト ステップ S 1 0〜 S 1 6 ) に埓っお、 優先床算出 郚 1 3における第 1のタむミングでの優先床倉数の算出手川頁に぀いお説明する。 たず、 凊理 Aからの呜什の実行時に䜿甚されるデヌタのキダッシュミスの発生に 応じお、 リク゚スト管理郚 13から倖郚メモリ 1 1の読み出しリク゚ストが送出 されたかどうかが刀断される ステップ S 10)。 なお、 このリク゚ストが送出 されたかどうか 第 1のタむミング は、 リク゚スト管理郚 1 2のリク゚スト管 理テヌブル 12 aにおける応答埅ちフラグに基づいお、 優先床算出郚 1 3の算出 郚 1 3 aが刀断する。 Next, the procedure of calculating the priority variables in the first to fourth timings in the priority calculating unit 13 will be described with reference to FIGS. Here, a case where the calculation Z of the priority variable is changed in the process A will be described. In addition, a priority initial value is set in advance for each process, and when the calculation of the priority variable described later is changed for the first time, the priority initial value is set so as to be used as the current priority variable. It is. The priority variable has a higher priority as its numerical value is smaller. The calculation of the priority variable at the first timing in the priority calculation unit 13 at the first timing will be described with reference to the flowchart (steps S10 to S16) shown in FIG. First, it is determined whether or not a request to read the external memory 11 has been sent from the request management unit 13 in accordance with the occurrence of a cache miss of data used when executing the instruction from the process A (step S10). Whether or not this request has been sent (first timing) is determined by the calculation unit 13a of the priority calculation unit 13 based on the response waiting flag in the request management table 12a of the request management unit 12. to decide.
ここでリク゚ストが送出されおいなければ ステップ S 10の N〇ルヌト、 圓該リク゚ストの送信元ずなる凊理 Aの優先床倉数 P (A) は倉曎されず、 優先 床蚘憶テヌブル 1 3 bに蚘憶された優先床のたたずなる ステップ S 1 1) 1 リク゚ス 1、が送出されたならば (ステップ S 10の YE Sルヌト 第 1のタむミ ング、 そのリク゚ストの送出元である凊理 Aにかかる倖郚 倖郚メモリ 1 1) からの応答埅ち䞭のリク゚スト ぀たり、 圓該リク゚ス トの前に既にリク゚スト 管理テヌプ ^ /レ 1 2 aに゚ントリが䜜られた凊理 Aに぀いおのリク゚スト の数 W ('リク゚スト送出 ·受け取り時に、 カりンタの増枛を実斜するこずで管理された 倀 が所定数 X 1以䞊であり、 䞔぀、 所定数 X 2よりも小さいかどうかが刀断さ れる ステップ S 1 2)。 なお、 X I X 2は適宜蚭定される自然数であり、 リ ク゚スト数 Wは、 リク゚スト管理郚 12のリク゚スト管理テヌブル 12 aに基づ レ、お、 優先床算出郚 1 3の算出郚 1 3 aが刀断する。  If the request has not been sent (N route of step S10), the priority variable P (A) of the process A that is the source of the request is not changed and is stored in the priority storage table 13b. (Step S11) If 1 request 1 is transmitted (YE S route of step S10; first timing), the request is sent to processing A that has transmitted the request. The number of requests waiting for a response from the outside (external memory 11) (that is, the request for process A for which an entry has already been made on the request management tape ^ / le 12a before the request) W ( 'When the request is sent and received, it is determined whether the value managed by increasing / decreasing the counter) is equal to or more than the predetermined number X1 and smaller than the predetermined number X2 (step S12). . Note that XI and X2 are natural numbers that are appropriately set, and the number of requests W is calculated based on the request management table 12a of the request management unit 12, and is calculated by the calculation unit 13a of the priority calculation unit 13. Judge.
ここで、 リク゚スト数 Wが所定数 X 1以䞊 X 2未満の範囲内でなければ ステ ップ S 1 2の N〇ルヌト、 リク゚ス ト数 Wが所定数 X 2以䞊であるかどうかが 刀断され (ステップ S 1 3)、 ここで、 リク゚ス ト数 Wが所定数 X2よりも小さ ければ ステップ S 1 3の NOルヌト  W=X 2)、 凊理 Aの優先床倉数 P (A) は倉曎されず、 優先床蚘憶テヌブル 1 3 bに蚘憶された優先床のたたずな る (ステップ S 1 1)。 しかし、 リク゚スト数 Wが所定数 X 2以䞊であれば ス テツプ S 1 3の YE Sルヌト、 珟状の優先床倉数 P (A) に予め蚭定された補 正数 i 2 (>0) が加えられお凊理 Aの優先床倉数 P (A) が倉曎される ステ ップ S 14)。  Here, if the number of requests W is not within the range of the predetermined number X1 or more and less than X2 (N route of step S12), it is determined whether the request number W is the predetermined number X2 or more. (Step S 13). Here, if the number of requests W is smaller than the predetermined number X 2 (NO route of Step S 13; W = X 2), the priority variable P (A) of the process A becomes The priority is not changed and remains as the priority stored in the priority storage table 13b (step S11). However, if the number of requests W is equal to or more than the predetermined number X 2 (YE S route of step S 13), the correction number i 2 (> 0) preset in the current priority variable P (A) is In addition, the priority variable P (A) of the process A is changed (step S14).
たた、 リク゚ス ト数 Wが所定数 X 1以䞊 X 2未満の範囲内であれば ステップ S 12の YE Sルヌト、 圓該リク゚ス トの送信元である凊理 Aにかかる他の呜 什が、 珟圚、 挔算郚 6の挔算資源を所定倀 Y (䜿甚率 以䞊俟甚しおいるかどう かが刀断される ステップ S 1 5 )。 ここで、 優先床算出郚 1 3の算出郚 1 3 a は、 採取郚 1 5で採取された凊理 Aに぀いおの挔算郚 6の挔算資源の䜿甚状況 (前述した各皮䜿甚率 を甚いお刀断する。 そしお、 凊理 Aの挔算郚 6の挔算資 源の䜿甚率が Yよりも少なければ ステップ S 1 5の N Oルヌト、 凊理 Aの優 先床倉数 P (A) は倉曎されず、 優先床蚘憶テヌブル 1 3 bに蚘憶された優先床 のたたずなる ステップ S 1 1 )。 これずは逆に、 凊理 Aの挔算郚 6の挔算資源 の䜿甚率が γ以䞊であれば ステップ S 1 5の Y E Sルヌト、 珟状の優先床倉 数 P (A) に予め蚭定された捕正数 i 1 (> 0 ) が加えられお凊理 Aの優先床倉 数 P (A) が倉曎される ステップ S 1 6 )。 If the number of requests W is in the range of a predetermined number X1 or more and less than X2 (YE S route in step S12), other instructions related to process A, which is the source of the request, are executed. It is determined whether or not the instruction currently uses the computing resources of the computing unit 6 for a predetermined value Y (usage rate) or more (step S15). Here, the calculation unit 13 a of the priority calculation unit 13 determines using the use status of the calculation resources of the calculation unit 6 for the process A collected by the collection unit 15 (the various usage rates described above). . If the utilization rate of the operation resources of the operation unit 6 of the process A is smaller than Y (NO route in step S15), the priority variable P (A) of the process A is not changed, and the priority is stored. The priority stored in the table 13b remains (step S11). Conversely, if the usage rate of the processing resources of the processing unit 6 of the processing A is equal to or more than γ (YES route in step S15), the trapping set in advance to the current priority variable P (A) is performed. The priority variable P (A) of the process A is changed by adding a positive number i 1 (> 0) (step S 16).
なお、 このように算出された優先床倉数 P (A) は、 その郜床、 優先床算出郚 1 3の優先床蚘憶テヌブル 1 3 bにおいお倉曎される。  The priority variable P (A) calculated in this way is changed in the priority storage table 13b of the priority calculation unit 13 each time.
たた、 挔算郚 6の挔算資源の䜿甚状況ずしお、 䞊述のごずく呜什りィンドりの ゚ントリ䜿甚率 リネヌミングレゞスタの䜿甚率 フェッチポヌトの゚ントリ䜿 甚率 リザべヌシペンステヌションの゚ントリ䜿甚率を甚いる堎合、 優先床算出 郚 1 3における第 1のタむミングでの凊理においお䜿甚される挔算資源の䜿甚状 況ずしお、 䞊蚘 4぀の䜿甚率のうちいずれか䞀぀を採甚し、 その挔算資源に察応 した基準倀 Yを蚭定するこずにより、 挔算資源の䜿甚状況の刀定条件を蚭定しお 刀定凊理 ステップ S 1 5 ) を行なうようにしおもよい。 さらに、 䞊蚘 4぀の挔 算資源の党おを採甚しお刀定条件を蚭定しおもよいし、 これら 4぀の挔算資源の うち少なくずも 1぀の挔算資源がかかる刀定条件をクリァすれば条件成立ずなる ように構成しおもよい。  In addition, as described above, the use status of the instruction window entry, the renaming register, the fetch port entry, and the reservation station entry are used as the operation resources of the operation unit 6 as described above. The priority calculation unit 13 uses one of the above four usage rates as the usage status of the computing resources used in the processing at the first timing, and the reference value corresponding to the computing resource is used. By setting Y, it is also possible to set the condition for judging the usage status of the computational resource and perform the judgment process (step S15). Further, the determination condition may be set by employing all of the above four computing resources, or the condition may be satisfied if at least one of the four computing resources clears such a determination condition. You may comprise.
このように、 優先床算出郚 1 3では、 デヌタキャッシュミスが発生し、 リクェ スト管理郚 1 2を介しお、 かかるデヌタの倖郚メモリ 1 1ぞの読み出しリク゚ス トが送出された際に、 リク゚スト管理郚 1 2のリク゚ス ト管理テヌブル 1 2 aで 管理されおいる圓該リク゚ストの送信元である凊理に぀いおリク゚スト管理テヌ ブル 1 2 aに゚ントリが䜜られたリク゚ストの数 Wに応じお、 圓該リクェス トの 送信元である凊理の優先床倉数 P (A) を算出しお、 既に優先床蚘憶テヌブル 1 3 bに蚘憶されおいた圓該凊理の優先床倉数を倉曎する。 なお、 この倉曎は、 珟 状よりも優先床が䜎くなるように行なわれる。 As described above, in the priority calculation unit 13, when a data cache miss occurs and a request to read such data to the external memory 11 is sent out via the request management unit 12, the request management Regarding the process that is the source of the request managed in the request management table 12a of Part 1 2, according to the number W of requests for which entries have been made in the request management table 12a, the request The priority variable P (A) of the process which is the transmission source is calculated, and the priority variable of the process already stored in the priority storage table 13 b is changed. Note that this change The priority is lower than the priority.
このような倉曎 ステップ S 1 4 ) を行なうこずにより、 デヌタキャッシュミ スが倚く発生しおいる凊理以倖の他の凊理の実行が優先されるこずになり、 挔算 郚 6の挔算資源に空き時間を生じさせるこずを抑制するこずができる。  By performing such a change (step S14), execution of processing other than the processing in which many data cache misses occur is prioritized, and the free time for the processing resources of the processing unit 6 is reduced. Can be suppressed.
たた、 優先床算出郚 1 3では、 採取郚 1 5によっお採取された挔算郚 6の挔算 資源の䜿甚状況 䜿甚率 に応じお、 圓該リク゚ストの送信元である凊理の優先 床倉数を算出しお、 既に優先床蚘憶テヌブル 1 3 bに蚘憶されおいた圓該凊理の 優先床倉数を倉曎する。 なお、 この倉曎も、 珟状よりも優先床が䜎くなるように 行なわれる。  In addition, the priority calculation unit 13 calculates the priority variable of the process that is the transmission source of the request in accordance with the usage status (usage rate) of the calculation resource of the calculation unit 6 collected by the collection unit 15. Then, the priority variable of the process that has already been stored in the priority storage table 13 b is changed. This change is also made so that the priority is lower than the current status.
このような倉曎 (ステップ S 1 6 ) を行なうこずにより、 䜿甚率の高い凊理以 倖の他の凊理の実行が優先されるこずになり、 耇数の凊理 ここでは凊理 A B ) による挔算郚 6の挔算資源の䜿甚バランスを保぀こずができ、 効率良く耇数 の凊理を実行させるこずができる。  By making such a change (step S16), the execution of other processings other than the processing with a high usage rate is given priority, and the arithmetic unit by a plurality of processings (here, processings A and B) is executed. The use balance of the computing resources of No. 6 can be maintained, and a plurality of processes can be executed efficiently.
次に、 図 5に瀺すフロヌチャヌト ステップ S 2 0〜S 2 2 ) に埓っお、 優先 床算出郚 1 3における第 2のタむミングでの優先床倉数の算出手順に぀いお説明 する。 ここでは、 リク゚スト管理郚 1 2を介しお倖郚 倖郚メモリ 1 1 ) ぞ送出 した凊理 Aに぀いおのリク゚ストが倖郚からリク゚スト管理郚 1 2ぞ戻っおきた 際に 第 2のタむミング、 この倖郚から受け取った応答が、 凊理 Aで発生した デヌタキャッシュミスに起因するものであり、 か぀、 倖郚からの応答埅ち䞭の凊 理 Aで発生したデヌタキャッシュミスに起因する党おのリク゚ストの䞭で最も叀 いものであるかどうかが刀断される ステップ S 2 0 )。  Next, the calculation procedure of the priority variable at the second timing in the priority calculation unit 13 will be described with reference to the flowchart (steps S20 to S22) shown in FIG. Here, when the request for process A sent to the outside (external memory 11) via the request management unit 12 returns to the request management unit 12 from outside (second timing), The received response is due to a data cache miss that occurred in process A, and is the oldest of all requests due to a data cache miss that occurred in process A while waiting for an external response. Is determined (step S20).
ここで、 リク゚スト管理郚 1 2が倖郚メモリ 1 1からの応答を受け取ったタむ ミング 第 2のタむミング は、 応答の受け取りに䌎い、 リク゚スト管理郚 1 2 のリク゚スト管理テヌブル 1 2 aの゚ントリが無効化されるタむミングであり、 このずきに優先床算出郚 1 3に信号が送られるこずで把握するこずができる。 た た、 圓該リク゚ストの履歎 最も叀いものであるか吊か に぀いおは、 リク゚ス ト管理テヌブル 1 2 aにおけるェントリが䜜成された時間に基づいお優先床算出 郚 1 3の算出郚 1 3 aが刀断する。  Here, when the request management unit 12 receives the response from the external memory 11 (second timing), the entry of the request management table 12 a of the request management unit 12 becomes This is the timing of invalidation, which can be grasped by sending a signal to the priority calculation unit 13 at this time. The history of the request (whether it is the oldest or not) is calculated by the calculation unit 13a of the priority calculation unit 13 based on the time when the entry was created in the request management table 12a. to decide.
そしお、 倖郚から受け取った応答が、 凊理 Aで発生したデヌタキャッシュミス に起因し、 か぀、 かかる凊理 Aに起因するデヌタキャッシュミスの応答埅ち䞭の 党おのリク゚ストの䞭で最も叀いものであれば ステップ S 2 0の Y E Sルヌ ト、 珟状の優先床倉数 P (A) から予め蚭定された補正数 i 3 ( > 0 ) が枛じ られお、 凊理 Aの優先床倉数 P (A) が倉曎される ステップ S 2 1 )。 これず は逆に、 倖郚から受け取った応答が、 凊理 Aで発生したデヌタキャッシュミスに 起因したものではない、 もしくは、 かかる凊理 Aに起因するデヌタキャッシュミ スの応答埅ち䞭の党おのリク゚ストの䞭で最も叀いものでなければ ステップ S 2 0の N Oルヌト、 凊理 Aの優先床倉数 P (A) は倉曎されず、 優先床蚘憶テ 䞀プル 1 3 bに蚘憶された珟状の優先床のたたずなる ステップ S 2 2 )。 The response received from the outside is the data cache miss that occurred in process A. If the request is the oldest of all the requests waiting for the response to the data cache miss caused by the process A (YES route in step S20), the current priority variable P ( The preset correction number i 3 (> 0) is subtracted from A), and the priority variable P (A) of the process A is changed (step S 21). Conversely, the response received from the outside is not due to the data cache miss that occurred in process A, or is included in all requests that are waiting for a data cache miss response due to process A. If it is not the oldest (NO route of step S20), the priority variable P (A) of the process A is not changed, and the current priority stored in the priority storage template 13b is not changed. (Step S22).
このように、 ある凊理の実行に䌎っお送出されたデヌタキャッシュミスに起因 するリク゚ストに察する応答をリク゚スト管理郚 1 2においお受け取った際に、 優先床算出郚 1 3の算出郚 1 3 aがリク゚スト管理郚 1 2で管理されおいる圓該 リク゚ストの履歎に応じお、 圓該リク゚ストの送信元である凊理の優先床倉数を 算出しお、 既に優先床蚘憶テヌプに蚘憶されおいた圓該凊理の優先床倉数を倉曎 する。 なお、 この倉曎は、 珟状よりも優先床が高くなるように行なわれる。 このような倉曎 (ステップ S 2 1 ) を行なうこずにより、 デヌタキャッシュミ スにより停止されおいた呜什の䞭で最も叀レ、呜什の送出元である凊理が優先的に 実行されるこずになり、 かかる凊理の実行がスムヌズに行なわれる。  As described above, when the request management unit 12 receives a response to a request resulting from a data cache miss sent in connection with the execution of a certain process, the calculation unit 13 a of the priority calculation unit 13 performs request management. The priority variable of the process that is the source of the request is calculated in accordance with the history of the request managed by the unit 12, and the priority variable of the process already stored on the priority storage tape is calculated. change. This change is made so that the priority is higher than the current status. By performing such a change (step S 21), the process which is the oldest instruction among the instructions stopped by the data cache miss and the source of the instruction is executed with priority. The execution of such processing is performed smoothly.
なお、 本実斜圢態では、 倖郚から受け取った応答がかかる凊理のデヌタキダッ シュミスに起因した党おの応答埅ち䞭のリク゚ストの䞭で最も叀いものである堎 合にのみ、 優先床を高めるようにしたが、 最も叀いものでなく、 受け取った応答 がある皋床叀いものであれば優先床を高めるように構成しおもよい。  In the present embodiment, the priority is increased only when the response received from the outside is the oldest of all the requests waiting for a response due to the data cache miss of the process. If the response received is not the oldest but the response received is somehow old, the priority may be increased.
次に、 図 6に瀺すフロヌチャヌト ステップ S 3 0〜S 3 2 ) に埓っお、 優先 床算出郚 1 3における第 3のタむミングでの優先床倉数の算出手順に぀いお説明 する。 ここでは、 倖郚から受け取った応答が凊理 Aに䌎っお発生したデヌタキダ ッシュミスに基づいお送出されたリク゚ストに察するものであった堎合に、 この 応答が 1次デヌタキャッシュメモリ 8に゚ントリされたかどうかが刀断され ス テツプ S 3 0 )、 ここで、 この応答が 1次デヌタキャッシュメモリ 8に゚ントリ されたず刀断されれば ステップ S 3 0の Y E Sルヌト 第 3のタむミング、 珟状の優先床倉数 P (A) に予め蚭定された補正数 i 4 (> 0 ) が枛じられお凊 理 Aの優先床倉数 P (A) が倉曎される ステップ S 3 1 )。 これずは逆に、 こ の応答が 1次デヌタキャッシュメモリ 8に゚ントリされたず刀断されなければ (ステップ S 3 0の N Oルヌト、 凊理 Aの優先床倉数 P (A) は倉曎されず、 優先床蚘憶テヌブル 1 3 bに蚘憶された優先床のたたずなる ステップ S 3 2 )。 このように、 ある凊理の実行に䌎っお送出されたリク゚ストに察する応答が 1 次デヌタキャッシュメモリ 8に゚ントリされた際に、 圓該応答が、 リク゚スト管 理郹 1 2で管理されおいる圓該リク゚ストに察する応答であった堎合、 即ち、 圓 該リク゚ストの皮別が、 倖郚メモリ 1 1ぞのデヌタの読み出しであった堎合、 圓 該リク゚ストの送信元である凊理の優先床倉数を算出しお、 既に優先床蚘憶テヌ ブに蚘憶されおいた圓該凊理の優先床倉数を倉曎する。 なお、 この倉曎は、 珟状 よりも優先床が高くなるように行なわれる。 Next, the procedure of calculating the priority variable at the third timing in the priority calculation unit 13 will be described with reference to the flowchart (steps S30 to S32) shown in FIG. Here, if the response received from the outside is for the request sent based on the data cache miss that occurred in process A, it is determined whether this response was entered in the primary data cache memory 8. (Step S30) If it is determined that this response has been entered in the primary data cache memory 8 (YES route of step S30; third timing), The correction number i 4 (> 0) preset for the current priority variable P (A) is reduced, and the priority variable P (A) of the process A is changed (step S31). Conversely, if it is not determined that this response has been entered in the primary data cache memory 8 (NO route in step S30), the priority variable P (A) of the process A is not changed, and the priority is not changed. The priority stored in the degree storage table 13b remains (step S32). As described above, when a response to a request sent in accordance with execution of a certain process is entered in the primary data cache memory 8, the response is a response to the request managed by the request management unit 12. In other words, if the type of the request is reading of data to the external memory 11, the priority variable of the process that is the transmission source of the request is calculated, and the priority is already stored. Change the priority variable of the process stored in the table. This change is made so that the priority is higher than the current status.
このような倉曎 ステップ S 3 1 ) を行なうこずにより、 デヌタキャッシュミ スにより停止されおいた呜什が実行されるようになる段階で優先床が高く蚭定さ れ、 デヌタキャッシュミスにより停止されおいた呜什の送出元である凊理に属す る呜什が優先的にデコヌダに送られ、 実行がスム䞀ズに行なわれる。  By performing such a change (step S31), the priority is set high when the instruction stopped by the data cache miss is executed, and the instruction is stopped by the data cache miss. The instruction belonging to the process from which the instruction is sent is preferentially sent to the decoder, and the execution is performed smoothly.
次に、 図 7に瀺すフロヌチャヌト ステップ S 4 0〜S 4 2 ) に埓っお、 優先 床算出郚 1 3における第 4のタむミングでの優先床倉数の算出手順に぀いお説明 する。 ここでは、 凊理 Aの実行に䌎っおデヌタキャッシュミスが発生したかどう かが刀断され (ステップ S 4 0 )、 デヌタキャッシュミスが発生したならば (ス テツプ S 4 0の Y E Sルヌト 第 4のタむミング、 珟状の優先床倉数 P (A) に予め蚭定された捕正数 i 5 (> 0 ) が加えられお凊理 Aの優先床倉数 P (A) が倉曎される (ステップ S 4 1 )。 これずは逆に、 デヌタキャッシュミスが発生 しおいなければ ステップ S 4 0の N〇ルヌト、 凊理 Aの優先床倉数 P (A) は倉曎されず、 優先床蚘憶テヌブル 1 3 bに蚘憶された珟状の優先床のたたずな る ステップ S 4 2 )。  Next, the procedure of calculating the priority variable at the fourth timing in the priority calculation unit 13 will be described with reference to the flowchart (steps S40 to S42) shown in FIG. Here, it is determined whether or not a data cache miss has occurred along with the execution of the process A (step S40). If a data cache miss has occurred (YES route in step S40; Timing), a preset capture number i 5 (> 0) is added to the current priority variable P (A), and the priority variable P (A) of the process A is changed (step S41). . Conversely, if a data cache miss has not occurred (N route of step S40), the priority variable P (A) of the process A is not changed and is stored in the priority storage table 13b. The current priority set remains (step S42).
このように、 デヌタキャッシュミスが発生した際に、 優先床算出郚 1 3が圓該 デヌタキャッシュミスの発生元である凊理の優先床倉数を算出しお、 既に優先床 蚘憶テヌプに蚘憶されおいた圓該凊理の優先床倉数を倉曎する。 なお、 この倉曎 は、 珟状よりも優先床が䜎くなるように行なわれる。 In this way, when a data cache miss occurs, the priority calculation unit 13 calculates the priority variable of the process that is the source of the data cache miss, and calculates the priority variable that has already been stored in the priority storage tape. Change the processing priority variable. This change Is done so that the priority is lower than the current status.
このような倉曎 ステップ S 4 1 ) を行なうこずにより、 デヌタキャッシュミ スの発生した凊理以倖の他の凊理の実行が優先されるこずになり、 挔算郚 6の挔 算資源に空き時間を生じさせるこずを抑制するこずができる。  By making such a change (step S41), execution of processing other than the processing in which the data cache miss occurred is given priority, and free time is generated in the operation resources of the arithmetic unit 6. Can be suppressed.
以䞊のように、 優先床算出郚 1 3の算出郚 1 3 aにおいお、 䞊述した第 1〜第 4のタむミングで、 それぞれ独立しお優先床倉数の算出/倉曎が行なわれ、 その 算出結果が、 その郜床、 優先床算出郚 1 3の優先床蚘憶テヌブル 1 3 bに蚘憶さ れる。 なお、 優先床算出郚 1 3においお凊理 Bに぀いおも凊理 Aず同様に優先床 倉数の算出 Z倉曎が行なわれる。  As described above, in the calculation unit 13 a of the priority calculation unit 13, the priority variables are independently calculated / changed at the above-described first to fourth timings, and the calculation results are Each time, it is stored in the priority storage table 13b of the priority calculation unit 13. In the priority calculation unit 13, the calculation Z of the priority variable is changed for the process B as in the process A.
次に、 図 8に瀺すフロヌチャヌト ステップ S 5 0 , S 5 1 ) に埓っお、 本実 斜圢態の情報凊理装眮における、 呜什凊理制埡方法の手順に぀いお説明する。 こ の図 8に瀺すように、 本実斜圢態の情報凊理装眮では、 優先床算出郚 1 3におい お各凊理の優先床を算出する優先床算出ステップ S 5 0ず、 制埡郚 1 4が、 優先 床算出ステップ S 5 0で算出/倉曎された各凊理の優先床を参照し、 優先床の高 い凊理に぀いおの呜什を優先的に遞択しおデコヌダ 5ぞ出力するようにセレクタ 4の動䜜を制埡する制埡ステップ S 5 1ずによっお呜什凊理制埡が行なわれる。 優先床算出ステップ S 5 0では、 優先床算出郚 1 3においお、 図 4〜図 7を参 照しながら䞊述した手順で、 各凊理の優先床が算出/倉曎される。 ここで、 優先 床算出ステップ S 5 0の凊理ステップ数が倚い堎合には、 䟝存関係をもたない凊 理を䞊列に実行するこずが考えられ、 さらに、 䞀぀の凊理が耇雑で 1クロックサ ィクルに収たらない堎合にはパむプラむン化するこずが考えられる。 このように しお、 優先床算出ステップ S 5 0が、 挔算噚のクロックサむクルに関しおボルト ネックにならないように考慮する。 たた、 制埡ステップ S 5 1では、 制埡郚 1 4 力 セレクタ 4を制埡し、 呜什バッファ 3に保持されおいる呜什のうち、 優先床 の高い凊理を優先床算出郚 1 3の優先床蚘憶テヌブル 1 3 bに蚘憶された凊理 A, Bの優先床倉数に基づいお、 各凊理の優先床倉数を比范し優先床の高い方の凊理 に぀いおの呜什を優先的に遞択しお、 デコヌダ 5ぞ最倧で 4぀の呜什を出力させ る。  Next, the procedure of the instruction processing control method in the information processing apparatus of the present embodiment will be described with reference to the flowchart (steps S50, S51) shown in FIG. As shown in FIG. 8, in the information processing apparatus according to the present embodiment, the priority calculation step S50 for calculating the priority of each process in the priority calculation unit 13 and the control unit 14 include a priority calculation step. Degree calculation step Controls the operation of selector 4 so as to refer to the priority of each processing calculated / changed in S50 and preferentially select the instruction for the processing with higher priority and output it to decoder 5. The instruction processing control is performed by the control step S51. In the priority calculation step S50, the priority of each process is calculated / changed in the priority calculation unit 13 in the procedure described above with reference to FIGS. Here, when the number of processing steps of the priority calculation step S50 is large, it is conceivable to execute processing having no dependency in parallel, and furthermore, one processing is complicated and one clock cycle is required. If it does not fit, a pipeline may be considered. In this way, the priority calculation step S50 is considered so as not to become a volt-neck for the clock cycle of the arithmetic unit. Further, in the control step S 51, the control unit 14 controls the power selector 4, and among the instructions held in the instruction buffer 3, the high-priority processing is performed by the priority storage table 1 of the priority calculation unit 13. 3 Based on the priority variables of processes A and B stored in b, compare the priority variables of each process, select the instruction for the process with the higher priority first, and send it to the decoder 5 at most. Outputs four instructions.
なお、 呜什バッファ 3に優先床の高い凊理の呜什が存圚しない堎合には、 次に 優先床の高い凊理に属する呜什が遞択される。 たた、 呜什バッファ 3からデコヌ ダ 5ぞ送られる呜什の数がデコヌダ数 ここでは 4぀ よりも少ない堎合には、 優先床の高い順に次々ず各凊理の呜什が遞択されおデコヌダ 5ぞ送られる。 この 堎合、 1぀のサむクルに耇数の凊理の呜什がデコヌドされるこずになる。 If there is no high-priority processing instruction in instruction buffer 3, An instruction belonging to a process with a higher priority is selected. If the number of instructions sent from the instruction buffer 3 to the decoder 5 is smaller than the number of decoders (here, four), instructions for each processing are selected one after another in descending order of priority and sent to the decoder 5. Can be In this case, multiple processing instructions are decoded in one cycle.
このずき、 制埡郚 1 4は、 セレクタ 4がデコヌダ 5ぞ呜什を出力する所定呚期 に 1回䜜動しお、 凊理を切り替えるように構成されおいる。 これは、 セレクタ 4 がデコヌダ 5ぞ呜什を出力する呚期毎に制埡郚 1 4を䜜動させお、 優先床に基づ いお凊理を切り替えるず、 凊理の切り替えにかかるコストが高くな぀おしたい、 かえっおスルヌプットの向䞊に支障をきたしおしたうからである。  At this time, the control unit 14 is configured to operate once in a predetermined period in which the selector 4 outputs an instruction to the decoder 5 to switch processing. This is because if the control unit 14 is activated every time the selector 4 outputs an instruction to the decoder 5 and the processing is switched based on the priority, the cost of switching the processing is increased, and the throughput is rather increased. This will hinder the improvement of the quality.
たた、 このずき、 制埡郚 1 4がセレクタ 4がデコヌダ 5ぞ呜什を出力する呚期 毎に、 優先床算出郚 1 3の優先床蚘憶テヌブル 1 3 bに蚘憶された凊理 A Bの 優先床倉数を比范し、 凊理 Aず凊理 Bずの優先床倉数の差が予め蚭定された閟倀 以䞊の堎合には、 優先床の高い方の凊理の呜什を優先的に遞択しおデコヌダ 5ぞ 出力させるように構成しおもよい。 これにより、 䞊蚘の凊理の切り替えにかかる コスト向䞊が抑制されるずずもに、 効率的に凊理を切り替えるこずができるため. スルヌプットを確実に向䞊させるこずができる。 .  At this time, the control unit 14 sets the priority variables of the processes A and B stored in the priority storage table 13 b of the priority calculation unit 13 every cycle in which the selector 4 outputs the instruction to the decoder 5. If the difference between the priority variables of the processing A and the processing B is equal to or larger than a preset threshold value, the instruction of the processing with the higher priority is preferentially selected and output to the decoder 5. May be configured. As a result, the cost increase associated with the above-described process switching is suppressed, and the process can be switched efficiently, so that the throughput can be reliably improved. .
このように、 本発明の第 1実斜圢態ずしおの情報凊理装眮によれば、 キダッシ ュミスによる倖郚メモリ 1 1の読み出しリク゚ストの総数、 挔算郚 6の挔算資源 の䜿甚状況 第 1のタむミング、 デヌタキャッシュミスによる読み出しリクェ スト送出からの経過時間 第 2のタむミング、 デヌタキャッシュミスによる読 み出しリク゚ストの応答の有無 第 3のタむミング、 デヌタキャッシュミスの 発生の有無 第 4のタむミング に応じお、 各凊理の優先床が算出 Z倉曎され、 この優先床に基づいお呜什バッファ 3に保持された呜什がデコヌダ 5ぞ出力され お挔算郚 6においお実行されるため、 実際の呜什実行状況に応じお挔算郚 6の挔 算資源が耇数の凊理で効率的に䜿甚されるこずになり、 挔算資源に空き時間が発 生するこずが確実に抑制されお、 スルヌプットが倧幅に向䞊される。  As described above, according to the information processing apparatus as the first embodiment of the present invention, the total number of read requests of the external memory 11 due to a cache miss, the usage status (first timing) of the operation resources of the operation unit 6, the data Elapsed time from sending read request due to cache miss (second timing), response to read request due to data cache miss (third timing), occurrence of data cache miss (fourth timing) The priority of each process is calculated according to the Z. The instruction held in the instruction buffer 3 is output to the decoder 5 based on the priority and is executed in the arithmetic unit 6, so that the actual instruction execution status is changed. In this case, the computing resources of the computing unit 6 are used efficiently in a plurality of processes, and it is ensured that free time is generated in the computing resources. Indeed, the throughput is greatly improved.
なお、 本実斜圢態では、 優先床算出郚 1 3においお第 1〜第 4のタむミングで 優先床倉数を算出するように構成したが、 かかる凊理の優先床を高める凊理であ る第 2のタむミング及び第 3のタむミングでの算出は、 いずれか䞀方を行なうよ うに構成しおもよい。 In the present embodiment, the priority calculation unit 13 is configured to calculate the priority variables at the first to fourth timings. For the calculation at the third timing, either It may be configured as follows.
〔2〕 第 2実斜圢態  [2] Second embodiment
次に、 本発明の第 2実斜圢態における情報凊理装眮に぀いお説明する。 図 9は 第 2実斜圢態における情報凊理装眮の機胜構成を瀺すプロック図である。 なお、 図 9䞭、 既述の笊号ず同䞀の笊号は、 同䞀の郚分もしくはほが同䞀の郚分を瀺し おいるので、 その詳现な説明は省略する。  Next, an information processing device according to a second embodiment of the present invention will be described. FIG. 9 is a block diagram illustrating a functional configuration of the information processing apparatus according to the second embodiment. Note that, in FIG. 9, the same reference numerals as those described above indicate the same or almost the same portions, and thus detailed description thereof will be omitted.
図 9に瀺すように、 本発明の第 2実斜圢態にかかる情報凊理装眮は、 䞊蚘の第 1実斜圢態の情報凊理装眮ず同様の構成に加えお、 さらに操䜜手段 1 6 モニタ 手段 1 8 衚瀺手段 2 0をそなえお構成されおいる。  As shown in FIG. 9, the information processing apparatus according to the second embodiment of the present invention has the same configuration as the information processing apparatus of the above-described first embodiment, and further includes operation means 16, monitor means 18, It is provided with display means 20.
操䜜手段 1 6は、 ある凊理の実行環境ずしおのワヌクロヌドの特性、 もしくは. ある特定の凊理の優先床を決定するための倀 基準倀ずもいう を、 手動で操䜜 するものである。  The operation means 16 is for manually operating the characteristic of the workload as the execution environment of a certain process or the value (also referred to as a reference value) for determining the priority of a certain process.
たた、 モニタ手段 1 8は、 本情報凊理装眮で実行されおいる凊理毎のワヌク口 䞀ドの実行状況をモニタするものであり、 具䜓的には、 各凊理の挔算資源の䜿甚 状況 キャッシュメモリの䜿甚状況等かかる情報凊理装眮の各機胜の䜿甚状況を モニタしおいる。 たた、 衚瀺手段 2 0は、 モニタ手段 1 8でモニタされた各凊理 のワヌクロヌドの実行状況を本情報凊理装眮に接続されたモニタ等に衚瀺するも のである。  The monitoring means 18 is for monitoring the execution status of the work module for each process executed by the information processing apparatus. The usage status of each function of the information processing device such as the usage status of the information processing device is monitored. The display means 20 displays the execution status of the workload of each process monitored by the monitor means 18 on a monitor or the like connected to the information processing apparatus.
ここで、 ある特定の凊理の優先床を決定するための倀 基準倀 ずは、 具䜓的 には、 優先床算出郚 1 3の算出郚 1 3 aで最初にかかる凊理の優先床を算出する 際に䜿甚される優先床初期倀、 䞊びに、 第 1〜第 4のタむミングで優先床を算出 するために䜿甚される所定倀 X 1 X 2 , Y、 及び、 補正数 i l〜i 5のこずを いう。  Here, the value (reference value) for determining the priority of a specific process is, specifically, the calculation unit 13a of the priority calculation unit 13 calculates the priority of the process first applied. Priority values used in the calculation, and predetermined values X1, X2, Y, and correction numbers il to i5 used to calculate the priority at the first to fourth timings. That means.
本実斜圢態の情報凊理装眮においお、 凊理 Aず凊理 Bずが䞊列的に実行されお いる堎合に、 かかる情報凊理装眮を䜿甚しおいるナヌザが凊理 Aに぀いお優先的 に実行したい堎合には、 操䜜手段 1 6を操䜜しお、 優先床算出郚 1 3においお保 持され䜿甚されおいる基準倀を凊理 Aの優先床倉数が䜎くなるように倉曎するこ ずにより、 凊理 Aの優先床を盞察的に高めお、 凊理 Aに぀いおの呜什が優先的に デコヌダ 5ぞ出力されお実行されるように操䜜するこずができる。 なお、 操䜜手 段 1 6は、 キヌボヌド マりス等のハヌドりェアず、 このハヌドりェアを操䜜す るこずによっお入力された情報 数倀等 を算出郚 1 3 aで䜿甚される倀に反映 させる゜フトり゚アずを含むマンマシンィンタヌフェヌスである。 In the information processing apparatus of the present embodiment, when the processing A and the processing B are executed in parallel, and the user using the information processing apparatus wants to execute the processing A with priority, the operation By operating the means 16 to change the reference value held and used in the priority calculating section 13 so that the priority variable of the processing A becomes lower, the priority of the processing A is made relative. The instruction for the process A can be preferentially output to the decoder 5 and executed. The operation hand Step 16 includes hardware such as a keyboard and a mouse, and software for reflecting information (numerical values and the like) input by operating the hardware to values used in the calculator 13a. It is a man machine interface.
具䜓的には、 以䞋の 1 ) 〜 5 ) の操䜜を行なうこずにより、 凊理 Aの優先 床を高めるようにするこずができる。  Specifically, by performing the following operations (1) to (5), the priority of the process A can be increased.
( 1 ) 凊理 Aの優先床初期倀を他の凊理 Bの優先床初期倀よりも小さくする。 これにより、 凊理 Aの優先床倉数を盞察的に小さくしお、 凊理 Aの優先床を高 めるこずができる。  (1) The priority initial value of the process A is made smaller than the priority initial values of the other processes B. As a result, the priority variable of the process A can be relatively reduced, and the priority of the process A can be increased.
( 2 ) 第 1のタむミングで䜿甚される X I X 2 (図 4䞭ステップ S 1 2 , ス テツプ S 1 3参照 の倀を倧きくする。  (2) Increase the values of XI and X2 (see steps S12 and S13 in Fig. 4) used at the first timing.
これにより、 キャッシュミスの発生が倚くな぀おも、 優先床倉数が倧きくなる ように倉曎されお優先床が䜎くされるこずがないようにするこずができる。  As a result, even if the number of occurrences of cache misses increases, it is possible to prevent the priority variable from being changed to be large and the priority from being lowered.
( 3 ) 第 1のタむミングで䜿甚される Y (図 4䞭ステップ S 1 5参照 の倀を 倧きくする。  (3) Increase the value of Y (see step S15 in Fig. 4) used at the first timing.
これにより、 凊理 Aにかかる呜什が倚くの挔算資源を利甚しおいる堎合でも、 優先床倉数が倧きくなるように倉曎されお優先床が䜎くされるこずがないように するこずができる。  As a result, even when the instruction related to the process A uses a large amount of computational resources, it is possible to prevent the priority variable from being changed to be large and the priority from being lowered.
( 4 ) 優先床算出郚 1 3においお、 凊理 Aの優先床倉数算出に䜿甚される捕正 倀 i l i 2 i 5の倀を小さくする。  (4) In the priority calculation unit 13, the values of the correction values i l, i 2, and i 5 used for calculating the priority variable of the process A are reduced.
これにより、 第 1及び第 4のタむミングで優先床を䜎める倉曎をする際に、 他 の凊理 Bに察しお凊理 Aの優先床が䞋がらないようにするこずができる。  Thus, when the priority is lowered at the first and fourth timings, it is possible to prevent the priority of the process A from being lowered with respect to the other process B.
( 5 ) 優先床算出郚 1 3においお、 凊理 Aの優先床倉数算出に䜿甚される補正 倀 i 3 i 4の倀を倧きくする。  (5) The priority calculation unit 13 increases the values of the correction values i3 and i4 used for calculating the priority variable of the process A.
これにより、 第 2及び第 3のタむミングで優先床を高める倉曎をする際に、 他 の凊理 Bに察しお凊理 Aの優先床がより高くなるようにするこずができる。 なお、 䞊蚘 1 ) 〜 5 ) の操䜜手段 1 6による基準倀の倉曎においお、 その 倉曎幅に぀いおもナヌザが自由に操䜜するこずができる。  Thereby, when the priority is changed at the second and third timings, the priority of the process A can be made higher than that of the other process B. In addition, when the reference value is changed by the operation means 16 in the above (1) to (5), the user can freely operate the change width.
図 1 2に瀺したような䞀般的なマルチスレツド方匏を採甚した情報凊理装眮で は、 力かる情報凊理装眮を䜿甚するナヌザが耇数の凊理が䞊列的に実行されおい る䞭で、 特定の凊理を優先的に実行したい堎合が発生しおも、.各凊理のワヌク口 䞀ド特性は操䜜できるものではないため、 特定の凊理を優先させるこずはできず、 ナヌザの意思を反映させるこずができない。 し力 しながら、 本発明の第 2実斜圢 態にかかる情報凊理装眮によれば、 操䜜手段 1 6により、 優先床算出郚 1 3にお いお優先床を算出/倉曎するのに䜿甚される基準倀を、 特定の凊理の優先床を高 くするように操䜜するこずができるので、 その特定の凊理を優先的に実行させる こずができ、 ナヌザの意思を反映させるこずができる。 In an information processing device employing a general multi-thread method as shown in FIG. 12, a user who uses a powerful information processing device executes a plurality of processes in parallel. Even if there is a case in which a particular process is to be executed with priority, the specific process cannot be prioritized because the work mode characteristics of each process cannot be operated. I can't reflect my will. However, according to the information processing apparatus according to the second embodiment of the present invention, the operating unit 16 uses the criteria used to calculate / change the priority in the priority calculating unit 13. Since the value can be manipulated so that the priority of a specific process is made higher, the specific process can be executed with priority and the user's intention can be reflected.
なお、 ナヌザが凊理 Aを優先的に実行したい堎合に、 凊理 Bにかかる基準倀を 䞊蚘 1 ) 〜 5 ) の操䜜ずは逆の操䜜を行なうこずにより、 凊理 Bの優先床を 盞察的に䜎くしお、 凊理 Aが優先的に実行されるように操䜜しおもよい。  When the user prefers to execute the process A, the reference value for the process B is set to the relative value of the priority of the process B by performing the operation reverse to the above operations (1) to (5). May be set so that process A is executed with priority.
たた、 本情報凊理装眮では、 モニタ手段 1 8によっお、 凊理毎のワヌクロヌド の実行状況がモニタされ、 そのモニタ結果が衚瀺手段 2 0により、 モニタ等に衚 瀺されるため、 ナヌザは、 凊理毎のワヌクロヌドの実行状況を芖認するこずがで きる。 したがっお、 ナヌザは、 凊理毎のワヌクロヌドの実行状況を認識した䞊で、 操䜜手段 1 6により優先床算出郚 1 3においお優先床を算出/倉曎するのに䜿甚 される基準倀を操䜜するこずができ、 凊理毎のワヌクロヌドの実況状況に応じお、 特定の凊理を優先的に実行させるこずができる。  Further, in the present information processing apparatus, the execution status of the workload for each process is monitored by the monitor unit 18 and the monitoring result is displayed on a monitor or the like by the display unit 20. Workload execution status can be visually checked. Therefore, after recognizing the execution status of the workload for each process, the user can operate the reference value used for calculating / changing the priority in the priority calculation unit 13 by the operation means 16 using the operation means 16. Depending on the workload status of each process, specific processes can be executed preferentially.
〔3〕 第 3実斜圢態  [3] Third embodiment
次に、 本発明の第 3実斜圢態における情報凊理装眮に぀いお説明する。 図 1 0 は第 3実斜圢態における情報凊理装眮の機胜構成を瀺すプロック図である。 なお、 図 1 0䞭、 既述の笊号ず同䞀の笊号は、 同䞀の郚分もしくはほが同䞀の郚分を瀺 しおいるので、 その詳现な説明は省略する。  Next, an information processing device according to a third embodiment of the present invention will be described. FIG. 10 is a block diagram illustrating a functional configuration of the information processing apparatus according to the third embodiment. In FIG. 10, since the same reference numerals as those described above indicate the same or almost the same parts, detailed description thereof will be omitted.
図 1 0に瀺すように、 本発明の第 3実斜圢態にかかる情報凊理装眮は、 䞊蚘の 第 1実斜圢態の情報凊理装眮ず同様の構成に加えお、 さらに、 実行環境ずしおの ワヌクロヌドの実行状況ずその実行状況に応じた基準倀ずの組み合わせを保持す るテヌブル 1 7ず、 かかる情報凊理装眮で実行されおいる凊理毎のワヌクロヌド の実行状況をモニタするモニタ手段 1 8ず、 このモニタ手段 1 8によるモ゚タ結 果を受けおテヌブル 1 7を参照し、 かかる凊理の基準倀をモニタ手段 1 8によ぀ おモニタされたワヌクロヌドの実行状況に応じたものに動的に倉曎する倉曎手段 1 9ずをそなえお構成されおいる。 ' As shown in FIG. 10, the information processing apparatus according to the third embodiment of the present invention has the same configuration as the information processing apparatus of the above-described first embodiment, and further includes the execution of a workload as an execution environment. A table 17 for storing a combination of a situation and a reference value according to the execution situation, a monitor means 18 for monitoring the execution situation of a workload for each process executed by the information processing apparatus, A change that dynamically changes the reference value of such processing to a value according to the execution status of the workload monitored by the monitoring means 18 by referring to the table 17 in response to the result of the moeta by the means 18 means It is composed with 19. '
テヌブル 1 7は、 ナヌザの意向等によっお、 特定のワヌクロヌドず、 このヮヌ クロヌドに察応する基準倀ずを保持させるこずができるように構成されおおり、 本実斜圢態のテヌブル 1 7には、 その䟋ずしお、 図 1 1に瀺すように、 ケヌス 1 〜ケヌス 3のワヌクロヌド実行状況ず、 各ワヌクロヌドの実行状況に応じた基準 倀ずが保持されおいる。  The table 17 is configured to be able to hold a specific workload and a reference value corresponding to the workload according to the user's intention and the like. As an example, as shown in Fig. 11, the workload execution status of case 1 to case 3 and the reference value according to the execution status of each workload are held.
テヌブル 1 7におけるケヌス 1には、 1次呜什キャッシュメモリ 2及び 1次デ ヌタキャッシュメモリ 8でのヒット率 即ち、 呜什に基づく呜什語矀が 1次呜什 キャッシュメモリ 2に栌玍されおいる率及び呜什に䜿甚するデヌタが 1次デヌタ キャッシュメモリ 8に栌玍されおいる率 が 9 7 %以䞊であるずいうワヌクロヌ ドの実行状況ず、 優先床算出郚 1 3の算出郚 1 3 aにおける第 1のタむミングで の優先床倉数の算出/倉曎に䜿甚される基準倀 X 2 (図 4のステップ S 1 2 S 1 3参照 の倀 1ずが察応づけられお保持されおいる。  Case 1 in Table 17 shows the hit rates in the primary instruction cache memory 2 and the primary data cache memory 8 (that is, the rate at which the instruction group based on the instruction is stored in the primary instruction cache memory 2). And the rate at which data used for instructions are stored in the primary data cache memory 8) is 97% or more, and the first priority in the calculation unit 13a of the priority calculation unit 13 The value 1 of the reference value X 2 (see steps S 12 and S 13 in FIG. 4) used for calculating / changing the priority variable at the timing of is held in association with each other.
たた、 テヌブル 1 7におけるケヌス 2には、 かかる凊理に぀いおの呜什を実行 する際のデヌタフェッチ芁求が 3 0 0䞇個以䞋であるずいうワヌクロヌドの実行 状況ず、 優先床算出郚 1 3の算出郚 1 3 aにおける第 1のタむミングでの優先床 倉数の算出/倉曎に䜿甚される基準倀 X 2 (図 4のステップ S 1 2 S 1 3参 照 の倀 1ずが察応づけられお保持されおいる。  Case 2 in Table 17 shows the workload execution status where the number of data fetch requests when executing instructions for such processing is 300000 or less, and the calculation unit of the priority calculation unit 13 13 The priority value at the first timing in 3a The value 1 of the reference value X2 (see steps S12 and S13 in Fig. 4) used for calculating / changing the variable is held in association with Have been.
さらに、 テヌブル 1 7におけるケヌス 3には、 かかる凊理に基づくキャッシュ ミスが 5 0 0呜什に 1回以䞊発生し、 䞔぀、 かかる凊理の挔算郚 6における実行 時間がこの凊理ず䞊列的に実行されおいる他の凊理の実行時間の 7 0 %以䞋であ るずいうワヌクロヌドの実行状況が、 優先床算出郚 1 3の算出郚 1 3 aにおける 第 1のタむミングでの優先床倉数の算出 Z倉曎に䜿甚される補正倀 i 1 (図 4の ステップ S 1 6参照 の倀を 1枛じ、 第 2のタむミングでの優先床倉数の算出 Z 倉曎に䜿甚される補正倀 i 3 (図 5のステップ S 2 1 '参照 の倀もしくは第 3の タむミングでの優先床倉数の算出/倉曎に䜿甚される補正倀 i 4 (図 6のステツ プ S 3 1参照 の倀に 1加えるこずに察応づけられお保持されおいる。  Further, in Case 3 in Table 17, a cache miss based on such processing occurs at least once in 500 instructions, and the execution time of the processing in the arithmetic unit 6 is executed in parallel with this processing. The execution status of the workload, which is 70% or less of the execution time of the other processing, is caused by the calculation Z of the priority variable at the first timing in the calculation unit 13a of the priority calculation unit 13. The value of the correction value i 1 used (see step S 16 in FIG. 4) is decremented by 1, and the correction value i 3 used to change the priority variable Z at the second timing (step S 16 in FIG. 5) 2 1 ′) or the correction value i 4 (see step S 31 in FIG. 6) used to calculate / change the priority variable at the third timing. Is held.
モニタ手段 1 8は、 凊理毎のヮ䞀クロヌドの実行状況をモニタするものであり、 具䜓的には、 各凊理の挔算資源の䜿甚状況 キャッシュメモリの䜿甚状況等かか る情報凊理装眮の各機胜の䜿甚状況をモ゚タしおいる。 The monitoring means 18 monitors the execution status of the first load for each process. Specifically, the monitoring means 18 determines whether the usage status of the processing resources of each process, the usage status of the cache memory, and the like. The usage status of each function of the information processing device is monitored.
このような構成により、 本菜明の第 3実斜圢態にかかる情報凊理装眮では、 侊 蚘の第 1実斜圢態ず同様、 制埡郚 1 4力 優先床算出郚 1 3が算出 Z倉曎した各 凊理の優先床に基づいお優先床の高い凊理を優先的に遞択しお呜什バッファ 3か らデコヌダ 5ぞ出力させるようにセレクタ 4を制埡するが、 その際、 倉曎手段 1 9がモニタ手段 1 8による各凊理のワヌクロヌド実行状況のモニタ状況を垞に監 芖しおおり、 倉曎手段 1 9は、 モニタ手段 1 8のモニタ結果を受けお、 テヌプノレ 1 7を参照し、 モニタ結果がテヌブル 1 7に保持されたケヌス 1〜3のワヌク口 ヌドの実行状況に該圓するずきには、 テヌブル 1 7に保持された、 かかるワヌク ロヌド実行状況に察応した基準倀ずなるように、 優先床算出郚 1 3における基準 倀を倉曎する。  With such a configuration, in the information processing apparatus according to the third embodiment of the present invention, as in the above-described first embodiment, the control unit 14 and the power priority calculation unit 13 calculate each Z-changed process. The selector 4 is controlled so that a process having a higher priority is preferentially selected on the basis of the priority and output from the instruction buffer 3 to the decoder 5. The monitoring status of the processing workload execution status is constantly monitored, and the changing means 19 receives the monitoring result of the monitoring means 18, refers to the tape hole 17, and holds the monitoring result in the table 17. In cases 1 to 3, the reference values in the priority calculation unit 13 are set so that the reference values corresponding to the workload execution status stored in Table 17 are obtained. To change.
ここで、 本実斜圢態の情報凊理装眮においお凊理 Aず凊理 Bずが䞊列的に実行 されおいる堎合に、 モニタ手段 1 8による凊理 Aのワヌクロヌドのモニタ結果が テヌブル 1 7のケヌス 1に瀺すワヌクロヌド実行状況に該圓するものであれば、 倉曎手段 1 9は、 優先床算出郚 1 3の凊理 Aの基準倀 X 2を 1ずする。 これによ り、 キダッシュミスがほずんど発生しおいなレ、凊理 Aにおいおキダッシュミスが 発生した堎合には、 凊理 Aの優先床を䜎くするように蚭定するこずができ 図 4 のステップ S 1 4参照、 凊理 Bずの実行バランスを良奜に保぀こずができるよ うになる。  Here, when the processing A and the processing B are executed in parallel in the information processing apparatus of the present embodiment, the monitoring result of the workload of the processing A by the monitoring means 18 is shown in Case 1 of Table 17. If it corresponds to the workload execution status, the change unit 19 sets the reference value X2 of the process A of the priority calculation unit 13 to 1. As a result, if a cache miss has hardly occurred, or if a cache miss has occurred in process A, the priority of process A can be set to be lower (step S 14 in FIG. 4). ), And it is possible to maintain a good execution balance with process B.
たた、 モニタ手段 1 8による凊理 Aのワヌクロヌドのモニタ結果がテヌブル 1 7のケヌス 2に瀺すワヌクロヌド実行状況に該圓するものであれば、 倉曎手段 1 9は、 優先床算出郚 1 3の凊理 Aの基準倀 X 2を 1ずする。 これにより、 デヌタ フェッチ芁求の少ない凊理 Aにおいおキダッシュミスが発生した堎合には、 凊理 Aの優先床を䜎くするように蚭定するこずができ 図 4のステップ S 1 4参照、 凊理 Bずの実行バランス 挔算資源の共有バランス を良奜に保぀こずができる ようになる。  Further, if the monitoring result of the workload of the process A by the monitoring means 18 corresponds to the workload execution status shown in Case 2 of Table 17, the changing means 19 performs the processing of the priority calculation unit 13 The reference value X 2 of A is set to 1. As a result, if a cache miss occurs in process A with a small data fetch request, the priority of process A can be set to be low (see step S14 in FIG. 4). The execution balance (computation resource sharing balance) can be maintained well.
さらに、 モニタ手段 1 8による凊理 Aのワヌクロヌドのモニタ結果がテヌブル 1 7のケヌス 3に瀺すワヌクロヌド実行状況に該圓するものであれば、 キダッシ ュミスが頻発し、 䞔぀、 他の凊理 ここでは凊理 B ) ず比范しお挔算資源の䜿甚 割合が少ない凊理 Aに぀いおの優先床を高くするように蚭定するこずができる (図 4のステップ S 1 6及び図 5のステップ S 2 1もしくは図 6のステップ S 3 1参照。 これにより、 他の凊理 Bず比范しお挔算郚 6の挔算資源をあたり䜿甚 しおおらず、 スムヌズに実行されおいない凊理 Aの優先床を高く倉曎させるこず ができ、 凊理 Bずの実行バランスを良奜に保぀こずができる。 Furthermore, if the monitoring result of the workload of process A by the monitoring means 18 corresponds to the workload execution status shown in Case 3 of Table 17, cache misses occur frequently and other processes (here, Use of computing resources compared to process B) The priority can be set to be higher for the process A having a small ratio (see step S16 in FIG. 4 and step S21 in FIG. 5 or step S31 in FIG. 6). This makes it possible to change the priority of the processing A, which does not use the computational resources of the processing unit 6 as much as compared with the other processing B, and is not executed smoothly, to a higher priority. Can be kept good.
このように、 本発明の第 3実斜圢態にかかる情報凊理装眮では、 テヌブル 1 7 に保持されたワヌクロヌド実行状況ずそのワヌクロヌド実行状況に察応した基準 倀ずに基づいお、 倉曎手段 1 9が動的に優先床算出郚 1 3の基準倀を倉曎するた め、 かかる凊理の優先床がワヌクロヌド実行状況に応じお動的に倉曎されるこず になる。 その結果、 ワヌクロヌドの実行状況に応じた耇数の凊理の実行が可胜に なるずずもに、 ナヌザ等の意向をワヌクロヌドの実行状況に応じお反映させるこ ずができる。  As described above, in the information processing apparatus according to the third embodiment of the present invention, the changing unit 19 is configured to change the workload execution status based on the workload execution status held in the table 17 and the reference value corresponding to the workload execution status. Since the reference value of the priority calculation unit 13 is dynamically changed, the priority of such processing is dynamically changed according to the workload execution status. As a result, a plurality of processes can be executed according to the workload execution status, and the intention of the user can be reflected according to the workload execution status.
なお、 本実斜圢態にかかるテヌブル 1 7に保持されたワヌクロヌド実行状況及 びそれに察応した基準倀の内容や具䜓的な数倀は、 䟋ずしお瀺したものであり、 これに限定されるものではない。 テヌブル 1 7に保持されるワヌクロヌド実行状 況ずそれに察応した基準倀ずは、 ナヌザの意向や情報凊理装眮における凊理の実 行状況等によっお倉曎されるものである。  Note that the workload execution status, the contents of the reference values corresponding thereto, and specific numerical values stored in the table 17 according to the present embodiment are shown as examples, and are not limited thereto. . The workload execution status and the corresponding reference value stored in Table 17 are changed depending on the user's intention, the execution status of the process in the information processing device, and the like.
〔4〕 その他  [4] Other
なお、 本発明は䞊述した実斜圢態に限定されるものではなく、 本発明の趣旚を 逞脱しない範囲で皮々倉圢しお実斜するこずができる。  It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the spirit of the present invention.
䟋えば、 䞊述した実斜圢態では、 䞊列的に実行される凊理 スレッ ド ストラ ンド の数が、 A, Bの 2぀である堎合に぀いお説明しおいるが、 本発明はこれ に限定されるものではなく、 3以䞊の凊理を䞊列的に実行する堎合にも䞊述した 各実斜圢態ず同様に適甚され、 䞊述した各実斜圢態ず同様の䜜甚効果を埗るこず ができる。  For example, in the above-described embodiment, the case where the number of processes (threads, strands) executed in parallel is two, A and B, but the present invention is not limited to this. However, the present invention is applied similarly to the above-described embodiments even when three or more processes are executed in parallel, and the same operation and effect as the above-described embodiments can be obtained.
たた、 リク゚スト管理郚 1 2で扱うリク゚ストの皮別がデヌタキャッシュミス 以倖のものに及ぶ堎合も考えられる。 その堎合は、 リク゚ストの皮別により、 個 別に基準倀を甚意するこずが考えられる。 さらに、 リク゚ストの皮別に察応しお、 かかる凊理の優先床倉数の最倧倀 ·最小倀を蚭定し、 これらの倀を超える堎合に は、 優先床倉数の増加 ·枛少凊理 優先床倉数の算出/倉曎凊理 を停止するよ うに構成するこずも考えられる。 It is also conceivable that the type of request handled by the request management unit 12 covers a type other than a data cache miss. In such a case, it is conceivable to prepare individual reference values depending on the type of request. Furthermore, the maximum value and the minimum value of the priority variable for such processing are set according to the type of the request, and when these values are exceeded, May be configured to stop the process of increasing / decreasing priority variables (calculation / change process of priority variables).
たた、 䞊述したリク゚スト管理郚 12 優先床算出郚 13 (算出郚 1 3 a) 制埡郚 14 採取郚 15 操䜜手段 16 モニタ手段 18, 倉曎手段 1 9ずしお の機胜は、 コンピュヌタ CPU, 情報凊理装眮 各皮端末を含む が所定のァ プリケヌシペンプログラム 呜什凊理制埡プログラム を実行するこずによっお 実珟される。  The functions of the request management unit 12, the priority calculation unit 13 (calculation unit 13a), the control unit 14, the collection unit 15, the operation unit 16, the monitor unit 18, and the change unit 19 described above are implemented by a computer (CPU , An information processing device, and various terminals) by executing a predetermined application program (command processing control program).
そのプログラムは、 䟋えばフレキシブルディスク CD— ROM, CD-R, CD-RW, DVD等のコンピュヌタ読取可胜な蚘録媒䜓に蚘録された圢態で提 䟛される。 この堎合、 コンピュヌタはその蚘録媒䜓から呜什凊理制埡プログラム を読み取っお内郚蚘憶装眮たたは倖郚蚘憶装眮に転送し栌玍しお甚いる。 たた、 そのプログラムを、 䟋えば磁気ディスク, 光ディスク, 光磁気ディスク等の蚘憶 装眮 蚘録媒䜓 に蚘録しおおき、 その蚘憶装眮から通信回線を介しおコンビュ ヌタに提䟛するようにしおもよレ、。  The program is provided in a form recorded on a computer-readable recording medium such as a flexible disk, a CD-ROM, a CD-R, a CD-RW, and a DVD. In this case, the computer reads the instruction processing control program from the recording medium, transfers it to the internal storage device or the external storage device, stores it, and uses it. Alternatively, the program may be recorded on a storage device (recording medium) such as a magnetic disk, an optical disk, or a magneto-optical disk, and provided to the computer from the storage device via a communication line. ,.
ここで、 コンピュヌタずは、 ハヌドりェアず OS (オペレヌティングシステ ム ずを含む抂念であり、 OSの制埡の䞋で動䜜するハヌドりェアを意味しおい る。 たた、 OSが䞍芁でアプリケヌションプログラム単独でハヌドりェアを動䜜 させるような堎合には、 そのハヌドりェア自䜓がコンピュヌタに盞圓する。 ハヌ ドり゚アは、 少なくずも、 CPU等のマむクロプロセッサず、 蚘録媒䜓に蚘録さ れたコンピュヌタプログラムを読み取るための手段ずをそなえおいる。 䞊蚘呜什 凊理制埡プログラムずしおのアプリケ䞀ションプログラムは、 䞊述のようなコン ピュヌタに、 リク゚スト管理郚 12 優先床算出郚 1 3 制埡郚 14, 採取郚 1 5, 操䜜手段 16 モニタ手段 18, 倉曎手段 19ずしおの機胜を実珟させるプ ログラムコヌドを含んでいる。 たた、 その機胜の䞀郚は、 アプリケヌションプロ グラムではなく O Sによっお実珟されおもよい。  Here, the computer is a concept including hardware and an OS (operating system), and means hardware that operates under the control of the OS. In the case where the OS is unnecessary and the hardware is operated by the application program alone, the hardware itself corresponds to a computer. The hardware has at least a microprocessor such as a CPU and a means for reading a computer program recorded on a recording medium. The application program as the instruction processing control program includes a request management unit 12, a priority calculation unit 13, a control unit 14, a sampling unit 15, an operation unit 16, a monitoring unit 18, It includes a program code for realizing the function as the changing means 19. In addition, some of the functions may be realized by OS instead of application programs.
さらに、 本実斜圢態における蚘録媒䜓ずしおは、 䞊述したフレキシブルデむス ク CD_ROM CD-R, CD-RW, DVD, 磁気ディスク 光ディスク 光磁気ディスクのほか、 I Cカヌド ROMカヌトリッゞ 磁気テヌプ ノ ンチ カヌド コンピュヌタの内郚蚘憶装眮 RAMや ROMなどのメモリ 倖郚蚘 憶装眮等や、 バヌコヌドなどの笊号が印刷された印刷物等の、 コンピュヌタ読取 可胜な皮々の媒䜓を利甚するこずもできる。 産業䞊の利甚可胜性 Furthermore, in addition to the above-mentioned flexible disk, CD_ROM, CD-R, CD-RW, DVD, magnetic disk, optical disk, and magneto-optical disk, the recording medium according to the present embodiment includes an IC card, a ROM cartridge, a magnetic tape, and a magnetic disk. Card, computer internal storage (memory such as RAM and ROM), external storage Various computer-readable media, such as storage devices and printed materials on which codes such as bar codes are printed, can also be used. Industrial applicability
以䞊のように、 本発明によれば、 2以䞊の凊理を䞊列的に実行する情報凊理装 眮においお、 実際の呜什実行状況に応じお挔算資源を有効に利甚できるように各 凊理の優先床を算出/倉曎しお、 この優先床に基づいお凊理を実行するため、 よ り確実に挔算資源の空き時間を削枛しおスルヌプットの倧幅な向䞊を実珟するこ ずができる。  As described above, according to the present invention, in an information processing apparatus that executes two or more processes in parallel, the priority of each process is set so that the computing resources can be effectively used according to the actual instruction execution status. Since the calculation / change is performed and the processing is executed based on this priority, it is possible to more surely reduce the idle time of the computational resources and achieve a significant improvement in the throughput.
埓っお、 本発明は、 マルチスレッド方匏を採甚したコンピュヌタ等の情報凊理 装眮に甚いお奜適であり、 その有甚性は極めお高いものず考えられる。  Therefore, the present invention is suitable for use in an information processing device such as a computer employing a multi-thread system, and its usefulness is considered to be extremely high.

Claims

請 求 の 範 囲 The scope of the claims
1 . 2以䞊の凊理を䞊列的に実行する情報凊理装眮であっお、 1.2 An information processing apparatus that executes two or more processes in parallel,
前蚘 2以䞊の凊理を実行するための呜什ァドレスを前蚘凊理毎に生成する呜什 アドレス生成郚ず、  An instruction address generator for generating an instruction address for executing the two or more processes for each of the processes;
䞻蚘憶䞊の呜什領域の䞀郚のコピヌを䞀時的に栌玍し、 該コピヌの䞭から、 該 呜什ァドレス生成郚によっお生成された前蚘呜什ァドレスに応じた呜什を出力す る呜什キャッシュメモリず、  An instruction cache memory for temporarily storing a partial copy of the instruction area on the main memory and outputting an instruction corresponding to the instruction address generated by the instruction address generation unit from the copy;
該呜什キダッシュメモリから出力された耇数の呜什を保持する呜什バッファず、 該呜什バッファに保持された呜什のうちの少なくずも䞀぀を遞択しお出力する セレクタず、  An instruction buffer for holding a plurality of instructions output from the instruction cache memory; a selector for selecting and outputting at least one of the instructions held in the instruction buffer;
該セレクタからの呜什をデコヌドするデコヌダず、  A decoder for decoding an instruction from the selector;
該デコヌダによるデコヌド結果に応じた挔算を実行する挔算郚ず、  An operation unit for executing an operation according to a decoding result by the decoder;
䞻蚘憶䞊のデヌタ領域の䞀郚のコピヌを䞀時的に栌玍し、 該コピヌの䞭から、 該挔算郚での挔算に必芁なデヌタを該挔算郚からの芁求に応じお出力するデヌタ キャッシュメモリず、  A data cache memory for temporarily storing a partial copy of the data area on the main memory and outputting data necessary for the operation in the operation unit from the copy in response to a request from the operation unit; ,
該挔算郚における挔算資源の空き時間を削枛するように各凊理の優先床を算出 /倉曎する優先床算出郚ず、  A priority calculation unit that calculates / changes the priority of each process so as to reduce the idle time of the calculation resources in the calculation unit;
該優先床算出郚によっお算出 Z倉曎された各凊理の優先床を参照し、 前蚘優先 床の高い凊理に぀いおの呜什を優先的に遞択しお該デコヌダぞ出力するように該 セレクタの動䜜を制埡する制埡郚ずをそなえたこずを特城ずする、 情報凊理装眮。  The operation of the selector is controlled so as to preferentially select an instruction for the high-priority processing and output the instruction to the decoder by referring to the priority of each processing whose Z has been changed by the priority calculation unit. An information processing device comprising a control unit.
2 . 前蚘 2以䞊の凊理の実行に䌎い圓該情報凊理装眮から倖郚に察しお送出さ れたリク゚ストに関する情報を前蚘凊理毎に管理するリク゚スト管理郚をさらに そなえ、 2. It further includes a request management unit that manages information on a request sent from the information processing apparatus to the outside with the execution of the two or more processes for each of the processes.
該優先床算出郚が、 該リク゚ス ト管理郚で管理されおいる前蚘リク゚ストに関 する情報に基づいお、 各凊理の前蚘優先床を算出/倉曎するこずを特城ずする、 請求の範囲第 1項蚘茉の情報凊理装眮。 2. The method according to claim 1, wherein the priority calculating unit calculates / changes the priority of each process based on information on the request managed by the request management unit. An information processing apparatus according to claim 1.
3 . 䞻蚘憶デヌタの読出しリク゚ストが前蚘リク゚ストずしお圓該情報凊理装 眮から倖郚に察しお送出された際に、 該優先床算出郚が、 該リク゚スト管理郚で 管理されおいる、 倖郚からの応答埅ち䞭のリク゚ストの数に応じお、 圓該リクェ ストの送出元である凊理の前蚘優先床を算出/倉曎するこずを特城ずする、 請求 の範囲第 2項蚘茉の情報凊理装眮。 3. When the read request of the main memory data is sent from the information processing device to the outside as the request, the priority calculation unit waits for an external response managed by the request management unit. 3. The information processing apparatus according to claim 2, wherein the priority of a process that is the source of the request is calculated / changed according to the number of requests in the request.
4 . 前蚘リク゚ストの数が所定倀を超えおいる堎合、 該優先床算出郚が、 圓該 リク゚ストの送出元である凊理の前蚘優先床を珟状よりも䜎くするように倉曎す るこずを特城ずする、 請求の範囲第 3項蚘茉の情報凊理装眮。 4. When the number of the requests exceeds a predetermined value, the priority calculation unit changes the priority of the process that is the source of the request to be lower than the current level. The information processing device according to claim 3.
5 . 前蚘 2以䞊の凊理のいずれか䞀぀の実行,に䌎っお送出された前蚘リク゚ス トに察する応答を受け取った際に、 該優先床算出郚が、 該リク゚スト管理郚で管 理されおいる圓該リク゚ストの履歎に応じお、 圓該リク゚ストの送出元である凊 理の前蚘優先床を算出 Z倉曎するこずを特城ずする、 請求の範囲第 2項蚘茉の情 報凊理装眮。 5. When receiving a response to the request transmitted in accordance with the execution of any one of the two or more processes, the priority calculation unit performs the request management managed by the request management unit. 3. The information processing apparatus according to claim 2, wherein the priority of a process that is the transmission source of the request is calculated or changed according to the history of the request.
6 . 圓該リク゚ストが、 該リク゚スト管理郚で管理されおいる、 倖郚からの応 答埅ち䞭の党おのリク゚ストの䞭で最も叀いものである堎合、 該優先床算出郚が、 圓該リク゚ストの送出元である凊理の前蚘優先床を珟状よりも高くするように倉 曎するこずを特城ずする、 請求の範囲第 5項蚘茉の情報凊理装眮。 6. If the request is the oldest of all requests waiting for a response from the outside managed by the request management unit, the priority calculation unit determines whether the request has been sent. 6. The information processing apparatus according to claim 5, wherein the priority of a certain process is changed so as to be higher than a current level.
7 . 前蚘 2以䞊の凊理のいずれか䞀぀の実行に䌎っお送出された前蚘リク゚ス トに察する応答を受け取った際に、 該優先床算出郚が、 該リク゚スト管理郚で管 理されおいる圓該リク゚ストの皮別に応じお、 圓該リク゚ストの送出元である凊 理の前蚘優先床を算出/倉曎するこずを特城ずする、 請求の範囲第 2項蚘茉の情 報凊理装眮。 7. When receiving a response to the request transmitted along with the execution of any one of the two or more processes, the priority calculation unit determines whether the request managed by the request management unit is 3. The information processing device according to claim 2, wherein the priority of the process that is the source of the request is calculated / changed according to the type.
8 . 圓該リク゚スト力 該デヌタキャッシュメモリでのミスヒッ トに䌎っお送 出されたものである堎合、 該優先床算出郚が、 圓該リク゚ストの送出元である凊 理の前蚘優先床を珟状よりも高くするように倉曎するこずを特城ずする、 請求の 範囲第 7項蚘茉の情報凊理装眮。 8. If the request power is transmitted due to a miss in the data cache memory, the priority calculation unit determines whether the request source is the source of the request. 8. The information processing apparatus according to claim 7, wherein the priority of the information processing is changed to be higher than the current level.
9 . 圓該情報凊理装眮から倖郚に察するリク゚ストが発生した際に、 該優先床 算出郚が、 該リク゚スト管理郚で管理されおいる圓該リク゚ストの皮別に応じお 圓該リク゚ストの送出元である凊理の前蚘優先床を算出/倉曎するこずを特城ず する、 請求の範囲第 2項蚘茉の情報凊理装眮。 9. When a request to the outside is generated from the information processing device, the priority calculation unit determines the priority of the process that is the transmission source of the request according to the type of the request managed by the request management unit. 3. The information processing apparatus according to claim 2, wherein the degree is calculated / changed.
1 0 . 圓該リク゚ス トが、 該デヌタキダッシュメモリでのミスヒッ トに䌎぀お 送出されたものである堎合、 該優先床算出郚が、 圓該リク゚ストの送出元である 凊理の前蚘優先床を珟状よりも䜎くするように倉曎するこずを特城ずする、 請求 の範囲第 9項蚘茉の情報凊理装眮。 10. If the request was sent in response to a miss in the data cache memory, the priority calculation unit sets the priority of the process that is the source of the request to be lower than the current level. 10. The information processing apparatus according to claim 9, wherein the information processing apparatus is changed so as to be lower.
1 1 . 該挔算郚における挔算資源の䜿甚状況を前蚘凊理毎に採取する採取郚を さらにそなえ、 11. A sampling unit for sampling the usage status of the computing resources in the computing unit for each of the processes is further provided.
該優先床算出郚が、 該採取郚によっお採取された該挔算資源の䜿甚状況に応じ お、 各凊理の優先床を算出 Z倉曎するこずを特城ずする、 請求の範囲第 1項蚘茉 の情報凊理装眮。  2. The information processing apparatus according to claim 1, wherein the priority calculation unit calculates and changes the priority of each process according to a use state of the computational resources collected by the collection unit. apparatus.
1 2 . 前蚘 2以䞊の凊理のいずれか䞀぀に぀いお該採取郚によっお採取された 該挔算資源の䜿甚状況ずしおの䜿甚率が所定倀を超えおいる堎合、 該優先床算出 郚が、 圓該凊理の前蚘優先床を珟状よりも䜎くするように倉曎するこずを特城ず する、 請求の範囲第 1 1項蚘茉の情報凊理装眮。 12. If the usage rate as the usage status of the computation resource collected by the collection unit for any one of the two or more processes exceeds a predetermined value, the priority calculation unit may The information processing apparatus according to claim 11, wherein the priority is changed so as to be lower than a current level.
1 3 . 前蚘 2以䞊の凊理の実行に䌎い圓該情報凊理装眮から倖郚に察しお送出 されたリク゚ストに関する情報を前蚘凊理毎に管理するリク゚スト管理郚ず、 該挔算郚における挔算資源の䜿甚状況を前蚘凊理毎に採取する採取郚ずをさら にそなえ、 13. A request management unit that manages information on a request sent from the information processing apparatus to the outside in accordance with the execution of the two or more processes for each of the processes. A sampling section for each treatment is further provided.
該優先床算出郚が、 該リク゚スト管理郚で管理されおいる前蚘リク゚ストに関 する情報ず、 該採取郚によっお採取された該挔算資源の䜿甚状況ずに応じお、 各 凊理の優先床を算出/倉曎するこずを特城ずする、 請求の範囲第 1項蚘茉の情報 凊理装眮。 The priority calculation unit relates to the request managed by the request management unit. 2. The information processing device according to claim 1, wherein the priority of each process is calculated / changed according to the information to be performed and the use status of the computational resources collected by the collection unit.
1 4 . 䞻蚘憶デヌタの読出しリク゚ストが前蚘リクェストずしお圓該情報凊理 装眮から倖郚に察しお送出された際に、 該優先床算出郚が、 該リク゚スト管理郚 で管理されおいる、 倖郚からの応答埅ち䞭のリク゚ストの数ず、 圓該リク゚ス ト の送出元である凊理に぀いお該採取郚によ぀お採取された該挔算資源の䜿甚状況 ずに応じお、 圓該リク゚ストの送出元である凊理の前蚘優先床を算出/倉曎する こずを特城ずする、 請求の範囲第 1 3項蚘茉の情報凊理装眮。 14. When the main memory data read request is sent from the information processing device to the outside as the request, the priority calculation unit waits for an external response managed by the request management unit. The priority of the process that is the source of the request is determined in accordance with the number of requests in the request and the usage status of the processing resource collected by the collection unit for the process that is the source of the request. The information processing apparatus according to claim 13, wherein the information processing apparatus calculates / changes the information.
1 5 . 前蚘リク゚ストの数が所定範囲內にあり、 䞔぀、 圓該リク゚ストの送出 元である凊理に぀いお該採取郚によっお採取された該挔算資源の䜿甚状況ずしお の䜿甚率が所定倀を超えおいる堎合、 該優先床算出郚が、 圓該リク゚ストの送出 元である凊理の前蚘優先床を珟状よりも䜎くするように倉曎するこずを特城ずす る、 請求の範囲第 1 4項蚘茉の情報凊理装眮。 15. When the number of the requests is within the predetermined range 內, and the usage rate as the usage status of the computational resources collected by the collection unit for the process from which the request is transmitted exceeds a predetermined value. 15. The information processing apparatus according to claim 14, wherein the priority calculation unit changes the priority of a process that is a source of the request so as to be lower than a current level.
1 6 . 前蚘リク゚ストの数が所定倀を超えおいる堎合、 該優先床算出郚が、 圓 該リク゚ストの送出元である凊理の前蚘優先床を珟状よりも䜎くするように倉曎 するこずを特城ずする、 請求の範囲第 1 4項蚘茉の情報凊理装眮。 16. If the number of the requests exceeds a predetermined value, the priority calculation unit changes the priority of the process that is the source of the request to be lower than the current level. The information processing device according to claim 14, wherein
1 7 . 圓該情報凊理装眮においお前蚘 2以䞊の凊理を実行する際に䜿甚される 1以䞊の実行環境ずしおのワヌクロヌドの特性、 もしくは、 ナヌザの芁望に応じ お、 基準倀 前蚘優先床の初期倀 前蚘リク゚ス トの数ず比范される前蚘所定倀, 前蚘リク゚ストの数ず比范される前蚘所定範囲 前蚘䜿甚率ず比范される前蚘所 定倀 該優先床算出郚による前蚘優先床の倉曎幅のうちの少なくずも䞀぀ を手 動で操䜜するための操䜜手段をさらにそなえたこずを特城ずする、 請求の範囲第 1項〜第 1 6項のいずれか䞀項に蚘茉の情報凊理装眮。 17. A reference value (initial value of the priority) according to a characteristic of a workload as one or more execution environments used when executing the two or more processes in the information processing device or a user's request. A value, the predetermined value to be compared with the number of requests, the predetermined range to be compared to the number of requests, the predetermined value to be compared to the usage rate, and a change width of the priority by the priority calculation unit. The information processing apparatus according to any one of claims 1 to 16, further comprising an operation means for manually operating at least one of the above.
1 8 . 圓該情報凊理装眮においお前蚘 2以䞊の凊理を実行する際に䜿甚される 1以䞊の実行環境ずしおのワヌクロヌドの実行状況ず、 その実行状況に応じた基 準倀 前蚘優先床の初期倀 前蚘リク゚ストの数ず比范される前蚘所定倀 前蚘 リク゚ストの数ず比范される前蚘所定範囲 前蚘䜿甚率ず比范される前蚘所定倀: 該優先床算出郚による前蚘優先床の倉曎幅のうちの少なくずも䞀぀ ずの組み合 わせを保持するテヌブルず、 18. The execution status of the workload as one or more execution environments used when executing the two or more processes in the information processing device, and a reference value according to the execution status (the initial value of the priority) A value, the predetermined value to be compared with the number of requests, the predetermined range to be compared to the number of requests, the predetermined value to be compared to the usage rate: a change width of the priority by the priority calculation unit. A table holding a combination with at least one of
前蚘ワヌクロヌドの実行状況をモニタするモニタ手段ず、  Monitoring means for monitoring the execution status of the workload;
該モニタ手段によるモニタ結果を受けお該テヌプルを参照し、 前蚘基準倀を、 該モニタ手段によっおモニタされた前蚘ワヌクロヌドの実行状況に応じたものに 動的に倉曎する倉曎手段ずをさらにそなえたこずを特城ずする、 請求の範囲第 1 項〜第 1 6項のいずれか䞀項に蚘茉の情報凊理装眮。  And a change unit for dynamically changing the reference value to a value corresponding to an execution status of the workload monitored by the monitor unit by referring to the table in response to the monitoring result by the monitor unit. The information processing apparatus according to any one of claims 1 to 16, characterized in that:
1 9 . 2以䞊の凊理を実行するための呜什アドレスを前蚘凊理毎に生成する呜 什ァドレス生成郚ず、 䞻蚘憶䞊の呜什領域の䞀郚のコピヌを䞀時的に栌玍し該コ ピヌの䞭から該呜什ァドレス生成郚によっお生成された前蚘呜什ァドレスに応じ た呜什を出力する呜什キダッシュメモリず、 該呜什キダッシュメモリから出力さ れた耇数の呜什を保持する呜什バッファず、 該呜什バッファに保持された呜什の うちの少なくずも䞀぀を遞択しお出力するセレクタず、 該セレクタからの呜什を デコヌドするデコヌダず、 該デコヌダによるデコヌド結果に応じた挔算を実行す る挔算郚ず、 䞻蚘憶䞊のデヌタ領域の䞀郚のコピヌを䞀時的に栌玍し、 該コピヌ の䞭から、 該挔算郚での挔算に必芁なデヌタを該挔算郚からの芁求に応じお出力 するデヌタキャッシュメモリずをそなえ、 前蚘 2以䞊の凊理を䞊列的に実行する 情報凊理装眮においお、 前蚘 2以䞊の凊理に぀いおの各呜什の実行状態を制埡す る呜什凊理制埡装眮であ぀お、 19.2 An instruction address generating unit for generating an instruction address for executing at least one processing for each processing, and temporarily storing a copy of a part of the instruction area on the main memory and storing the copy in the copy. An instruction cache memory that outputs an instruction corresponding to the instruction address generated by the instruction address generation unit from an instruction buffer; an instruction buffer that holds a plurality of instructions output from the instruction cache memory; A selector for selecting and outputting at least one of the instructions, a decoder for decoding an instruction from the selector, an operation unit for performing an operation in accordance with a result of decoding by the decoder, and data on the main memory. A data key for temporarily storing a partial copy of the area and outputting data necessary for the operation in the operation unit in response to a request from the operation unit from the copy Includes a Sshumemori, in an information processing apparatus for executing parallel to the two or more processing shall apply in the instruction processing controller that controls the execution status of each instruction for the two or more processing,
該挔算郚における挔算資源の空き時間を削枛するように各凊理の優先床を算出 Calculate the priority of each process so as to reduce the free time of computation resources in the computation unit
Z倉曎する優先床算出郚ず、 A priority calculating unit for changing Z,
該優先床算出郚によ぀お算出/倉曎された各凊理の優先床を参照し、 前蚘優先 床の高い凊理に぀いおの呜什を優先的に遞択しお該デコヌダぞ出力するように該 セレクタの動䜜を制埡する制埡郚ずをそなえたこずを特城ずする、 呜什凊理制埡 Referring to the priority of each process calculated / changed by the priority calculation unit, the operation of the selector is performed so as to preferentially select an instruction for the process with the higher priority and output it to the decoder. Command processing control characterized by having a control unit for controlling
2 0 . 2以䞊の凊理を実行するための呜什ァドレスを前蚘凊理毎に生成する呜 什ァドレス生成郚ず、 䞻蚘憶䞊の呜什領域の䞀郚のコピヌを䞀時的に栌玍し該コ ピヌの䞭から該呜什ァドレス生成郚によっお生成された前蚘呜什ァドレスに応じ た呜什を出力する呜什キャッシュメモリず、 該呜什キャッシュメモリから出力さ れた耇数の呜什を保持する呜什バッファず、 該呜什バッファに保持された呜什の うちの少なくずも䞀぀を遞択しお出力するセレクタず、 該セレクタからの呜什を デコヌドするデコヌダず、 該デコヌダによるデコヌド結果に応じた挔算を実行す る挔算郚ず、 䞻蚘憶䞊のデヌタ領域の䞀郚のコピヌを䞀時的に栌玍し、 該コピヌ の䞭から、 該挔算郚での挔算に必芁なデヌタを該挔算郚からの芁求に応じお出力 するデヌタキャッシュメモリずをそなえ、 前蚘 2以䞊の凊理を䞊列的に実行する 情報凊理装眮においお、 前蚘 2以䞊の凊理に぀いおの各呜什の実行状態を制埡す る呜什凊理制埡方法であっお、 An instruction address generation unit for generating an instruction address for executing 0.2 or more processes for each of the processes; a copy of a part of the instruction area on the main memory is temporarily stored and stored in the copy; An instruction cache memory for outputting an instruction corresponding to the instruction address generated by the instruction address generation unit, an instruction buffer for storing a plurality of instructions output from the instruction cache memory, and an instruction buffer for storing the instructions. A selector for selecting and outputting at least one of the instructions, a decoder for decoding an instruction from the selector, an operation unit for performing an operation in accordance with a result of decoding by the decoder, and data on the main memory. A data key for temporarily storing a partial copy of the area and outputting data necessary for the operation in the operation unit in response to a request from the operation unit from the copy Includes a Sshumemori, the information processing apparatus to perform parallel two or more processing, an instruction processing control method that controls the execution status of each instruction for the two or more processing,
該挔算郚における挔算資源の空き時間を削枛するように各凊理の優先床を算出 Z倉曎する優先床算出ステップず、  A priority calculating step of calculating the priority of each process so as to reduce the idle time of the processing resources in the processing unit;
該優先床算出ステップにおいお算出/倉曎された各凊理の優先床を参照し、 前 蚘優先床の高い凊理に぀いおの呜什を優先的に遞択しお該デコヌダぞ出力するよ うに該セレクタの動䜜を制埡する制埡ステップずを含むこずを特城ずする、 呜什 凊理制埡方法。  The operation of the selector is controlled by referring to the priority of each process calculated / changed in the priority calculation step and preferentially selecting an instruction for the process with the higher priority and outputting the instruction to the decoder. And a controlling step.
2 1 . 2以䞊の凊理を実行するための呜什ァドレスを前蚘凊理毎に生成する呜 什ァドレス生成郚ず、 䞻蚘憶䞊の呜什領域の䞀郚のコピヌを䞀時的に栌玍し該コ ピヌの䞭から該呜什ァドレス生成郚によっお生成された前蚘呜什ァドレスに応じ た呜什を出力する呜什キャッシュメモリず、 該呜什キャッシュメモリから出力さ れた耇数の呜什を保持する呜什バッファず、 該呜什バッファに保持された呜什の うちの少なくずも䞀぀を遞択しお出力するセレクタず、 該セレクタからの呜什を デコヌドするデコヌダず、 該デコヌダによるデコヌド結果に応じた挔算を実行す る挔算郚ず、 䞻蚘憶䞊のデヌタ領域の䞀郚のコピヌを䞀時的に栌玍し、 該コピヌ の䞭から、 該挔算郚での挔算に必芁なデヌタを該挔算郚からの芁求に応じお出力 するデヌタキャッシュメモリずをそなえ、 前蚘 2以䞊の凊理を䞊列的に実行する 情報凊理装眮においお、 前蚘 2以䞊の凊理に぀いおの各呜什の実行状態を制埡す る機胜をコンピュヌタに実行させるための呜什凊理制埡プログラムであっお、 該挔算郚における挔算資源の空き時間を削枛するように各凊理の優先床を算出 /倉曎する優先床算出郚、 および、 2.1.2 An instruction address generation unit for generating an instruction address for executing more than one process for each of the processes, and temporarily storing a copy of a part of the instruction area on the main memory and storing the copy in the copy. An instruction cache memory for outputting an instruction corresponding to the instruction address generated by the instruction address generation unit, an instruction buffer for storing a plurality of instructions output from the instruction cache memory, and an instruction buffer for storing the instructions. A selector for selecting and outputting at least one of the instructions, a decoder for decoding an instruction from the selector, an operation unit for performing an operation in accordance with a result of decoding by the decoder, and data on the main memory. Temporarily store a copy of the area, A data cache memory that outputs data necessary for the operation in the operation unit in response to a request from the operation unit, and executes the two or more processes in parallel. An instruction processing control program for causing a computer to execute a function of controlling the execution state of each instruction for two or more processings, wherein the priority of each processing is set so as to reduce the idle time of operation resources in the operation unit. A priority calculation unit that calculates / changes
該優先床算出郚によっお算出ノ倉曎された各凊理の優先床を参照し、 前蚘優先 床の高い凊理に぀いおの呜什を優先的に遞択しお該デコヌダぞ出力するように該 セレクタの動䜜を制埡する制埡郚ずしお、 該コンピュヌタを機胜させるこずを特 城ずする、 呜什凊理制埡プログラム。  The operation of the selector is controlled so as to refer to the priority of each process calculated and changed by the priority calculation unit and to preferentially select an instruction for the process with the higher priority and output it to the decoder. An instruction processing control program characterized by causing the computer to function as a control unit.
2 2 . 2以䞊の凊理を実行するための呜什ァドレスを前蚘凊理毎に生成する呜 什ァドレス生成郚ず、 䞻蚘憶䞊の呜什領域の䞀郚のコピヌを䞀時的に栌玍し該コ ピヌの䞭から該呜什ァドレス生成郚によっお生成された前蚘呜什ァドレスに応じ た呜什を出力する呜什キャッシュメモリず、 該呜什キャッシュメモリから出力さ れた耇数の呜什を保持する呜什バッファず、 該呜什バッファに保持された呜什の うちの少なくずも䞀぀を遞択しお出力するセレクタず、 該セレクタからの呜什を デコヌドするデコヌダず、 該デコヌダによるデコヌド結果に応じた挔算を実行す る挔算郚ず、 䞻蚘憶䞊のデヌタ領域の䞀郚のコピヌを䞀時的に栌玍し、 該コピヌ の䞭から、 該挔算郚での挔算に必芁なデヌタを該挔算郚からの芁求に応じお出力 するデヌタキャッシュメモリずをそなえ、 前蚘 2以䞊の凊理を䞊列的に実行する 情報凊理装眮においお、 前蚘 2以䞊の凊理に぀いおの各呜什の実行状態を制埡す る機胜をコンピュヌタに実行させるための呜什凊理制埡プログラムを蚘録したコ ンピュヌタ読取可胜な蚘録媒䜓であっお、 2.2.2 An instruction address generation unit that generates an instruction address for executing two or more processes for each of the processes, and temporarily stores a copy of a part of the instruction area on the main memory and stores the copy in the copy. An instruction cache memory for outputting an instruction corresponding to the instruction address generated by the instruction address generation unit, an instruction buffer for storing a plurality of instructions output from the instruction cache memory, and an instruction buffer for storing the instructions. A selector for selecting and outputting at least one of the instructions, a decoder for decoding an instruction from the selector, an operation unit for executing an operation in accordance with a result of decoding by the decoder, and data on the main memory. A data key for temporarily storing a partial copy of the area and outputting data necessary for the operation in the operation unit in response to a request from the operation unit from the copy And an instruction processing control program for causing a computer to execute a function of controlling an execution state of each instruction for the two or more processes, the information processing device having a flash memory and executing the two or more processes in parallel. A computer-readable recording medium on which the computer is recorded;
該呜什凊理制埡プログラムが、  The instruction processing control program comprises:
該挔算郚における挔算資源の空き時間を削枛するように各凊理の優先床を算出 /倉曎する優先床算出郚、 および、  A priority calculation unit that calculates / changes the priority of each process so as to reduce the idle time of the calculation resources in the calculation unit; and
該優先床算出郚によっお算出/倉曎された各凊理の優先床を参照し、 前蚘優先 床の高い凊理に぀いおの呜什を優先的に遞択しお該デコヌダぞ出力するように該 セレクタの動䜜を制埡する制埡郚ずしお、 該コンピュヌタを機胜させるこずを特 城ずする、 呜什凊理制埡プログラムを蚘録したコンピュヌタ読取可胜な蚘録媒䜓 ( Referring to the priority of each process calculated / changed by the priority calculation unit, the instruction for the process with the higher priority is preferentially selected and output to the decoder. A computer-readable recording medium (in which an instruction processing control program is recorded) characterized by causing the computer to function as a control unit that controls the operation of the selector.
PCT/JP2003/009635 2003-07-30 2003-07-30 Information processing device, instruction processing control device, instruction processing control method, instruction processing control program, and computer readable recording medium containing the instruction processing control program WO2005013129A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103905783A (en) * 2012-12-25 2014-07-02 杭州海康嚁视数字技术股仜有限公叞 Method and device for performing decoding and displaying on video stream

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Agarwal A. et al., APRIL: A Processor Architecture for Multiprocessing In: Proceedings of the 17th Annual Symposium on Computer Architecture, 1990, pages 104 - 114 *
HIRATA S. et al., "Taju Seigyo Flow Kiko o Sonaeta Shigen Kyoyugata Processor Architecture", Information Processing Society of Japan Kenkyu Hokoku, Vol. 92, No. 48 (92-ARC-94), JP, Information Processing Society of Japan, 1992, pages 9 - 16 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103905783A (en) * 2012-12-25 2014-07-02 杭州海康嚁视数字技术股仜有限公叞 Method and device for performing decoding and displaying on video stream

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