JP2004295195A - Method and device for issuing instruction, central processing unit, instruction issuing program, and computer readable storage medium for storing the program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cause a multithreaded processor to achieve real-time processing through overtaking based on priority of instruction. <P>SOLUTION: An instruction fetching unit 2 fetches instructions from an instruction cache 3 and sends them to an instruction decoding unit 9. The instruction decoding unit 89 decodes the instructions. A reservation station 20 obtains from a register file 1-1 the instructions and the operands needed for executing the instructions. A thread control unit 21 sets the priority of each thread. The reservation station 20 supervises a common data bus 12 if not all the operands needed for executing the instructions are obtained, and fetches, if any, necessary operands. The reservation station 20 selects an entry with the highest priority from among entries where there are all the operands needed for executing the instructions, and sends its instruction and operand to a computing unit 4. The computing unit 4 executes the instructions according to the instruction and the operand. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an instruction issuing method and apparatus, a central processing unit, an instruction issuing program, and a computer-readable storage medium storing the instruction issuing program, and in particular, to various kinds of distributed real-time control of various robots, automobiles, plants, home automation, and the like. TECHNICAL FIELD The present invention relates to an instruction issuing method and apparatus, a central processing unit, an instruction issuing program, and a computer-readable storage medium that stores the instruction issuing method and apparatus, which support real-time processing necessary for realizing the processing by hardware.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as a technique using a multi-thread processor, Patent Literature 1 discloses a technique that independently processes a plurality of instruction flows and flexibly controls processing performance in units of instruction flows. In this multi-thread processor, the priority in each instruction flow is controlled by the instructions in the instruction flow, and when a plurality of instruction issuance requests are output to one functional unit at the same time, the instructions to be issued to the functional unit are given priority. , The processing performance required for each instruction flow is dynamically realized. Note that a thread generally refers to a processing unit or a minimum unit obtained by dividing a process or a task in order to process a certain process or task in parallel. At this time, one process or one task may become one thread without dividing the process or the task.
[Patent Document 1]
JP-A-10-124316
[0003]
[Problems to be solved by the invention]
In a reservation station of a conventional multithread processor, processing is performed irrespective of which thread the instruction belongs to. Therefore, when a plurality of threads are executed simultaneously, the execution time of a certain thread is affected by the execution of another thread, and it becomes difficult to predict the execution time. Therefore, this point is a problem in a system that is strict in time constraints such as real-time processing.
[0004]
In view of the above, the present invention provides real-time processing in a multi-thread processor,
(1) Overtaking by instruction priority and / or
(2) Priority change for each clock,
It is an object of the present invention to enable a thread to execute real-time processing without being affected by other threads.
[0005]
[Means for Solving the Problems]
In the present invention, in particular,
1. Prioritize the instructions to be executed so that higher priority instructions overtake lower priority instructions at the reservation station; and / or
2. Changing the priority of instructions for each clock,
This realizes that a thread performs real-time processing without being affected by another thread.
[0006]
According to a first solution of the present invention,
An instruction issuing device in a multi-thread processor in which a central processing unit executes instructions of a plurality of threads,
A thread control unit for setting a priority for each thread;
A register file storing instructions and operands of a thread to be executed in arithmetic processing and / or memory access processing;
Corresponding to the thread identifier (thread ID), an entry including priority information, an instruction, and data indicating each operand used for executing the instruction is stored, data is received from the register file, and the instruction and the operand are stored. A reservation station to issue,
An operation unit that receives an instruction and an operand issued from the reservation station, performs various operations according to the instruction, and writes an operation result back to the register file;
With
The reservation station,
Means for monitoring an output from the arithmetic unit and, when necessary data which is an unresolved operand in the register file is output as an arithmetic result from the arithmetic unit, capturing the arithmetic result as an operand;
Means for obtaining priority information corresponding to the thread ID from the thread control unit;
Means for sending an instruction of a thread having a high priority according to the priority information to the arithmetic unit, wherein the instruction has all the operands necessary for the execution of the instruction.
The instruction issuing device, wherein the instruction issued from the reservation station to the arithmetic unit is such that the instruction of the thread with the higher priority overtakes the instruction with the lower priority.
[0007]
According to a second solution of the present invention,
An instruction issuing device as described above,
An instruction cache and a data cache for respectively caching instructions and data;
An instruction fetch unit that fetches and decodes instructions from the instruction cache and accesses the register file based on the decoded instructions;
An interface unit for inputting and outputting data to and from an external storage device and / or an input / output device;
A central processing unit having the following is provided.
[0008]
According to a third solution of the present invention,
A register file storing, in correspondence with a thread identifier (thread ID), an entry including priority information, an instruction, and data indicating each operand used for executing the instruction, and storing an operand of a thread to be executed A reservation station for receiving data from the reservation station and issuing instructions and operands; and an operation unit for receiving the instructions and operands issued from the reservation station, performing various operations in accordance with the instructions, and writing the operation results back to the register file. An instruction issuing method using an instruction issuing device in a multi-thread processor, comprising:
The reservation station monitors an output from the arithmetic unit, and when necessary data that is an unresolved operand in the register file is output as an arithmetic result from the arithmetic unit, capturing the arithmetic result as an operand. ,
The reservation station obtaining priority information corresponding to a thread ID from a thread control unit for setting a priority corresponding to each thread;
The reservation station sends an instruction of a thread having a high priority according to priority information to the arithmetic unit, the instruction including all operands necessary for executing the instruction;
And the instruction issuance method from the reservation station to the arithmetic unit is provided such that an instruction of a thread with a higher priority overtakes an instruction with a lower priority. Furthermore, there is provided an instruction issuing program for causing a computer to execute each step described in the third solving means, and a computer-readable storage medium storing the instruction issuing program.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
1. Related technology
As an example, the present embodiment is used on a central processing unit (CPU) of a multi-thread processor such as a responsive multi-threaded processor (Responsive Multi-Threaded (RMT) Processor). Therefore, first, a multi-thread processor having a CPU according to the present embodiment will be described.
[0010]
FIG. 1 shows a configuration diagram of a multi-thread processor that performs out-of-order execution related to the present embodiment. Here, out-of-order execution refers to performing instruction operations in an order different from the order described in the program. Therefore, in the out-of-order execution, as described below, using the reorder buffer and the reservation station, the executable instructions are sequentially sent to the arithmetic unit, and the order is restored in the reorder buffer.
[0011]
This processor has a CPU 101, a memory 200, an I / O 300, and a bus 400. The CPU 101 is connected to the memory 200, the I / O 300, and the like via the bus 400. The CPU 101 includes a register group 1, an instruction fetch unit 2, an instruction cache 3, an arithmetic unit 4, a memory access unit 5, a data cache 6, a bus interface unit 7, a reorder buffer 8, an instruction decode unit 9, a reservation station 10, and an arithmetic bus 11. , A common data bus 12. The register group 1 has a register file 1-1 and a rename register 1-2.
[0012]
As the instruction cache 3 and the data cache 6, for example, elements such as an SRAM and a flip-flop (FF) are used, and although the processing speed of access, reading, writing, and the like is high, the storage capacity is small. On the other hand, as the memory 200 outside the CPU 101, an element such as an SDRAM or a DRAM is used, and the processing speed of access, reading, writing, and the like is slower than that of the cache, but the storage capacity is large.
[0013]
The instruction fetch unit 2 outputs an address (Address) to the instruction cache 3, fetches an instruction (instruction) from the instruction cache 3, and sends the fetched instruction to the instruction decode unit 9. The instruction decode unit 9 decodes the instruction fetched by the instruction fetch unit 2 and reads data necessary for the operation from the register file 1-1 of the register group 1 based on the decoded instruction.
[0014]
The register file 1-1 of the register group 1 includes various registers such as a general-purpose register (GPR), a floating-point register (FPR), a program counter (PC), and a status register (SR). The register file 1-1 stores operands or data required for the currently executed instruction. In the case of a multi-thread processor, a plurality of register files 1-1 exist in parallel. The rename register 1-2 of the register group 1 changes the operand name to resolve the dependency of the operand. The rename register 1-2 outputs the renamed register ID instead of the data when the necessary operand is still being calculated and the result is not obtained. The operand or data output from the register file 1-1 or the rename register 1-2 is sent to the reservation station 10 via the operation bus 11 together with the decoded instruction.
[0015]
The operation bus 11 connects the register file 1-1 or the rename register 1-2 of the register group 1, the reorder buffer 8, and the reservation station 10 in parallel.
[0016]
The reservation station 10 stores, from the register file 1-1 and / or the rename register 1-2, operands or data that are read from the register group 1 according to the decoded instruction and that are necessary for the operation. The reservation station 10 monitors the output from each of the arithmetic units 4 and the memory access unit 5 via the common data bus 12, and obtains necessary data from the arithmetic unit 4 for operands that have not been resolved in the register file 1-1. When output, capture the result as an operand. The reservation station 10 sends to the arithmetic unit 4 or the memory access unit 5 connected in order from an instruction having all the operands. In the case of a memory access instruction such as a load (Load) or a store (Store), the instruction and the operand are stored in the reservation station 10 connected to the memory access unit 5.
[0017]
The arithmetic unit 4 uses necessary data and instructions from the instruction cache 3, the data cache 6, or the memory 200 via the reservation station 10 or the register group 1 according to the principle of locality. The arithmetic unit 4 executes an operation according to the instruction received from the reservation station 10 and outputs the calculated result to the common data bus 12.
[0018]
Further, the memory access unit 5 accesses the data cache 6 to execute load or store, and outputs the data to the common data bus 12. In the case of a store instruction, the memory access unit 5 sends an address and data to the data cache 6, and stores the data in the data cache 6. In the case of a load instruction, the memory access unit 5 sends an address to the data cache 6 and reads data from the data cache 6. The read data is written back to the register file 1-1 via the common data bus 12. At this time, if there is no data to be sought in the data cache 6, it is read from the memory 200 via the bus interface unit 7. The bus interface unit 7 is a unit that connects the instruction cache 3 and the data cache 6 to the memory 200 and the I / O 300 outside the CPU via the bus 400 and inputs and outputs data between the inside and the outside of the CPU.
[0019]
The common data bus 12 transfers the operation result of the operation unit 4 and the execution result of loading or storing of the memory access unit 5 to the register file 1-1 or the rename register 1-2, the reorder buffer 8, and the reservation station 10.
[0020]
The reorder buffer 8 restores the order of the instructions executed out-of-order by the operation units 4 to the original order, and then writes the operation result to the actual register file 1-1.
[0021]
FIG. 2 shows a format of the entry of the reservation station 10. The entry of the reservation station 10 includes a busy bit, an operation, a set of one or more valid bits and data, (valid0 and data0, valid1 and data1,...).
[0022]
The "busy bit" indicates whether the entry is valid or invalid, that is, whether or not the entry has an instruction. The "instruction" is an instruction to be operated by the arithmetic unit 4 or executed by the memory access unit 5. Here are the instructions for “Data” indicates an operand necessary for executing the instruction, and “valid bit” indicates whether or not the value is valid for the corresponding operand used in the operation. The reservation station 10 can set the number of pairs of valid bits and data according to the instruction. The reservation station 10 can use the valid bit to determine that all the operands have been prepared.
[0023]
3 and 4 show flowcharts (1) and (2) of processing for issuing an instruction to the arithmetic unit 4 in the reservation station 10. FIG. 3 shows steps from step S101 to step S109, and FIG. 4 shows steps from step S111 to step S117. In the instruction issuing process, after processing the steps from step S101 to step S109, the steps from step S111 to step S117 are processed.
[0024]
The reservation station 10 receives the data read from the register file 1-1, and creates and stores an entry for storing data necessary for executing the instruction. The reservation station 10 stores one or a plurality of such entries inside.
[0025]
When the instruction issuance process is started, a repetitive loop process from step S101 to step S109 is performed for all entries of the reservation station 10. In the repetitive loop processing, first, the reservation station 10 determines whether or not all the operands necessary for executing the instruction indicated by the entry are provided for each entry (S103). The reservation station 10 may determine the required number of operands according to the instruction, or may determine the required number or area for each instruction in advance in the entry. The reservation station 10 determines, for example, whether all the valid bits of each entry are valid. In step S103, if all the data necessary for the execution of the instruction has been obtained as operands, for example, if all the valid bits for all the operands necessary for the execution of the corresponding instruction have been set, the process proceeds to step S109. On the other hand, if the necessary operands are not available, for example, if all the valid bits have not been set (S103), the reservation station 10 has not obtained the necessary data yet, and proceeds to step S105. In this case, the reservation station 10 monitors the operation result flowing from the common data bus 12, and when necessary data comes (S105), fetches it as an operand in the entry data and sets the corresponding valid bit (S105). S107). On the other hand, if the necessary data does not come (S105), the process proceeds to step S109.
[0026]
After repeating the processing from step S101 to step S109 for all entries of the reservation station 10, the process proceeds to step S111 to continue the processing.
[0027]
Next, the processing from step S111 to step S117 will be described with reference to FIG.
In step S111, the reservation station 10 determines whether or not there is an entry having all the operands necessary for executing the instruction (S111). For example, as described above, the reservation station 10 can determine that all valid bits are valid. If there is no entry with all the operands, the instruction issuance ends. On the other hand, when there is an entry having all the operands, the reservation station 10 determines whether there is one or more such entries (S113). For example, when all the valid bits are set, all the operands necessary for executing the instruction are complete.
[0028]
If there is one entry with all the operands, the reservation station 10 sends the instruction and operand of the entry to the arithmetic unit 4 (S115). On the other hand, when all of the plurality of entries can be calculated, the reservation station 10 sends the oldest entry to the computing unit 4 (S117). The entry which is not selected is kept from issuing until the processing clock for issuing the next instruction.
[0029]
2. CPU with instruction issuing device of multiple threads according to priority
In the above-mentioned “1. Related Art”, the operation of the reservation station 10 mainly includes a case where operands are aligned and an instruction that can be operated is sent to the arithmetic unit 4 so that a plurality of instructions can be operated simultaneously. Described running from the oldest instruction. In the following, description will be given of instruction issuance for executing instructions of a thread with the highest priority first when a plurality of instructions can be operated simultaneously.
[0030]
FIG. 5 shows a configuration diagram of a multi-thread processor that performs out-of-order execution using priority.
This processor has a CPU 102, a memory 200, an I / O 300, and a bus 400. The CPU 102 is connected to the memory 200, the I / O 300, and the like via the bus 400. The CPU 102 includes a register group 1, an instruction fetch unit 2, an instruction cache 3, an arithmetic unit 4, a memory access unit 5, a data cache 6, a bus interface unit 7, a reorder buffer 8, an instruction decode unit 9, an arithmetic bus 11, and a common data bus. 12, a reservation station 20, and a thread control unit 21. The register group 1 includes a register file 1-1 and a rename register 1-2.
[0031]
The instruction fetch unit 2 outputs an address (Address) to the instruction cache 3, fetches an instruction (instruction) from the instruction cache 3, and decodes the instruction with the instruction decode unit 9.
[0032]
The thread control unit 21 sets the priority of each thread. In addition, the thread control unit 21 sends the set priority to all the reservation stations 20. The thread control unit 21 holds a predetermined number of data for identifying the priority of each thread. For this purpose, the thread control unit 21 can include, for example, a memory that stores priority information corresponding to each thread. In addition, the thread control unit 21 can perform execution and stop of a thread, control of replacement with a context cache that caches a context, and the like. Here, the context is information for execution of each thread stored in a storage unit (eg, register file 1-1) such as a general-purpose register, a floating-point register, a program counter, and a status register, or the current execution. Refers to the inside state.
[0033]
As described above, the reservation station 20 stores the operands or data necessary for the operation, read from the register file 1-1 and / or the rename register 1-2 according to the decoded instruction.
[0034]
The reservation station 20 monitors the output from each of the arithmetic units 4 and the memory access unit 5 via the common data bus 12, and obtains necessary data from the arithmetic unit 4 for operands that have not been resolved in the register file 1-1. When output, capture the result as an operand. Further, the reservation station 20 receives the priority information set from the thread control unit 21 or accesses the thread control unit 21 to obtain the priority information of a predetermined thread. The reservation station 20 may store a table storing priority information for each thread in an internal register. The reservation station 20 sends to the arithmetic unit 4 or the memory access unit 5 connected in order from the instruction having the highest priority among instructions having all operands. In the case of a memory access instruction such as load or store, the instruction and the operand are sent to the reservation station 20 connected to the memory access unit 5.
[0035]
As described above, the configuration and operation of each of the other units are the same as the configuration and operation of each unit of the CPU 101 shown in FIG.
[0036]
FIG. 6 shows a format of the entry of the reservation station 20. In this entry, instruction priority information (priority) is added to the entry of the reservation station 10.
[0037]
The entries of the reservation station 20 include a busy bit, a thread ID (thread ID), priority information (priority), an instruction (operation), a set of one or more valid bits and data, (valid0 and data0, valid1). , And data1,...).
[0038]
The busy bit, instruction, valid bit, and data are the same as those described in FIG. “Thread ID” indicates which thread the instruction of the entry belongs to. By omitting the thread ID and using a table storing information for identifying each entry for each thread ID, the reservation station 20 can also appropriately grasp each thread ID. The "priority information" indicates the priority of an instruction, and indicates whether the thread control unit 21 has received an instruction in the reservation station 20, obtained an operand, every processing clock, and / or when all operands have been prepared. Set from. The reservation station 20 checks the value of the priority for each thread and changes the priority information based on the settings of the register and the thread control unit 21 specified separately for each thread. In the present embodiment, the thread control unit 21 prepares, for example, an 8-bit register for each thread, and specifies the priority information as a value of 256 levels. For example, this value can be set such that the higher (larger) the higher the priority is, and the lower (small) the lower the priority.
[0039]
FIGS. 7 and 8 show flowcharts (1) and (2) of processing for issuing an instruction to the arithmetic unit 4 in the reservation station 20 using the priority. FIG. 7 shows steps from step S201 to step S209, and FIG. 8 shows steps from step S211 to step S217. In the instruction issuing process, after processing the steps from step S201 to step S209, the steps from step S211 to step S217 are processed.
[0040]
The reservation station 20 stores data and instructions sent from the register file 1-1, and creates and stores entries for storing data necessary for executing the instructions. The reservation station 20 stores one or more such entries internally.
[0041]
When the instruction issuance process is started, a repetitive loop process from step S201 to step S209 is performed on all entries of the reservation station 20. In the repetitive loop processing, first, the reservation station 20 determines whether or not all the operands necessary for executing the instruction indicated by the entry are provided for each entry (S203). The reservation station 20 may determine the required number of operands according to the instruction, or may determine the required number or area for each instruction in advance in the entry. The reservation station 20 determines, for example, whether all the valid bits of each entry are valid. If all the operands necessary for the execution of the instruction are available in step S203, for example, if all the valid bits for all the operands necessary for the execution of the corresponding instruction are set, the process proceeds to step S208. On the other hand, if the necessary operands are not available, for example, if all the valid bits are not set (S203), the reservation station 20 has not yet obtained the data necessary for executing the instruction of the entry. , And the process proceeds to step S205. Here, the reservation station 20 monitors the common data bus 12 and, when necessary data comes (S205), takes it as an operand in an entry and sets a corresponding valid bit (S207). On the other hand, if the necessary data does not come (S205), the process proceeds to step S208.
[0042]
Next, the reservation station 20 updates the priority information from the thread ID of each entry (S208). For example, since the reservation station 20 has a field indicating which thread belongs to each entry, that is, a thread ID, the reservation station 20 can determine which thread the entry belongs to by referring to the field. Further, in the thread control unit 21, priority information is specified for each thread ID by a memory or the like. Therefore, the reservation station 20 obtains the set priority by accessing the memory of the thread control unit 21 or the like. The priority information of the corresponding entry can be updated. Conversely, the thread control unit 21 may obtain the thread ID of the entry of each reservation station 20 and give priority information corresponding to the thread ID, so that the reservation station 20 can obtain the priority information. . The reservation station 20 obtains the data of the priority from the thread control unit 21 at an appropriate timing, stores the priority information in the internal memory corresponding to the thread ID, and refers to the priority information. Thus, the priority information may be obtained according to the thread ID.
[0043]
The reservation station 20 repeats the processing from step S201 to step S209 for all entries, and then proceeds to step S211.
[0044]
Next, the processing from step S211 to step S217 will be described with reference to FIG.
In step S211, the reservation station 20 determines whether there is an entry in which all the operands necessary for executing the instruction are present (S211). For example, as described above, the reservation station 20 can determine that all valid bits are valid. If there is no entry with all the operands, the instruction issuance ends. On the other hand, when there is an entry having all the operands, the reservation station 20 determines whether there is one or more such entries (S213). For example, as described above, when all the valid bits are set, the operands required for executing the instruction are complete.
[0045]
When there is one entry having all the operands, the reservation station 20 sends the instruction and the operand of the entry to the arithmetic unit 4 (S215). On the other hand, if the plurality of entries can be operated with all operands being the same, the reservation station 20 compares the priority information of each entry in which the instruction can be executed, and selects an entry having a higher priority (S217). ). Here, if there are a plurality of entries having the same or substantially equal priorities, the reservation station 20 selects an older entry or an entry in a predetermined order to select the arithmetic unit 4. Send to It should be noted that the entry which is not selected is issued until the processing clock of the next instruction issuance.
[0046]
In this way, the reservation station 20 can preferentially send an entry having a higher priority value to the arithmetic unit 4, whereby an instruction having a higher priority is operated first. Note that the process of step S208 may be performed before step S203.
[0047]
3. Multi-thread instruction issuing device and CPU using priority and counter
In this embodiment, an instruction issuance for issuing an instruction to be executed first based on a priority and a counter will be described. The configuration and operation of the instruction issuing device and the CPU of this embodiment are as shown in FIG. 5 and the description thereof, and the entries used in the reservation station 20 are different.
[0048]
FIG. 9 shows a format of an entry to which a counter of the reservation station 20 is added.
[0049]
The entry includes a busy bit, a thread ID (thread ID), priority information (priority), an instruction (operation), a set of one or more valid bits and data, (valid0 and data0, valid1 and data1, ..) And a counter. The busy bit, thread ID, priority information, instruction, valid bit, and data are the same as those described in FIG. 2 or FIG.
The counter is, for example, a counter value that is reset when an instruction is entered into an entry by the reservation station 20, and is counted up every processing clock for issuing an instruction.
[0050]
FIGS. 10 and 11 show flowcharts (1) and (2) of issuing an instruction to the arithmetic unit 4 in the reservation station 20 using a counter. FIG. 10 shows steps from step S201 to step S209, and FIG. 11 shows steps from step S211 to step S307. In the instruction issuing process, after processing the steps from step S201 to step S209, the steps from step S211 to step S307 are processed.
[0051]
In the flowcharts of FIGS. 10 and 11, the processes in the steps having the same step numbers as those of the flowcharts of FIGS. 7 and 8 are as described above. In the following description, mainly the parts different from the processing of steps S301 to S307 of FIGS. 10 and 11 and the order of the processing of FIGS. 10 and 11 and the order of FIGS. 7 and 8 will be described.
[0052]
As described above, the reservation station 20 stores data and instructions sent from the register file 1-1, and creates and stores entries for storing data necessary for executing the instructions. The reservation station 20 stores one or more such entries internally.
[0053]
When the instruction issuance process is started, a repetitive loop process from step S201 to step S209 is performed on all entries of the reservation station 20. In the repetitive loop processing, first, the reservation station 20 determines, for each entry, whether the entry is valid or invalid (for example, whether or not an instruction is stored) (S301). The reservation station 20 determines whether the entry is valid or invalid based on, for example, a busy bit of each entry. If the entry is invalid in step S301, the process proceeds to step S209. On the other hand, if the entry is valid, the reservation station 20 increases the counter value of the entry by one (S303). The counter is reset, for example, when an instruction is entered into an entry, and thereafter, is incremented every processing clock for issuing the instruction.
[0054]
Next, as described above, the reservation station 20 updates the priority information from the thread ID of each entry (S208). Then, as described above, the reservation station 20 determines whether all the operands necessary to execute the instruction indicated by each entry are available (S203), and all the operands necessary to execute the instruction are available. If there is, the process proceeds to step S209, and a loop process is repeatedly executed from step S201. On the other hand, if the necessary operands are not available (S203), the reservation station 20 monitors the common data bus 12 and, when necessary data comes (S205), fetches the data as an operand into the data of the entry and reads the corresponding valid bit. Is set (S207). On the other hand, if the necessary data does not come (S205), the process proceeds to step S209, and the loop processing is repeatedly executed from step S201.
[0055]
Next, the processing from step S211 to step S307 will be described with reference to FIG.
In step S211, as described above, the reservation station 20 determines whether there is an entry having all the operands necessary for executing the instruction (S211). If there is no entry with all the operands, the instruction issuance ends. On the other hand, when there is an entry having all the operands, the reservation station 20 determines whether there is one or more such entries (S213).
[0056]
When there is one entry having all the operands, the reservation station 20 sends the instruction and the operand of the entry to the arithmetic unit 4 (S215). On the other hand, when the plurality of entries can be operated with all the operands being the same, the reservation station 20 compares the priority information of each entry in which the instruction can be executed, and selects an entry having a higher priority (S305). ). Further, when there are a plurality of entries having the highest priority, the reservation station 20 sends the instruction of the entry having the largest counter value to the arithmetic unit 4 (S305). In the case where a plurality of entries can be calculated, the reservation station 20 compares, for example, the priority information for the high-order bit and the concatenated value of the counter for the low-order bit, and selects an instruction having a larger numerical value. Is also good. The entry that is not selected is issued until the processing clock for issuing the next instruction. When the processing in step S215 or S305 is completed, the reservation station 20 clears the counter value of the entry that sent the instruction to the arithmetic unit 4, changes the busy bit, and invalidates the entry (S307). Note that the process of step S208 may be performed after step S207.
As a result, an instruction with a higher priority is selected, and if the priorities are equal, an older instruction is selected.
[0057]
4. Other
An instruction issuing method or an instruction issuing apparatus / system of the present invention includes an instruction issuing program for causing a computer to execute each procedure, a computer-readable recording medium on which the instruction issuing program is recorded, and an internal memory of the computer including the instruction issuing program. The program can be provided by a program product that can be loaded into a computer, a computer such as a server including the program, or the like.
[0058]
【The invention's effect】
According to the present invention, real-time processing is performed in a multi-thread processor,
(1) Overtaking by instruction priority and / or
(2) Priority change for each clock,
By using such a technique, execution of a real-time process of a thread can be performed without being affected by another thread.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a multi-thread processor that performs out-of-order execution related to the present embodiment.
FIG. 2 is a format of a reservation station 10 entry.
FIG. 3 is a flowchart (1) of issuing an instruction to a computing unit 4 in the reservation station 10.
FIG. 4 is a flowchart (2) of issuing an instruction to a computing unit 4 in the reservation station 10.
FIG. 5 is a configuration diagram of a multi-thread processor that performs out-of-order execution using priority.
FIG. 6 shows a format of the reservation station 20 entry.
FIG. 7 is a flowchart (1) of issuing an instruction to the arithmetic unit 4 in the reservation station 20 using priority.
FIG. 8 is a flowchart (2) of issuing an instruction to the arithmetic unit 4 in the reservation station 20 using the priority.
FIG. 9 is a format of an entry to which a counter of the reservation station 20 is added.
FIG. 10 is a flowchart (1) of issuing an instruction to the arithmetic unit 4 in the reservation station 20 using a counter.
FIG. 11 is a flowchart (2) of issuing an instruction to the arithmetic unit 4 in the reservation station 20 using a counter.
[Explanation of symbols]
1 register group
1-1 Register file
1-2 Rename register
2 Instruction fetch unit
3 Instruction cache
4 arithmetic unit
5 Memory access unit
6 Data cache
7 Bus interface unit
8 Reorder buffer
9 Instruction decode unit
10 Reservation Station
11 arithmetic bus
12 Common data bus
20 reservation stations
21 Thread control unit
101, 102 CPU
200 memory
300 I / O
400 bus

Claims (13)

An instruction issuing device in a multi-thread processor in which a central processing unit executes instructions of a plurality of threads,
A thread control unit for setting a priority for each thread;
A register file storing instructions and operands of a thread to be executed in arithmetic processing and / or memory access processing;
Corresponding to the thread identifier (thread ID), an entry including priority information, an instruction, and data indicating each operand used for executing the instruction is stored, data is received from the register file, and the instruction and the operand are stored. A reservation station to issue,
An operation unit that receives an instruction and an operand issued from the reservation station, performs various operations according to the instruction, and writes an operation result back to the register file;
With
The reservation station,
Means for monitoring an output from the arithmetic unit and, when necessary data which is an unresolved operand in the register file is output as an arithmetic result from the arithmetic unit, capturing the arithmetic result as an operand;
Means for obtaining priority information corresponding to the thread ID from the thread control unit;
Means for sending an instruction of a thread having a high priority according to priority information to the arithmetic unit in accordance with priority information. The instruction issuance apparatus wherein the instruction of the high-priority thread overtakes the instruction of the low-priority instruction. Means for creating an entry, wherein the reservation station stores operands read from the register file based on the decoded instruction, and further includes a valid bit indicating that data is valid for each operand; ,
The reservation station fetches, for each entry stored in the reservation station, necessary data as an operand from the operation result of the arithmetic unit until all the operands necessary for executing the instruction are obtained, and a valid bit corresponding to the data. Means for updating each entry by setting and obtaining and setting a priority by referring to the thread control unit according to the thread ID for each entry;
Means for determining an operable entry in which all of the valid bits are set to the operand, and
When a plurality of entries having the same operand can be operated, the reservation station compares the priorities of the entries, selects an entry having a higher priority, and sends the instruction of the entry and the instruction of the entry to the arithmetic unit. 2. The instruction issuing device according to claim 1, further comprising: an operand sending unit. 2. The instruction issuing apparatus according to claim 1, wherein the reservation station updates the priority of the instruction of the thread at each entry update or instruction issuance processing clock. Means for resetting a counter when an instruction is input or created in an entry, and counting up the counter for each processing clock that updates the entry or every processing clock that issues the instruction; and
Means for, when there are a plurality of high-priority entries, selecting an entry having a large value according to a counter and issuing the instruction and operand to the arithmetic unit;
The instruction issuing device according to claim 1, further comprising: 2. The instruction issuing device according to claim 1, further comprising a memory access unit that receives instructions and operands from the reservation station and executes loading or storing to the register file or the data cache. A plurality of sets of the reservation station and the computing unit are provided,
A reorder buffer for returning the order of the instructions calculated out-of-order by the respective arithmetic units to the original order, and writing the operation result returned to the original order to the register file;
2. The instruction issuing device according to claim 1, further comprising: a common data bus for supplying an output of each of the arithmetic units to the reservation station, the register file, and the reorder buffer. The instruction issuing device according to claim 1, wherein the reservation station and / or the thread control unit includes a memory storing priority information corresponding to a thread ID. An instruction issuing device according to any one of claims 1 to 7,
An instruction cache and a data cache for respectively caching instructions and data;
An instruction fetch unit that fetches and decodes instructions from the instruction cache and accesses the register file based on the decoded instructions;
An interface unit for inputting and outputting data to and from an external storage device and / or an input / output device;
Central processing unit equipped with. A register file storing, in correspondence with a thread identifier (thread ID), an entry including priority information, an instruction, and data indicating each operand used for executing the instruction, and storing an operand of a thread to be executed A reservation station for receiving data from the reservation station and issuing instructions and operands; and an operation unit for receiving the instructions and operands issued from the reservation station, performing various operations in accordance with the instructions, and writing the operation results back to the register file. An instruction issuing method using an instruction issuing device in a multi-thread processor, comprising:
The reservation station monitors an output from the arithmetic unit, and when necessary data that is an unresolved operand in the register file is output as an arithmetic result from the arithmetic unit, capturing the arithmetic result as an operand. ,
The reservation station obtaining priority information corresponding to a thread ID from a thread control unit for setting a priority corresponding to each thread;
Sending the instruction of the thread having a higher priority according to the priority information to the arithmetic unit, wherein the reservation station is an instruction having all the operands necessary for executing the instruction. The instruction issuance method according to claim 1, wherein an instruction of a thread having a higher priority overtakes an instruction of a lower priority. Creating an entry, wherein the reservation station stores data read from the register file based on the decoded instruction, and further includes a valid bit indicating that the data is valid for each operand; ,
The reservation station, for each entry stored in the reservation station, fetches the operation result of the operation unit as an operand until all operands necessary for instruction execution are obtained, sets a valid bit corresponding to the data, Updating each entry by obtaining and setting a priority by referring to the thread control unit according to the thread ID for each entry;
The reservation station determining an entry in which all the valid bits are set as an operable entry having all operands;
When a plurality of entries having the same operand can be operated, the reservation station compares the priorities of the entries, selects an entry having a higher priority, and sends the instruction of the entry and the instruction of the entry to the arithmetic unit. The instruction issuing method according to claim 9, further comprising a step of sending an operand. The reservation station resetting a counter when an instruction is input or created in an entry, and counting up the counter every processing clock for updating the entry or every processing clock for issuing the instruction thereafter;
The reservation station, when there are a plurality of entries having a high priority, selecting an entry having a large value according to a counter, and issuing the instruction and the operand to the arithmetic unit;
The method according to claim 9, further comprising: Corresponding to the thread identifier (thread ID), an entry including priority information, an instruction, and data indicating each operand used to execute the instruction is stored, and the instruction and operand of the thread to be executed are stored. A reservation station for receiving data from the register file and issuing instructions and operands; and an arithmetic unit for receiving the instructions and operands issued from the reservation station, performing various operations in accordance with the instructions, and writing the operation results back to the register file. An instruction issuing program for causing a computer to execute each of the following steps using an instruction issuing device in a multi-thread processor,
The reservation station monitors an output from the arithmetic unit, and when necessary data that is an unresolved operand in the register file is output as an arithmetic result from the arithmetic unit, capturing the arithmetic result as an operand. ,
The reservation station obtaining priority information corresponding to a thread ID from a thread control unit for setting a priority corresponding to each thread;
Sending the instruction to the arithmetic unit, which is an instruction having all the operands necessary for the execution of the instruction and having a high priority thread in accordance with priority information, to the computer. Instruction issuing program. A register file storing, in correspondence with a thread identifier (thread ID), an entry including priority information, an instruction, and data indicating each operand used for executing the instruction, and storing an operand of a thread to be executed A reservation station for receiving data from the reservation station and issuing instructions and operands; and an operation unit for receiving the instructions and operands issued from the reservation station, performing various operations in accordance with the instructions, and writing the operation results back to the register file. A computer-readable storage medium storing an instruction issuing program for causing a computer to execute each of the following steps using an instruction issuing device in a multi-thread processor,
The reservation station monitors an output from the arithmetic unit, and when necessary data that is an unresolved operand in the register file is output as an arithmetic result from the arithmetic unit, capturing the arithmetic result as an operand. ,
The reservation station obtaining priority information corresponding to a thread ID from a thread control unit for setting a priority corresponding to each thread;
Sending the instruction to the arithmetic unit, which is an instruction having all the operands necessary for the execution of the instruction and having a high priority thread in accordance with priority information, to the computer. A computer-readable storage medium storing an instruction issuing program.

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