WO2005008695A2 - Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements - Google Patents
Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements Download PDFInfo
- Publication number
- WO2005008695A2 WO2005008695A2 PCT/IB2004/051234 IB2004051234W WO2005008695A2 WO 2005008695 A2 WO2005008695 A2 WO 2005008695A2 IB 2004051234 W IB2004051234 W IB 2004051234W WO 2005008695 A2 WO2005008695 A2 WO 2005008695A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- semiconductor device
- inductive element
- tilling
- structures
- tilling structures
- Prior art date
Links
- 230000001939 inductive effect Effects 0.000 title claims abstract description 123
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000005516 engineering process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 44
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- 238000013461 design Methods 0.000 claims description 3
- 230000010354 integration Effects 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 73
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- -1 e.g. copper Chemical class 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/008—Electric or magnetic shielding of printed inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to processing of inductive and capacitive elements in advanced semiconductor technologies with minimum pattern density requirements as well as semiconductor devices including the elements.
- Conventional semiconductor devices typically comprise a semiconductor substrate, generally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns.
- An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter- wiring spacings.
- conductive patterns on different layers are electrically connected by a conductive plug filling a via hole through an insulating layer.
- Semiconductor chips comprising five or more levels of moralization are becoming more prevalent as device geometries shrink to sub-micron levels. Because of miniaturization of electronics over the last few years, it has become possible to integrate more functionality in a smaller volume.
- Tilling structures improve manufacturability on a number of points: 1) The improved planarity enlarges the process window of lithography an processing of subsequent layers. 2) The uniformity of Chemical Mechanical Polishing (CMP) removal rate is improved, and becomes independent of the patterns (mask-set) that is used. 3) The integrity of low-k dielectrics is improved by avoiding large areas of this (often fragile) material.
- CMP Chemical Mechanical Polishing
- High quality inductors preferably have a large quality factor (Q), a sufficiently large inductance, a relatively low resistance and a low capacitive coupling to the substrate onto which the inductor is formed.
- Q quality factor
- the above objective is accomplished by a method and device according to the present invention. It is an advantage of the present invention that the high quality inductive element can be combined with a high quality capacitive element.
- the present invention provides a semiconductor device comprising a plurality of layers, the semiconductor device comprising: - a substrate having a first major surface, - an inductive element fabricated on the first major surface of the substrate, the inductive element comprising at least one conductive line, and - a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element. It is an advantage of the above semiconductor device that, by using such tilling structures, an inductive element with a higher quality factor is obtained.
- the plurality of tilling structures are preferably arranged in a pattern so as to obtain a good quality factor, preferably the best quality factor possible, for the inductive element processed with minimum pattern density requirements.
- the tilling structures are made from tilling structure material, such as metal for example.
- the plurality of tilling structures may be arranged in a pattern so that the amount of tilling structure material in an area closer to the inductive element, where the magnetic field is higher, is smaller than the amount of tilling structure material in an area farther away from the inductive element. This way, a high density pattern is obtained in the center of the coil and a low density pattern is obtained close to the inductor path, which pattern will less disturb the quality factor of the inductive element.
- the tilling structures may be located at different layers, tilling structures at each layer being arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element.
- the geometrical pattern of tilling structures at two different layers may be different in shape and/or orientation, or it may be the same.
- the tilling structures at different layers may be electrically connected to each other.
- the tilling structures may be connected to a DC potential.
- the DC potential may be ground potential.
- the tilling structures may be a plurality of slender elongate elements, having a finger-shape for example. Alternatively, the tilling structures may be a plurality of substantially triangular elements.
- the elements of the tilling structures may be locally oriented perpendicular to the at least one conductive line of the inductive element.
- the geometrical pattern in at least one layer may be a radial pattern.
- a semiconductor device according to the present invention may furthermore comprise a ground shield for shielding the inductive element from a further layer.
- the further layer may be the substrate.
- the semiconductor device may furthermore comprise connection means electrically connecting the plurality of tilling structures with the ground shield without creating a conductive loop.
- the conductive line of the inductive element may be arranged as a spiral.
- the conductive line of the inductive element is arranged as a single turn inductor.
- the tilling structures may be formed in a region other than a region directly below the inductive element.
- a semiconductor device may furthermore be provided with a further passive element, such as a capacitive element for example.
- the capacitive element may comprise two capacitor electrodes, at least one of the capacitor electrodes being formed by a plurality of tilling structures.
- a capacitor electrode formed by a plurality of tilling structures may lead to a density of conductive material, such as metal or polysilicon, possibly suicided polysilicon, or active region, in the inductor vicinity respecting the design rules of advanced IC technologies.
- One capacitor electrode of the capacitive element may be formed by the ground shield.
- the integration of the capacitive element with the inductive element may be optimized to respect the metal pattern density in advanced silicon technologies.
- the distance between the capacitive element and the inductive element may be large enough to avoid a dominant fringe coupling between them.
- the distance between the capacitive element and the inductive element in a direction substantially parallel with the first major surface of the substrate may be large compared to the distance between the capacitor plates in a direction substantially perpendicular to the first major surface of the substrate, for example twice that distance or more.
- the distance between the capacitive element and the inductive element in a direction substantially parallel with the first major surface of the substrate may large compared to the distance between the inductive element and a ground shield in a direction substantially perpendicular to the first major surface of the substrate, for example twice that distance or more.
- the present invention provides a method for providing an inductive element in a semiconductor device comprising a plurality of layers, the method comprising: - providing a substrate having a first major surface, - forming an inductive element above the first major surface of the substrate, the inductive element comprising at least one conductive line, - providing a plurality of tilling structures in at least one layer, wherein the plurality of tilling structures are electrically connected together and are arranged in a geometrical pattern so as to substantially inhibit an inducement of an image current in the tilling structures by a current in the inductive element.
- Fig. 1 is a schematic partially transparent top view of semiconductor device comprising a single-turn inductive element and a plurality of finger-like tilling structure pattern layers, of which only one is visible, according to an embodiment of the present invention.
- Fig. 2 is a vertical cross-section of the semiconductor device of Fig. 1.
- Fig. 3 is a schematic top view of a semiconductor device comprising a single- turn inductive element and a radial tilling structure pattern according to a second embodiment of the present invention.
- Fig. 4 is a schematic top view of a semiconductor device comprising a dual- turn inductive element and a tilling structure pattern according to a third embodiment of the present invention.
- Fig. 1 is a schematic partially transparent top view of semiconductor device comprising a single-turn inductive element and a plurality of finger-like tilling structure pattern layers, of which only one is visible, according to an embodiment of the present invention.
- Fig. 2 is a vertical cross-section of the semiconductor device of Fig. 1.
- FIG. 5 is a schematic top view of a semiconductor device comprising a single- turn inductive element and a tilling structure pattern according to a fourth embodiment of the present invention.
- Fig. 6 is a schematic top view of an inductive element comprising a meander inductor according to a further embodiment of the present invention.
- Fig. 7 and Fig. 8 illustrate other embodiments of tilling structure patterns for use according to the present invention.
- Fig. 9 illustrates yet another embodiment of a tilling structure pattern with a single-turn inductive element according to an embodiment of the present invention.
- Fig. 10 is a top view of a capacitor patterned into an inductor area in accordance with a further embodiment of the present invention.
- Fig. 11 is a vertical cross-section of the devices of Fig. 10.
- Fig. 10 is a top view of a capacitor patterned into an inductor area in accordance with a further embodiment of the present invention.
- Fig. 11 is a vertical cross-section of the devices of
- Fig. 12 and Fig. 13 illustrate a further embodiment of a capacitor patterned into an inductor area in accordance with a further embodiment of the present invention.
- Fig. 14 illustrates a fringe capacitor which may be used in the inductor area according to a further embodiment of the present invention.
- the same reference Figs refer to the same or analogous elements.
- first, second, third and the like in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein. Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
- a semiconductor device comprising an inductive element is provided on a substrate, the semiconductor device comprising a plurality of layers.
- the term "substrate” may include any underlying material or materials that may be used, or upon which a device, a circuit or an epitaxial layer may be formed.
- this "substrate” may include a semiconductor substrate such as e.g. a doped silicon, a gallium arsenide (GaAs), a gallium arsenide phosphide (GaAsP), an indium phosphide (InP), a germanium (Ge), or a silicon germanium (SiGe) substrate.
- the "substrate” may include for example, an insulating layer such as a Si0 2 or an Si 3 N 4 layer in addition to a semiconductor substrate portion.
- the term substrate also includes silicon-on-glass, silicon-on sapphire substrates.
- the term “substrate” is thus used to define generally the elements for layers that underlie a layer or portion of interest.
- the "substrate” may be any other base on which a layer is formed, for example a glass or metal layer.
- the present invention may be implemented based on other semiconductor material systems and that the skilled person can select suitable materials as equivalents of the dielectric and conductive materials described below.
- an inductive element may be a planar or a non-planar single- turn inductor, or a planar or non-planar spiral inductor comprising a plurality of turns.
- the shape of the inductive element may be circular, square, hexagonal, octagonal, meander- shaped, or the inductive element may have any suitable other shape.
- the wiring of the inductor may extend over two or more metal layers, usually top metal layers, these top metal layers being the metal layers furthest away from the substrate.
- the size of the spiral inductor may be hundreds of microns square or less. For present technologies it is typically between 40 ⁇ m 2 and 500 ⁇ m 2 .
- the inductive element may comprise a single conductive line or a plurality of conductive line segments.
- a plurality of conductive and insulating layers may be provided between the substrate and the inductive element. Also, if the inductive element extends over two or more metal layers, then in between two layers of an inductive element at least one insulating layer is provided. In at least one layer of the semiconductor device, dummy elements or tilling structures are provided. These tilling structures may be used to prevent dishing and/or delamination when carrying out a polishing process such as CMP. Contrary to the dummy structures known from the prior art, which are small pillars separated from each other, all or significant parts of the tilling structures according to the present invention are electrically connected to each other and are arranged in a geometrical pattern so as to form a tilling structure pattern.
- the tilling structure pattern has a shape such that it substantially inhibits an inducement of an image current in the tilling structure pattern due to current flowing through the conductor of the inductive element.
- the tilling structure pattern may for example be a grating composed of a collection of locally isolated conductive lines locally separated by slots. All conductive lines of the tilling structure pattern are electrically connected to each other and to a DC voltage, for example to ground (0 Volts).
- the conductive lines of the tilling structure pattern preferably do not cross the inductor path(s).
- Fig. 1 shows a partially transparent top view of a semiconductor device 10 according to the present invention.
- the semiconductor device 10 is built of a plurality of layers, and comprises an inductive element 11.
- Fig. 1 consists of a single loop conductive element. However, the invention is not limited thereto.
- a plurality of tilling structures are provided at the inside area of the inductive element 11, a plurality of tilling structures are provided.
- the tilling structures consist of elongate metal strips 12, which are connected to each other by means of an interconnection strip 13, thus forming a finger-like or comb-like tilling structure pattern 14.
- Fig. 2 illustrates a vertical cross-section of the semiconductor device 10 of Fig. 1, at a position indicated with II-IF in Fig. 1.
- a plurality of layers are provided on a substrate 20. Those layers comprise conductive and insulating layers.
- the tilling structure patterns 14 are formed in a plurality of subsequent metal layers Ml, M2, M3, M4. In fact the tilling structure patterns 14 may be formed in every layer where they are needed.
- Table 1 An example of a 5 metal layer process according to the present invention is shown in Table 1 hereunder.
- the inductive element 11 is formed by means of metal 5, the topmost metal layer.
- a plurality of tilling structure pattern layers are provided, consisting of metal 1, metal 2, metal 3 and metal 4.
- each of the tilling structure patterns at different layers have the same shape and the same orientation.
- the invention is not limited thereto: tilling structure patterns at different layers can have the same shape but a different orientation, or they can even have a different shape, as long as the shape of the tilling structure patterns substantially inhibits the inducement of image currents in the tilling structures by a current in the inductive element 11. As can be seen in Fig.
- all elongate metal strips 12 of a tilling structure pattern 14 at one metal layer are electrically connected to each other by means of an interconnection strip 13. It is advantageous to provide the interconnection strip 13 substantially in the center of the tilling structure pattern 14 rather than at the extremities thereof, because if provided at the extremities the chances increase of creating a conductive path in which image currents can be generated. Furthermore, all tilling structure patterns 14 of different metal layers are electrically connected to each other by means of vias 21. In between every two metal layers, insulating layers are provided. It can be seen on Fig. 2 that the tilling structure patterns 14 do not cross a location above the substrate 20 where the inductive element 11 is provided.
- a ground shield 22 may be fabricated above or near an interface of the substrate 20, for example a semiconductor layer, e.g. a silicon substrate layer, with an insulating layer, e.g. a silicon oxide layer.
- the patterned ground shield 22 may be a grating composed of a collection of locally isolated conductive lines locally separated by slots and mutually grounded.
- each of the conductive lines in the ground shield grating is positioned orthogonal to the conductive line segments in the inductive element 11 above it. In that case, the patterned ground shield does not allow the flow of counter-currents or Eddy currents induced by changes in the magnetic flux by current flowing through the inductive element 11.
- ground shield 22 is processed in a lower layer, typically in suicided polysilicon or metal 1 ; in the example given above in Table 1 it is processed in suicided polysilicon.
- the shield lines go under the inductor path(s) and are responsible for a parasitic capacitor between the ground shield 22 and the inductive element 11 and thus for a decreased resonance frequency.
- the ground shield layer preferably is placed as far as possible from the inductor layer, in order to decrease the parasitic capacitance.
- the slots which separate adjacent conductive lines of the ground shield are preferably very narrow in comparison with the width of the conductive lines.
- the patterned ground shield still blocks the penetration of electric field lines of the inductive element to the substrate. Accordingly, the performance of the inductive element is not reduced by losses arising from penetration of the electric field into the substrate, and coupling through the substrate between the inductor and other nearby circuit elements is reduced.
- the thickness of the ground shield is significantly less than the skin depth at the frequency of interest in order to avoid attenuation of the magnetic field and reductions of the effective inductance of the inductive element.
- the tilling structure patterns 14 are located between the ground shield 22 and the inductive element 11.
- all or part of the tilling structure patterns 14 may be located above the inductive element 11, so that the inductive element 11 is located between the ground shield 22 and at least one of the tilling structure patterns 14.
- the tilling structure patterns 14 are all connected to a same DC potential. Hence, any capacitive effect between the different tilling structure pattern layers is avoided.
- the tilling structure patterns 14 are connected to the ground shield provided underneath the inductive element 11.
- the inductor parasitic capacitance is dominated by the capacitance between the inductive element 11 and the ground shield 22.
- the tilling structure pattern 14 allows to connect all metals within the inductor vicinity to the ground shield 22 without creating a conductive loop. Therefore, the tilling structure pattern avoids parasitic capacitance effects.
- Fig. 1 shows a top view of a single-loop inductive element 11 and a tilling structure pattern 14 according to the present invention.
- the distance DI between the inductive element 11 and the ground shield 22 should be optimized, i.e. should be as large as possible in order to avoid parasitic capacitance between the inductive element 11 and the ground shield 22.
- the distance D2 between the inductive element 11 and the tilling structure patterns 14 should also be optimized when taking into account as far as possible the minimum pattern density allowed by technology requirements.
- the tilling structure patterns 14 are placed as close as possible to the center of the inductive element 11, and thus as far away from the conductive lines of the inductive element 11 as allowed by the design rules (maximum metal to metal requirements).
- the shape of the tilling structure pattern 14 is finger-like or comb- like, i.e. the pattern comprises a plurality of substantially parallel lines 12 which are all connected to each other by means of a further line 13 which is substantially perpendicular to the plurality of parallel lines 12 and is laying in the same plane.
- any other shape of tilling structure pattern 14 which also prevents large induced currents to flow is also valid.
- FIG. 3 shows a radial pattern 30 for the tilling structure pattern. Due to the radial pattern, all conductive lines 31 forming the tilling structure pattern 30 are electrically connected substantially in the center point of the pattern.
- the inductive element 11 consists of a plurality of conductive line segments. It is an advantage of the radial pattern 30 combined with the octagonal shaped inductive element 11 of Fig. 3 that each elongate strip 31 of the radial pattern 30 is located locally perpendicular to the nearest conductive segment of the inductive element 11.
- the tilling structure 30 does not permit the flow of counter-currents induced by changes in the flux through the inductor. Therefore, the performance of the inductive element is not reduced by such induced counter-currents, as is the case with conventional dummy structures. It is not intended to limit the embodiment of the present invention relating to radial patterns 30 to a combination of the radial pattern 30 with an octagonal shaped inductive element 11 : the radial pattern 30 may be used with any suitable shape of inductive element 11, such as a substantially circular or spiral inductive element.. Fig.
- FIG. 4 illustrates a double loop rectangular conductive element 11, and a corresponding patterned tilling structure in the center area of the conductive element 11.
- the conductive lines 12 of the tilling structure pattern 40 are oriented roughly perpendicular to the conductive lines of the inductive element 11. Furthermore, the conductive lines 12 of the tilling structure pattern 40 are all electrically connected to each other. Although it is generally preferred to arrange the conductive lines in the patterned tilling structures so that they are oriented perpendicular to the conductive lines in the inductive element, good results can also be obtained with other patterns.
- the embodiment of Fig. 1, or the embodiment of Fig. 5 each show an example of a tilling structure pattern comprising parallel conductive lines.
- Patterns of this type are not optimal for spiral inductors since they contain conductive lines oriented parallel or substantially parallel to the conductive lines of the inductive element. Nevertheless, because these patterns still inhibit the flow of the image current, they are far superior to the separate dummy elements of the prior art. It is to be noted that these patterns can be very effective in conjunction with a meander inductor as illustrated in Fig. 6.
- a meander inductor as illustrated in Fig. 6.
- the tilling structures 70 consist of triangular shaped metal pieces 71. Those triangular shaped metal pieces 71 are all electrically connected together by means of an interconnection strip 72.
- the capacitance between the tip of a triangle and the inductive element is smaller, and that the amount of metal in a neighborhood of the inductive element where the magnetic field is higher (closer to the inductive element) is smaller.
- this triangular shape may be approximated by a stepwise triangular shape as in Fig. 8.
- the triangular parts of the tilling structure pattern can also be used in a radial pattern as illustrated in Fig. 9. It is an advantage of such triangular shaped or approximated triangular shaped tilling structure patterns that the capacitance between the tips of the triangles 71 or approximated triangles 81 and the inductive element 11 is reduced.
- a capacitor and an inductor are processed together in silicon to create a transformer of an LC tank.
- a capacitor may be processed, independent of the inductor or not, in the inductive element vicinity.
- the vicinity of the inductive element is mainly meant the area enclosed by the inductor loop, as well as the area around the loop, where the two regions, inside and outside the loop, are connected together by the grounded shield if there is one.
- the shape used for the tilling structure pattern layer(s) may be used to build a capacitive element in the vicinity of the inductive element.
- the shape of the tilling structure pattern layer(s) is as described above, which may comprise any pattern that substantially inhibits an inducement of an image current in the tilling structure pattern due to current flowing through the conductor of the inductive element.
- Fig. 10, Fig. 11, Fig. 12, Fig. 13 and Fig. 14 show embodiments of what a capacitive element processed in the inductor vicinity can look like according to the present invention.
- Fig. 10 illustrates a top view of a capacitive element 100 patterned into an inductive element 11.
- the capacitive element 100 comprises two capacitor terminals or capacitor plates 101, 102.
- One capacitor terminal or capacitor plate 101 may be formed by an tilling structure pattern layer as described above, e.g. a fingerlike or comb-like structure.
- the other capacitor terminal or capacitor plate 102 may be formed by another tilling structure pattern layer as described above, or by the ground shield.
- the second capacitor terminal or capacitor plate 102 has the same fingerlike or comb-like structure as the first capacitor terminal or capacitor plate 101, and is implemented above a (preferably patterned) ground shield 111.
- a vertical cross-section of the embodiment of Fig. 10 is represented in Fig. 11.
- the first capacitor terminal or capacitor plate 101 has the same shape as the second capacitor terminal or capacitor plate 102, and both capacitor terminals or capacitor plates 101, 102 are located right above each other.
- Fig. 12 and Fig. 13 illustrate, respectively in a top view and in a vertical cross- section, a second embodiment of a capacitive element according to the present invention. It shows an embodiment in which the two capacitor terminals or capacitor plates 121, 122 have substantially the same shape, but a different orientation. No ground shield is present in this embodiment.
- Fig. 14 shows a cross-section of a third embodiment of a capacitive element according to the present invention. The capacitor terminals do not form two separate capacitor plates. Instead, the capacitive element represented has two capacitor terminals each formed by a plurality of fingers of different layers of tilling structure patterns.
- All fingers which are represented as white squares in the vertical cross-section of Fig. 14 form a first capacitor terminal, and all fingers which are represented as hatched squares in Fig. 14 form the second capacitor terminal.
- the tilling structure metal patterns according to the present invention may thus be used to form at least one plate or terminal of a capacitive element, and pillar-like tilling structures as known from the prior art are not used in the neighborhood of the inductive element.
- the distance between the patterned capacitive element and the inductive element must be large enough to avoid a dominant fringe coupling between them, for example at least a factor 50 larger than the minimum metal width.
- the distance between the patterned capacitive element and the inductive element must be larger than the distance between the inductive element and its ground plane or ground shield (which is roughly 5 ⁇ m in present technologies) if present, for example the distance between the capacitive element and the inductive element may be twice the distance between the inductive element and its ground shield or more, i.e. for present technologies about 10 ⁇ m or more.
- the present invention is particularly interesting for inductive elements with a large radius, i.e. which have a radius which is large enough to place something in the center area of the inductive element.
- Such large inductors are the ones concerned by the pattern density requirements, as saving semiconductor area, e.g. silicon area, is a bigger issue when the inductor is large.
- the capacitor can be more easily designed within the inductor vicinity without modifying the parasitic capacitance of the inductor.
- the capacitor can be variable if processed as an active device, e.g. polysilicon on an active area, or as diodes in the inductor area.
- Table 2 and Table 3 hereinafter give examples of layers assigned to the different electrodes of the inductive element, capacitive element and shield here considered in a standard CMOS process. Tilling structures may be provided apart from capacitive elements.
- any suitable conductive material may be used, for example polysilicon, or metals such as e.g. copper, copper alloy or aluminum.
- the material for the insulating layers between the metal layers is most preferably silicon oxide, or a low-k dielectric material such as any of a number of different suitable low- k dielectric materials employed in interconnect technology, e.g. organic low-k materials such as e.g. benzocyclobutene (BCB), SILK, FLARE or inorganic dielectric low-k materials such as e.g. methyl silsesquioxane (MSQ), hydrogen silsesquioxand (HSQ), SiOF.
- organic low-k materials such as e.g. benzocyclobutene (BCB), SILK, FLARE or inorganic dielectric low-k materials such as e.g. methyl silsesquioxane (MSQ), hydrogen silsesquioxand (HSQ), SiOF.
- MSQ methyl silsesquioxane
- HSQ hydrogen silsesquioxand
- SiOF SiOF.
- the preferred thickness of the layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04744591A EP1652199A2 (en) | 2003-07-23 | 2004-07-15 | Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements |
JP2006520960A JP2006528837A (en) | 2003-07-23 | 2004-07-15 | Inductive and capacitive elements for semiconductor technology with minimum pattern density requirements |
CN200480021000.4A CN1826670B (en) | 2003-07-23 | 2004-07-15 | Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements |
US10/564,582 US8653926B2 (en) | 2003-07-23 | 2004-07-15 | Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03102261.9 | 2003-07-23 | ||
EP03102261 | 2003-07-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2005008695A2 true WO2005008695A2 (en) | 2005-01-27 |
WO2005008695A3 WO2005008695A3 (en) | 2005-05-12 |
Family
ID=34072677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2004/051234 WO2005008695A2 (en) | 2003-07-23 | 2004-07-15 | Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements |
Country Status (6)
Country | Link |
---|---|
US (1) | US8653926B2 (en) |
EP (1) | EP1652199A2 (en) |
JP (1) | JP2006528837A (en) |
CN (1) | CN1826670B (en) |
TW (1) | TW200519979A (en) |
WO (1) | WO2005008695A2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007273577A (en) * | 2006-03-30 | 2007-10-18 | Toshiba Corp | Semiconductor integrated circuit |
WO2019164598A1 (en) * | 2018-02-20 | 2019-08-29 | Qualcomm Incorporated | Folded metal-oxide-metal capacitor overlapped by on-chip inductor/transformer |
US10643985B2 (en) | 2017-12-15 | 2020-05-05 | Qualcomm Incorporated | Capacitor array overlapped by on-chip inductor/transformer |
EP4072017A1 (en) * | 2021-04-09 | 2022-10-12 | Marquardt GmbH | Sensor device for a motor vehicle |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7928539B2 (en) * | 2007-01-29 | 2011-04-19 | Renesas Electronics Corporation | Semiconductor device |
JP5180625B2 (en) * | 2007-03-12 | 2013-04-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
GB2464542A (en) * | 2008-10-21 | 2010-04-28 | Cambridge Silicon Radio Ltd | Interdigitised metal on metal capacitor |
CN102576605B (en) * | 2009-11-17 | 2016-01-20 | 马维尔国际贸易有限公司 | Ground shield capacitor |
KR101133397B1 (en) * | 2010-04-05 | 2012-04-09 | 삼성전기주식회사 | Planar transformer and manufacturing method thereof |
US8836078B2 (en) | 2011-08-18 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertically oriented inductor within interconnect structures and capacitor structure thereof |
US8675368B2 (en) | 2011-08-18 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertically oriented semiconductor device and shielding structure thereof |
US8791784B2 (en) | 2011-08-18 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertically oriented semiconductor device and shielding structure thereof |
US8809956B2 (en) * | 2011-10-13 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vertically oriented semiconductor device and shielding structure thereof |
CN102412230B (en) * | 2011-11-28 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | Inductance ground shielding structure for radio frequency process |
CN102738125B (en) * | 2012-06-29 | 2015-01-28 | 杭州电子科技大学 | New fractal PFS structure |
CN102738124B (en) * | 2012-06-29 | 2015-05-13 | 杭州电子科技大学 | Novel fractal pattern grounding shield structure |
CN102738127B (en) * | 2012-06-29 | 2015-05-20 | 杭州电子科技大学 | Novel fractal PGS (Program Generation System) structure |
US9214269B2 (en) * | 2012-12-10 | 2015-12-15 | Texas Instruments Incorporated | IC rectangular inductor with perpendicular center and side shield traces |
US9551758B2 (en) | 2012-12-27 | 2017-01-24 | Duracell U.S. Operations, Inc. | Remote sensing of remaining battery capacity using on-battery circuitry |
US9478850B2 (en) | 2013-05-23 | 2016-10-25 | Duracell U.S. Operations, Inc. | Omni-directional antenna for a cylindrical body |
CN104241242B (en) * | 2013-06-09 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Earth shield structure and semiconductor devices |
US9726763B2 (en) | 2013-06-21 | 2017-08-08 | Duracell U.S. Operations, Inc. | Systems and methods for remotely determining a battery characteristic |
CN104934408B (en) * | 2014-03-20 | 2017-11-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of inductor with metal charge structure |
US9646759B1 (en) * | 2014-04-11 | 2017-05-09 | Altera Corporation | LC tank circuitry with shielding structures |
US9882250B2 (en) | 2014-05-30 | 2018-01-30 | Duracell U.S. Operations, Inc. | Indicator circuit decoupled from a ground plane |
US10297875B2 (en) | 2015-09-01 | 2019-05-21 | Duracell U.S. Operations, Inc. | Battery including an on-cell indicator |
US10644697B2 (en) | 2016-02-11 | 2020-05-05 | Texas Instruments Incorporated | Material-discernment proximity sensor |
DE102016110425B4 (en) * | 2016-06-06 | 2023-07-20 | X-Fab Semiconductor Foundries Gmbh | SEMICONDUCTOR TRANSFORMER |
US11024891B2 (en) | 2016-11-01 | 2021-06-01 | Duracell U.S. Operations, Inc. | Reusable battery indicator with lock and key mechanism |
US10608293B2 (en) | 2016-11-01 | 2020-03-31 | Duracell U.S. Operations, Inc. | Dual sided reusable battery indicator |
US10818979B2 (en) | 2016-11-01 | 2020-10-27 | Duracell U.S. Operations, Inc. | Single sided reusable battery indicator |
US10151802B2 (en) | 2016-11-01 | 2018-12-11 | Duracell U.S. Operations, Inc. | Reusable battery indicator with electrical lock and key |
US10483634B2 (en) | 2016-11-01 | 2019-11-19 | Duracell U.S. Operations, Inc. | Positive battery terminal antenna ground plane |
US10790244B2 (en) | 2017-09-29 | 2020-09-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
US11004589B2 (en) * | 2018-04-27 | 2021-05-11 | Realtek Semiconductor Corp. | High-Q integrated inductor and method thereof |
US10658973B2 (en) * | 2018-04-30 | 2020-05-19 | International Business Machines Corporation | Reconfigurable allocation of VNCAP inter-layer vias for co-tuning of L and C in LC tank |
US12087808B2 (en) * | 2020-07-29 | 2024-09-10 | Silicon Laboratories Inc. | Ensuring minimum density compliance in integrated circuit inductors |
US11837754B2 (en) | 2020-12-30 | 2023-12-05 | Duracell U.S. Operations, Inc. | Magnetic battery cell connection mechanism |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998050956A1 (en) | 1997-05-02 | 1998-11-12 | The Board Of Trustees Of The Leland Stanford Junior University | Patterned ground shields for integrated circuit inductors |
DE10012118A1 (en) | 1999-03-12 | 2000-11-09 | Nec Corp | High frequency circuit apparatus e.g. for filter, has slits in electrodes opposing capacitance element for reducing eddy current loss |
US20020074620A1 (en) | 2000-12-19 | 2002-06-20 | Yue Chik Patrik | Planar inductor with segmented conductive plane |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06326106A (en) | 1993-03-18 | 1994-11-25 | Sony Corp | Method of forming dummy pattern |
US6310378B1 (en) | 1997-12-24 | 2001-10-30 | Philips Electronics North American Corporation | High voltage thin film transistor with improved on-state characteristics and method for making same |
US6310387B1 (en) | 1999-05-03 | 2001-10-30 | Silicon Wave, Inc. | Integrated circuit inductor with high self-resonance frequency |
KR100326202B1 (en) * | 1999-08-19 | 2002-02-27 | 구본준, 론 위라하디락사 | Liquid Crystal Display Device and Method of Detecting Etching Point Thereof |
JP3488164B2 (en) * | 2000-02-14 | 2004-01-19 | Necエレクトロニクス株式会社 | Semiconductor device |
JP2002110908A (en) * | 2000-09-28 | 2002-04-12 | Toshiba Corp | Spiral inductor and method for manufacturing semiconductor integrated circuit device having the same |
JP2002158278A (en) * | 2000-11-20 | 2002-05-31 | Hitachi Ltd | Semiconductor device and manufacturing method and design method thereof |
US6489663B2 (en) * | 2001-01-02 | 2002-12-03 | International Business Machines Corporation | Spiral inductor semiconducting device with grounding strips and conducting vias |
US6362012B1 (en) | 2001-03-05 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications |
JP2002373896A (en) * | 2001-06-15 | 2002-12-26 | Mitsubishi Electric Corp | Semiconductor device |
-
2004
- 2004-07-15 US US10/564,582 patent/US8653926B2/en active Active
- 2004-07-15 CN CN200480021000.4A patent/CN1826670B/en not_active Expired - Fee Related
- 2004-07-15 WO PCT/IB2004/051234 patent/WO2005008695A2/en active Application Filing
- 2004-07-15 JP JP2006520960A patent/JP2006528837A/en not_active Withdrawn
- 2004-07-15 EP EP04744591A patent/EP1652199A2/en not_active Withdrawn
- 2004-07-20 TW TW093121660A patent/TW200519979A/en unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998050956A1 (en) | 1997-05-02 | 1998-11-12 | The Board Of Trustees Of The Leland Stanford Junior University | Patterned ground shields for integrated circuit inductors |
DE10012118A1 (en) | 1999-03-12 | 2000-11-09 | Nec Corp | High frequency circuit apparatus e.g. for filter, has slits in electrodes opposing capacitance element for reducing eddy current loss |
US20020074620A1 (en) | 2000-12-19 | 2002-06-20 | Yue Chik Patrik | Planar inductor with segmented conductive plane |
Non-Patent Citations (1)
Title |
---|
WOUTER DE COCK; MICHIEL STEYAERT, CONFERENCE ESSCIRC, 2001, pages 496 - 499 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007273577A (en) * | 2006-03-30 | 2007-10-18 | Toshiba Corp | Semiconductor integrated circuit |
US10643985B2 (en) | 2017-12-15 | 2020-05-05 | Qualcomm Incorporated | Capacitor array overlapped by on-chip inductor/transformer |
WO2019164598A1 (en) * | 2018-02-20 | 2019-08-29 | Qualcomm Incorporated | Folded metal-oxide-metal capacitor overlapped by on-chip inductor/transformer |
US10600731B2 (en) | 2018-02-20 | 2020-03-24 | Qualcomm Incorporated | Folded metal-oxide-metal capacitor overlapped by on-chip inductor/transformer |
EP4072017A1 (en) * | 2021-04-09 | 2022-10-12 | Marquardt GmbH | Sensor device for a motor vehicle |
Also Published As
Publication number | Publication date |
---|---|
EP1652199A2 (en) | 2006-05-03 |
CN1826670A (en) | 2006-08-30 |
US20060163692A1 (en) | 2006-07-27 |
WO2005008695A3 (en) | 2005-05-12 |
CN1826670B (en) | 2012-12-05 |
JP2006528837A (en) | 2006-12-21 |
TW200519979A (en) | 2005-06-16 |
US8653926B2 (en) | 2014-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8653926B2 (en) | Inductive and capacitive elements for semiconductor technologies with minimum pattern density requirements | |
CN103247596B (en) | on-chip ferrite bead inductor | |
KR101084959B1 (en) | A spiral inductor formed in a semiconductor substrate and a method for forming the inductor | |
US6492708B2 (en) | Integrated coil inductors for IC devices | |
US5936298A (en) | Method for realizing magnetic circuits in an integrated circuit | |
US6489663B2 (en) | Spiral inductor semiconducting device with grounding strips and conducting vias | |
WO1998050956A1 (en) | Patterned ground shields for integrated circuit inductors | |
EP1267391B1 (en) | A method to fabricate RF inductors with minimum area | |
JP2005175434A (en) | Inductor formed within integrated circuit | |
WO1997045873A1 (en) | Conductors for integrated circuits | |
US11011303B2 (en) | Dummy fill with eddy current self-canceling element for inductor component | |
JP4584533B2 (en) | Thin film multilayer high Q transformer formed in a semiconductor substrate | |
US8004061B1 (en) | Conductive trace with reduced RF impedance resulting from the skin effect | |
US6864581B1 (en) | Etched metal trace with reduced RF impendance resulting from the skin effect | |
US7223680B1 (en) | Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect | |
WO2002049110A1 (en) | Shielded inductor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200480021000.4 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2004744591 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 2006163692 Country of ref document: US Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10564582 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2006520960 Country of ref document: JP |
|
WWP | Wipo information: published in national office |
Ref document number: 2004744591 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 10564582 Country of ref document: US |