WO2005004032A1 - Dispositif a fonction - Google Patents

Dispositif a fonction Download PDF

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Publication number
WO2005004032A1
WO2005004032A1 PCT/JP2004/009442 JP2004009442W WO2005004032A1 WO 2005004032 A1 WO2005004032 A1 WO 2005004032A1 JP 2004009442 W JP2004009442 W JP 2004009442W WO 2005004032 A1 WO2005004032 A1 WO 2005004032A1
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Prior art keywords
function
output
voltage
input
circuit
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PCT/JP2004/009442
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English (en)
Japanese (ja)
Inventor
Viktor Varshavsky
Vjacheslav Marakhovsky
Ilja Levin
Natali Kravchenko
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Advanced Logic Projects Inc.
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Priority to JP2005511364A priority Critical patent/JPWO2005004032A1/ja
Publication of WO2005004032A1 publication Critical patent/WO2005004032A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N7/00—Computing arrangements based on specific mathematical models
    • G06N7/02—Computing arrangements based on specific mathematical models using fuzzy logic
    • G06N7/04—Physical realisation
    • G06N7/043—Analogue or partially analogue implementation

Definitions

  • the present invention relates to a function device that executes a function.
  • a fuzzy device (a controller or device having a fuzzy control function), which is one of the function devices, includes a fuzzifier, a fuzzy inference block (processing block), and a defuzzifier.
  • the fuzzy generator and the deferred dagger are usually implemented in hardware, and the fuzzy inference block is usually implemented as software of a microprocessor.
  • Patent Document 1 JP-A-7-334369
  • the processing block becomes a load on the microprocessor.
  • An AD converter and a DA converter are required on the input and output sides of the processing block, respectively.
  • the processing speed is limited by the time interval for detecting input variables to the processing block by the microprocessor.
  • the present invention has been made in view of such a point, and an object of the present invention is to solve one or more of the above problems.
  • the function device of the present invention includes an operational amplifier that acts as an analog threshold value element on an input voltage and generates a result of a weighting operation on the input voltage as an output voltage, and the operational amplifier includes: The output voltage behaves linearly with respect to the input voltage In addition, a desired function is realized by controlling so as to be limited by a predetermined power supply voltage.
  • the "operational amplifier” may be a summing amplifier! /, Or may be another type such as a differential amplifier.
  • An example of the “predetermined power supply voltage” is the voltage of the operation power supply of the operational amplifier.
  • the function may be expressed using a lookup table or the like, instead of being expressed using a mathematical expression. Note that the look-up table is not limited to one or two dimensions (that is, the number of input variables is one or two), but may be three or more dimensions (that is, three or more input variables). .
  • the upper and lower limits of the output voltage may determine the saturation characteristics of the operational amplifier, and the operating point of the operational amplifier may be 1Z2 of the power supply voltage.
  • Another embodiment of the present invention is also a function device, and is configured by a plurality of operational amplifiers, and the multi-valued voltage signal of the input and the output of the operational amplifier is a combination of a plurality of analog threshold functions. Corresponds to a predetermined function.
  • the output voltage of the operational amplifier becomes a saturation level.
  • the look-up table include a truth table in multi-valued logic and a fuzzy rule table in fuzzy logic.
  • an approximation based on a linear output may be made between discrete points (elements in the table) constituting a lookup table expressing the function.
  • discrete points elements in the table
  • a certain variable is a discrete expression such as “large”, “medium”, “small”, or the like. Therefore, when they are numerically drawn, they naturally become discrete, and when the fuzzy rule is expressed as a matrix, for example, it is represented by 3 ⁇ 3 discrete nine points. Therefore, the point between such discrete points may be approximated by, for example, linearly interpolating between the output voltages determined for the discrete points.
  • the function device may be configured as an analog circuit that eliminates software processing. In this case, it is possible to increase the processing speed and reduce the circuit scale.
  • the function device includes an input terminal for inputting an input voltage; A processing circuit unit that processes the input voltage input from the slave and generates an output voltage to be output with respect to the input voltage; and an output terminal that outputs the output voltage generated by the processing circuit unit.
  • the processing circuit section includes a plurality of threshold element circuits for outputting a linear sum of the input voltages, and the output of the threshold element circuits is superimposed on the output voltages.
  • Each of the threshold element circuits may be configured such that the input voltage and z or a voltage output from the other threshold element circuit are input to each of the threshold element circuits so as to be a voltage.
  • the threshold value element circuit for example, an operational amplifier can be used.
  • the threshold value element circuit outputs the linear sum when the linear sum is within a predetermined range, and outputs the upper limit when the linear sum is equal to or more than the upper limit of the predetermined range. Then, when the linear sum is equal to or smaller than the lower limit of the predetermined range, the lower limit may be output.
  • the “predetermined range” is, for example, a range within a saturation level of the threshold element circuit (a range from a lower limit voltage to an upper limit voltage of the saturation level).
  • the threshold element circuit includes a PMOS transistor having a source connected to a first power terminal, and a source connected to a second power terminal to which a voltage lower than that of the first power terminal is applied.
  • p (p: odd) CMOS transistors each comprising a NMOS transistor having a drain connected to the drain of the PMOS transistor, and the PMOS transistor constituting the CMOS transistor of each stage.
  • each drain of the NMOS transistor is connected to the gate of the PMOS transistor and the gate of the NMOS transistor forming the CMOS transistor of the next stage, and the PMOS transistor forming the CMOS transistor of the first stage.
  • a voltage to be input to the threshold element circuit is input to each of the gates of the first stage through an input resistor. Output said threshold element circuit power from each said drain of the stage. It may be configured to output a power voltage.
  • the above-described threshold element circuit can be realized with a simple configuration.
  • CMOS transistor l
  • the one CMOS transistor is both the first-stage CMOS transistor and the P-th (last) CMOS transistor.
  • the number of CMOS transistors provided in each of the plurality of threshold and value element circuits included in the processing circuit unit may be different if not necessary.
  • the voltage applied to the first power supply terminal may determine an upper limit of the predetermined range, and the voltage applied to the second power supply terminal may determine a lower limit of the predetermined range.
  • the second power terminal may be grounded. At this time, the voltage applied to the second power supply terminal is 0.
  • the input voltage and the output voltage may both be analog signals, and the processing circuit may process the input voltage as an analog signal.
  • the function device may execute fuzzy control (fuzzy device).
  • the device may be configured as an AZD translator, a DAZA translator, and an analog circuit that eliminates software processing by a microprocessor.
  • the function device includes a first circuit that realizes a first output section in which an output of the device is on a first straight line, and a first circuit in which the output is on a second straight line. And a second circuit that implements a two-output section.
  • the desired function is implemented by combining a plurality of circuits having linear output characteristics with respect to the input.
  • the first and second circuits are configured to include, for example, one or more threshold element circuits.
  • the output of the first circuit takes a constant value in a section other than the first output section
  • the output of the second circuit takes a constant value in a section other than the second output section.
  • the first circuit does not affect the slope of the straight line on which the output of the device is mounted in a section other than the first output section.
  • the fuzzy device of the present invention includes an operational amplifier that operates as an analog threshold value element for an input voltage and generates an inversion of a result of a weighting operation on the input voltage as an output voltage.
  • the amplifier realizes a desired fuzzy function by controlling the output voltage to behave linearly with respect to the input voltage and to be limited by a predetermined power supply voltage.
  • Another embodiment of the present invention is also a fuzzy device, and is constituted by a plurality of operational amplifiers, and a multi-valued voltage signal of an input and an output of the operational amplifier is a predetermined value as a superposition of a plurality of analog threshold functions. It corresponds to the fuzzy function.
  • the operational amplifier controls the output voltage to the saturation level. You can.
  • an approximation by a linear output may be made between discrete points constituting the specification of the fuzzy rule.
  • This device is composed of a fuzzy ladder that is an AZD variable, a defuzzy ridge that is a DZA variable, and a microprocessor. It may be configured as an analog circuit that eliminates software processing. In this case, it is possible to increase the processing speed and reduce the circuit scale.
  • the multi-valued logic device of the present invention includes an operational amplifier that operates as an analog threshold value element for an input voltage and generates a result of a weighting operation on the input voltage as an output voltage. Realizes a desired multi-valued logic function by controlling the output voltage to behave linearly with respect to the input voltage and to be limited by a predetermined power supply voltage.
  • Another embodiment of the present invention is also a multi-valued logic device, which is constituted by a plurality of operational amplifiers, and the multi-valued voltage signal of the input and output of the operational amplifiers is obtained by superimposing a plurality of analog threshold functions.
  • the combination corresponds to a predetermined multi-valued logic function.
  • the output voltage of the operational amplifier becomes the saturation level.
  • matrix expressing multi-valued logic rule One example is a truth table in multi-valued logic.
  • an approximation by a linear output may be made between discrete points constituting the specification of the multi-valued logic rule.
  • the multi-valued logic device may be configured as an analog circuit that eliminates software processing. In this case, it is possible to increase the processing speed and reduce the circuit scale.
  • a multi-valued logic device processes an input terminal for inputting an input voltage associated with an input logical value, processes the input voltage input from the input terminal, and converts the input logical value to the input logical value.
  • a processing circuit unit that generates an output voltage associated with an output logic value to be output to the processing circuit unit; and an output terminal that outputs the output voltage generated by the processing circuit unit.
  • a plurality of operational amplifiers that output a linear sum of the input voltages, and each of the operational amplifiers is configured such that a voltage output from the operational amplifier at the last stage in the processing circuit unit becomes the output voltage.
  • the input voltage and the voltage output from Z or another output from the operational amplifier may be configured to be input.
  • the “final stage operational amplifier” is an operational amplifier whose output is the output voltage, and a plurality of operational amplifiers corresponding to the operational amplifier may be provided in the processing circuit unit. That is, if there are a plurality of output variables in the multi-valued logic, a plurality of final stage operational amplifiers may be provided.
  • FIG. 1 (a) is a diagram showing a general structure of a summing amplifier
  • FIG. 1 (b) is a diagram showing an example of a CMOS implementation thereof.
  • FIG. 2 (a) shows the behavior of the summing amplifier in a voltage coordinate system
  • FIG. 2 (b) also shows the behavior in a multi-valued variable coordinate system.
  • FIG. 3 ( a ; H ⁇ fa (x), and FIG. 3 (b) is a diagram showing maj (x, —a, —k), respectively.
  • FIG. 4 is a diagram showing an implementation of a function (x + 1).
  • FIG. 5 is a view showing the structure of a conventional fuzzy device.
  • FIG. 6 is a diagram schematically showing a function specified by Table 1.
  • FIG. 8 is a diagram showing a CMOS implementation of a fuzzy controller specified by a wash_time matrix.
  • FIG. 9 is a diagram showing a SPICE simulation result of the operation of the fuzzy controller in FIG. 8
  • FIG. 10 (a) is a diagram showing an example of a seven-valued function in fragment constant, and (b) is a diagram showing fragment linear.
  • ⁇ 12] is a diagram showing a circuit in which the expression (22) is mounted.
  • FIG. 13 (a)-(c) is a diagram showing an example of the behavior of the circuit in FIG.
  • FIG. 15 is a diagram showing a membership function of an input variable.
  • FIG. 16 (a) shows F (y) in Table 8
  • FIG. 16 (b) shows F (y).
  • FIG. 17 is a diagram showing a procedure for constructing F (y).
  • FIG. 18 is a diagram illustrating a configuration of a circuit implemented according to Expression (37).
  • FIG. 19 (a) and (b) are diagrams showing an example of a summing amplifier configured using a three-stage and five-stage push-pull CMOS operational amplifier, respectively.
  • FIG. 20 is a diagram showing a controller circuit used for SPICE simulation.
  • FIG. 21 is a diagram showing a simulation result when a controller is configured using a three-stage amplifier.
  • FIG. 22 is a diagram showing a simulation result when a controller is configured using a 5-stage amplifier.
  • FIG. 23 is a graph showing a function f (z).
  • FIG. 24 is a graph showing five components of a function f (z).
  • FIG. 25 is a graph for explaining how to obtain a function a (z).
  • FIG. 26 is a graph for explaining how to obtain a function a (z).
  • FIG. 27 is a diagram for explaining how to implement the matrix M.
  • FIG. 28 (a) is a graph showing a function ⁇ ( ⁇ ).
  • (b) is a graph showing the function ⁇ (w).
  • FIG. 29 (a) is a graph showing a function ⁇ (y).
  • (b) is a graph showing the function ⁇ ( ⁇ )
  • FIG. 30 is a graph showing a function f.
  • FIG. 31 is a graph showing a function ⁇ (X).
  • FIG. 32 is a graph showing a function f.
  • FIG. 33 is a graph showing a function ⁇ (X).
  • FIG. 35 is a diagram for explaining how to implement the pyramid function shown in FIG.
  • FIG. 36 is a graph showing a function ⁇ (X).
  • FIG. 38 (a) is a graph showing a cross section perpendicular to the y-axis of the pyramid function of FIG. (B) is a graph showing a cross section of the pyramid function of FIG. 34 perpendicular to the X axis.
  • FIG. 39 (a)-(c) are diagrams for explaining a cross-sectional shape of a pyramid function.
  • FIG. 42 (a) is a diagram showing a configuration example of HS3-HS33 in FIG. 43.
  • (B) shows P in Fig. 43.
  • FIG. 3 is a diagram showing a configuration example of HS1 and PHS2.
  • FIG. 43 is a diagram showing a controller circuit in which the functions shown in Table 9 are implemented.
  • FIG. 44 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 43.
  • FIG. 45 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 43.
  • FIG. 46 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 43.
  • FIG. 47 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 43.
  • FIG. 48 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 43.
  • FIG. 49 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 43.
  • FIG. 50 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 43.
  • FIG. 51 is a diagram showing a function F (X, V).
  • FIG. 52 is a diagram showing a function F (X, V).
  • FIG. 53 is a graph showing a function F (X, V).
  • FIG. 54 is a diagram showing a fuzzy controller circuit implementing the functions shown in Table 10.
  • FIG. 55 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 54.
  • FIG. 56 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 54.
  • FIG. 57 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 54.
  • FIG. 58 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 54.
  • FIG. 59 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 54.
  • FIG. 60 is a graph showing the results of SPICE simulation on the circuit shown in FIG. 54.
  • FIG. 63 A graph showing subfunction 7? (P).
  • FIG. 64 (a) is a graph showing sub-functions corresponding to each sampling point.
  • (B) is a graph obtained by superimposing all subfunctions.
  • FIG. 65 is a diagram for explaining a case where the implemented function is a straight line.
  • FIG. 68 is a diagram showing a circuit in which subfunction 7? (P) in FIG. 67 is mounted.
  • Ml 24 ⁇ Transistor, R1–93 ⁇ Resistance, S—S, HS1—33, PHS1, 2, 7
  • Width (threshold element circuit).
  • Fig. 1 (a) The behavior of the summing amplifier is accurately determined in the unconnected state as shown in Fig. 1 (a), and is described as follows.
  • the infinitesimal order of the members included in this circuit is determined by the amplification factor.
  • V is the power supply voltage
  • V is the j-th input voltage
  • R is the value of the j-th resistor
  • R is the feedback resistance value of dd jj
  • V Z2 is the operation midpoint of the amplifier.
  • Figure 1 (b) shows an implementation example using the OS.
  • the lower limit is output.
  • equation (1) can be expressed as follows.
  • FIG. 2 (b) schematically shows equation (3).
  • the Webb function can be expressed by a threshold or a multi-decision function.
  • FIG. 3 (a) The function maj (x, —a, —k) is shown in Fig. 3 (b).
  • maj (x, —a, —k) — k because X a—k ⁇ k.
  • f (X) + maj (x, -a, k) a + k holds (a
  • a fuzzy device as a multilevel analog circuit
  • a conventional fuzzy device or fuzzy controller that is, a circuit having a fuzzy control function usually has a configuration shown in FIG.
  • the fuzzy inference block states that "if a has an average positive value and a has a small negative value j
  • the Defozzificator is a digital variable B represented by a weighted linguistic expression.
  • the fuzzifier and defuzzifier are implemented in hardware by an ADA, ie, an analog-to-digital-to-analog converter, and the fuzzy inference is usually implemented in microprocessor software.
  • a fuzzy device can be thought of as an analog signal converter that performs the following functions:
  • the fuzzifier supports variables with seven levels of linguistic expression. Each level is NB-negative large (-3); NM-negative medium (-2); NS-negative small (-1); ZO-zero (0); PS-positive small (1); PM-Positive Medium (2); PB-Positive Large (3).
  • the output has a uniform slope.
  • PB NB NB NB NB NM NS ZO Table 2 is a look-up table (LUT) showing Table 1 as a seven-valued logic function.
  • FIG. 7 shows a CMOS circuit (function device) corresponding to a desired function, which has 16 transistors and 5 resistors.
  • ⁇ 0.4 and “0.6” indicate the semiconductor process, that is, the size of the transistor.
  • the six transistors Ml 1-16 on the left correspond to the main body of the summing amplifier used as an inverter.
  • the right-hand ten transistors Ml-10 correspond to the body of the summing amplifier.
  • this functional device is an arithmetic operation configured by appropriately connecting the transistor Ml-10 and the resistors R1,2,5.
  • a processing circuit section including two operational amplifiers (a threshold element circuit and an operational amplifier) constituted by an amplifier and a transistor Ml 1-16 and a resistor R3-4 appropriately connected is provided. Of the amplifiers, the right side in the figure corresponds to the final stage operational amplifier.
  • the part described as ce is the input terminal of the function device, the part described as V is the output terminal, R1 output
  • the terminal connected to the source of Ml 1-13 is the second power supply terminal (grounded! /,).
  • the manipulator conceived experimentally has two force Z torque sensors.
  • One of the sensors is a calculation force sensor F, and the other is an “environmental force sensor” ⁇ .
  • the value has three linguistic variables-S (small), M (medium) and B (large), and has the following five fuzzy rules:
  • the output is a ternary logic function as shown in Table 3.
  • R 0.5 ⁇ ohm.
  • VL Very long (VL), long (L), medium (M), short (S), very short (VS);
  • dirtness— of— clothes power S is large, type— of— dirt force S is medium, wash— time is long. If dirtness— of— clothes power S is medium, type—of— Medium;
  • wash—time is 3 ⁇ 4i
  • wash_time is very short
  • Table 4 shows the above as a matrix of variables in linguistic expressions.
  • Table 5 shows the matrix of multivalued variables.
  • wash time ⁇ (- ⁇ ⁇ , - ⁇ 2 ) ⁇ (10a)
  • X corresponds to type_of_dirt, and can take up to ⁇ 2 to +2 as follows.
  • the wash_time can be expressed as follows.
  • wash tim e ⁇ ( ⁇ 3 (7),-0.DX, -2, -3 ⁇ 43 ⁇ 4) (13)
  • wash_time is formulated as follows.
  • FIG. 8 shows a CMOS circuit obtained in this manner, based on the equations (16), (11) and (14). This circuit is implemented by superimposing four multi-valued threshold element circuits.
  • This function device consists of an operational amplifier (upper left part in the figure) composed of transistors Ml-6 and resistors R1-3 connected appropriately, and a transistor M7-12 and resistors R4-6 and R10 connected appropriately.
  • Operational amplifier (lower left part in the figure), an operational amplifier (lower right part in the figure) composed of transistors M13-18 and resistor R7-8 connected appropriately, transistor Ml9-24 and resistor
  • a processing circuit unit including four operational amplifiers is provided with an operational amplifier (upper right part in the figure) configured by appropriately connecting R11-15.
  • the one in the upper right in the figure corresponds to the final operational amplifier.
  • X and Y are the input terminals of the function device, and the washjime is the output terminal.
  • Resistor R3 is ideally a force of 10000k ohms. Actually, it is 9300k ohms and adjusted according to the amplification gain of this circuit. R3 is the lower limit of the saturation value,
  • Resistors R5 and R10 are 9500k ohms, ideally 10,000k ohms.
  • the resistance R6 is 5000k ohms, half of R4. This gives twice the upper limit of the saturation value,
  • Resistor R15 connects the lower left and upper right circuits and is 18000k ohms. Its ideal value is 20000k ohms. R15 is about twice that of R11,
  • the upper right circuit corresponds to the summation amplifier main body, and has the function of (1) in Equation (16).
  • Resistor R13 is 20000k ohms, twice that of R11.
  • the lower limit of the saturation value —2 is multiplied by 1Z2, which is Rl 1 / R13, and 1 is realized.
  • the circuit at the lower right corresponds to 0.5X in equation (16).
  • 0.5 is achieved by making the resistor R12 twice as large as R11 at 20000k ohms.
  • FIG. 9 shows the result of SPICE simulation of the operation of the circuit of FIG.
  • the horizontal and vertical axes indicate the variable Y and the output voltage, respectively.
  • the output value when the output value is "1", the output voltage becomes OV.
  • An example is at the point (OV, OV) in the figure.
  • the output value when the output value is "1”, the output voltage becomes 0.9V. This can be seen at (1.75V, 0.9V).
  • the output value is "0”, “1” or “2”
  • the output voltage becomes 1.8V, 2.5V or 3.2V, respectively.
  • a summing amplifier is a threshold element circuit that has function completeness in any multi-valued logic (of any value), and can be the basis for implementing analog fuzzy devices. it can.
  • the function describing the behavior of the fuzzy controller can be appropriately represented by the following first or second method.
  • the first method is a method of expressing it by a fuzzy rule of the type "if A, then B."
  • a and B are variables represented by linguistic expressions (language variables).
  • a set of linguistic variables is represented as a table corresponding to one output.
  • Equation (17) can be further extended, and thus shows that a fuzzy circuit can be constructed by a method of exclusion of variables. For that purpose, a sub-circuit corresponding to the following equation (18) is required.
  • FIGS. 10A and 10B show an example of a seven-valued function.
  • the function in Figure 10 (a) which is a fragment constant, fully corresponds to the table representing the fuzzy rules (fuzzy rule table), but does not take into account the process of fuzzification and defuzzification. If these processes are considered, the above function should be fragment-linear as shown in Fig. 10 (b). According to such a fragment linear function, input variables and output variables are appropriately distributed for fuzzification and defuzzification, respectively.
  • ⁇ ⁇ , ⁇ , ⁇ ⁇ ⁇ , ⁇ Is an analog variable or a multi-valued variable
  • j8 is a constant that symbolizes the threshold
  • the power supply voltage V corresponds to the logical value a
  • the ground potential V corresponds to the logical value a.
  • the masking function can be implemented as follows using a summing amplifier.
  • I a I means the absolute value of a.
  • FIG. 12 shows a circuit corresponding to this equation. In the figure, four summing amplifiers are provided. Further, the circuit in the figure is represented by the following equation.
  • FIGS. 13 (a) to 13 (c) the behavior of the circuit in FIG. 12 is as shown in FIGS. 13 (a) to 13 (c).
  • Fig. 13 (a) Indicates M (x) and M (x)
  • FIG. 13 (b) shows the relationship between S (—M (x); 2) and S (M (x); 2).
  • FIG. 13C shows the final output of the circuit of FIG. 12 (ie, y in equation (23)).
  • FIG. 14 (a) shows M (x) and M (x)
  • FIG. 14 (b) shows M (X)
  • FIG. 14 (c) shows S (—M (X); 2) and S ( M
  • This fuzzy controller implements a function having two language variables, "position error” and "force error”.
  • these variables are represented as X and y, respectively.
  • the variables X and y have seven values, NL, NM, NS, ZE, PS, PM, and PL, respectively.
  • their membership functions are as shown in FIG.
  • Table 7 shows Table 6 with the values of the corresponding multi-valued logic functions.
  • Table 7 is composed of the two types of columns shown in Table 8.
  • Figs. 16 (a) and 16 (b) depict the two types of columns shown in Table 8 as functions of the force error y.
  • F (y) can be constructed. Therefore, F (y) and F (y) can be implemented as in the following equation.
  • the rule of Expression (28) can be implemented as follows according to Expressions (25), (26), and (23).
  • Figure 18 shows the configuration of the circuit implemented according to equation (37).
  • coefficients representing the input weight of each addition amplifier are described. For example, looking at the summing amplifier represented by S, it shows that each of the two inputs (V and y) is multiplied by 3Z2 dd
  • This function device has 13 operational amplifiers of S—S and M (X) and M (X)
  • the portions described as X and y are input terminals of the function device, and the portions described as V are output terminals.
  • FIGS. 19 (a) and 19 (b) show a 3-stage and 5-stage push-pull CMOS operational amplifier.
  • FIGS. 19 (a) and 19 (b) show a summing amplifier configured using a three-stage push-pull CMOS operational amplifier.
  • FIG. 19 (b) shows a summing amplifier configured using a five-stage push-pull CMOS operational amplifier.
  • FIG. 20 shows a controller circuit used for the simulation. SPICE simulation ( The behavior of the controller in Fig. 20 was checked using MSIM 8). As a transistor,
  • the power supply voltage was set to 3.5V.
  • the input X was varied linearly up to 3.5V from the OV force, and the input y was varied discretely according to its logical value.
  • the value of y was kept constant while changing X one cycle from OV to 3.5V.
  • FIG. 21 shows a simulation result when a controller is configured using a three-stage amplifier. It can be seen that the behavior of the controller is correct (the logical value of the output variable depends on the logical value of the input variable according to Table 7).
  • the matrix M shown in Table 9 is divided into two matrices M and M.
  • M is the symmetric component extracted from the M force, and M is the residual component
  • M for example, “ ⁇ 0” is any value as long as it is 0 or less
  • ⁇ 2 means that any value of 2 or more may be used. This is due to the saturation characteristics of the operational amplifier.
  • equation (51) can be operated with one summing amplifier. From the above, the following equation is obtained.
  • the matrix Mi representing the function ⁇ ( ⁇ ) is represented by a controller circuit shown in FIG.
  • the matrix M is decomposed into two matrices M 1 and M 2.
  • f (X, y) is realized by two summing amplifiers HS8 and HS9.
  • the matrix M is decomposed into two matrices M 1 and M 2.
  • the sum of these two matrices contains the desired element ("3") at the intersection of the two straight lines.
  • the matrices M and ⁇ are expressed as one-variable functions ⁇ ( ⁇ ) and ⁇ (w), respectively.
  • ⁇ (X, y) can be implemented as in the following equation.
  • ⁇ (X, y) can also be implemented with three summing amplifiers. One of them outputs ⁇ (x, y)
  • the amplifiers HS21 to HS24 correspond to the equation (64).
  • the function: ⁇ (x.v) S (S ( ⁇ (y) — ⁇ ( ⁇ ) +3) - ⁇ ( ⁇ ) +3) is a function of the two amplifiers HS25 and
  • the amplifier HS20 is also used in the implementation of the function ⁇ (x, y) shown in equation (61). Also, the constant “1 3” in the equation (61) and the constant “3” in the equation (63) cancel each other out when these two functions are added.
  • This amplifier H S20 implements a function S ( ⁇ ( ⁇ , y) + ⁇ (x, y)) representing a matrix M.
  • the function f is implemented in amplifiers HS26—HS28 and HS17.
  • the pyramid function is 70) is a function of the element block that implements the type of condition shown in equation.
  • Figure 34 shows an example of this function.
  • the pyramid function takes a certain value c at the point (a, b) and takes a value 0 at an adjacent point. c
  • the change up to zero force is linear.
  • construct a pyramid function In the figure, two functions j8 (X) and j8 (X) are shown. These are implemented in (2k + l) -valued logic (one k ⁇ x ⁇ k) as follows:
  • a pyramid of any height can be obtained.
  • a pyramid with a height of kZ2 can be realized by setting the input resistance to twice the feedback resistance.
  • ⁇ ( ⁇ ), ⁇ by setting code appropriately at the stage of constructing the (y), X y Vila shown in FIG. 34 with respect to the plane Density symmetrical pyramids (i.e. three-dimensional coordinates of the vertices (X, y , k) can be easily obtained.
  • the pyramid function is not limited to the one shown in Fig. 34, and various functions can be considered.
  • a pyramid shown in FIG. 37 can be obtained.
  • Which pyramid function to use may be determined while confirming by SPICE simulation or the like so that good interpolation between adjacent grid points is realized.
  • the present invention is not limited to the quadrangular pyramid shape as shown in FIGS. That is, by appropriately changing the constants in the eight functions (see equations (71) and (72)), it is possible to implement the condition of the type represented by the following equation
  • FIGS. 38 (a)-Fig. 39 (c) are called “center trapezoid", “right trapezoid” and “left trapezoid”, respectively.
  • the cross sections shown in FIGS. 38 (a) and 38 (b) are called “triangular type”.
  • the pyramid function f is represented by y in FIG.
  • Such a function f may be implemented as in the following equation.
  • ⁇ 8 ( ⁇ ) S (3x + 6) + 3.
  • Figure 40 (a) Figure 40 (d) shows ⁇ (y), ( ⁇ ), ⁇ (y), and ⁇ ( ⁇
  • Fig. 41 (d)-Fig. 41 (f) also denote ⁇ , ⁇ and f respectively.
  • the function f (X, y) is implemented by the amplifiers HS10 to HS17.
  • FIG. 43 shows a controller circuit in which the functions shown in Table 9 are implemented. This controller contains 33 amplifiers and 93 resistive elements. In FIG. 43, high-output amplifiers PHS1 and PHS2 generate voltage signals corresponding to y and X, respectively.
  • FIG. 42 (a) shows a configuration example of HS3-HS33, and FIG. 42 (b) shows a configuration example of PHS1 and PHS2.
  • FIG. 44-FIG. 50 are graphs showing the results of SPICE simulation for the circuit shown in FIG.
  • the variable X is fixed, and the output dependency on the variable y is shown.
  • the variable y is fixed, and the output dependence on the variable X is shown.
  • the variables X and y are each changed from ⁇ 3 to +3 by 0.58333V, that is, about 1 by a logical value.
  • the variables X and y are each changed from ⁇ 3 to +3 by 0.39266 V, that is, by about 0.5 in logical values.
  • FIGS. 45 and 48 the variables X and y are each changed from ⁇ 3 to +3 by 0.39266 V, that is, by about 0.5 in logical values.
  • FIG. 50 shows a result of the SPICE simulation for the circuit shown in FIG. 43 in a three-dimensional coordinate system.
  • Table 11 shows the variables in linguistic expressions in Table 10 corresponding to the respective voltage values. However, the voltage range is 0-3.5V.
  • F (X, V) and F (X, V) are shown in Fig. 51, respectively.
  • a symmetric function F (X, V) is defined as shown in the right matrix in the same matrix.
  • the function F (X, V) can be viewed as a one-variable function for the variable (X + Y), as shown in FIG.
  • this function F ((X + Y) Z2) has two regions where the values change, and can be implemented as shown in the following equation using three amplifiers.
  • ⁇ 1 S ⁇ 6-X + 6-V- ⁇ 5
  • F (X, V) is obtained by multiplying F (X, V) and F (X, V) by 2/3.
  • F F + F.
  • the function F is based on the two variables X,
  • equation (84) becomes as follows.
  • F (X, V) S [ 7l (X, V) -3 ⁇ ... C8 S)
  • the function F is calculated by the five summing amplifiers (HS9-HS12 and HS16) in the controller circuit shown in Fig. 54. Has been implemented.
  • Function F can be implemented according to the rules expressed by the following equation.
  • K x, v) s [r, v) + ⁇ l ... (87)
  • the function F is expressed by four summing amplifiers (HS13—HS1
  • the amplifier HS16 is commonly used for mounting both functions F 1 and F 2 and realizes the following equation.
  • Equation (90) is implemented with five summing amplifiers (HS3-HS6 and HS17) in the controller circuit shown in FIG.
  • the output of the amplifier HS17 is the output of the controller in Fig. 54 and is expressed by the following equation.
  • FIG. 55—FIG. 60 are graphs showing SPICE simulation results for the circuit shown in FIG. Both graphs fix the variable X and show the dependence of the output on the variable V.
  • the variable X is set to a logical value and changed from ⁇ 3 to +3 in steps of three.
  • the variable X is set to a logical value and changed from -3 to +3 by one.
  • the domain and the range of the implemented function are respectively closed in the closed interval [k by performing parallel translation and reduction or enlargement as necessary in the X-axis direction and the y-axis direction. , k].
  • the range just fits when y y
  • ss dd ss dd is the lower limit voltage and upper limit voltage of the saturation level, respectively.
  • the relationship between the output variable q and the voltage V is the same as the above relationship between the input variable p and the voltage V, and can be obtained by replacing p in equation (94) with q.
  • the relationship between the input variable X and the voltage V is as follows.
  • q h (p) is sampled at appropriate intervals.
  • the P coordinate of the sampling point is set to P, p,
  • the sampling interval is one
  • h (k) ⁇ 0
  • Subfunction 7? (P) can be implemented using the threshold element circuit as in the following equation.
  • FIG. 64 (a) illustrates subfunctions r? I (p) for all i.
  • q h (p).
  • ⁇ ⁇ ⁇ represents a line graph obtained by connecting adjacent sampling points with a straight line, as shown in FIG. 64 (b).
  • a graph is shown only within the domain [k, k] for.
  • an arbitrary function can be implemented using the threshold element circuit. If the implemented function is curved, it will be implemented approximately. However, by setting the sampling interval appropriately, the error can be kept within an allowable range. Also, since the sampling interval does not need to be constant, it is possible to make the sampling interval relatively narrow where the radius of curvature is relatively small on the graph and make the sampling interval relatively wide where the radius of curvature is relatively large on the graph. It is possible. By doing so, it is possible to increase the mounting accuracy of the function while suppressing an increase in the number of samplings (which leads to an increase in the number of circuit elements). As shown in FIG. 65, when the implemented function is linear, an arbitrary function can be implemented theoretically without error. In this case, the non-differentiable point (the point where the slope of the straight line changes) may be set as the sampling point.
  • the non-differentiable points include points corresponding to the minimum value and the maximum value of the domain.
  • equation (100) can be implemented as shown in FIG.
  • circuits corresponding to 7 ⁇ , ⁇ and 7 ⁇ are not provided. This is a book
  • the operation corresponding to ⁇ .r? (P) is executed in two stages. That is, the amplifier SF1 performs the superposition operation of 7 ?, ⁇ , and r?
  • the operation corresponding to ⁇ ⁇ ( ⁇ ) may be performed in one stage, or may be performed in three or more stages.
  • the output from the final-stage amplifier becomes- ⁇ ⁇ ⁇ ( ⁇ ).
  • the sign of the above output may be inverted using an inverter.
  • the sign of the subfunction r? the sign of the subfunction r?.
  • Equation ( ⁇ ) may be inverted in advance, that is, a function in which h (p) in Equation (98) is replaced with h (p) may be implemented.
  • the input weights of the amplifiers SF1 to SF4 and the amplifier F are all “1”.
  • the functions are implemented by hardware, and do not require software processing by a microprocessor or the like.
  • This device can be manufactured at low cost because there is no need to mount a microprocessor. Incorporating the device into a device with a microprocessor (eg, appliances, vehicles, etc.) does not impose a burden on the microprocessor.
  • this device can be constructed with a smaller number of transistors than a microprocessor. Therefore, compared to devices that require a microprocessor, In addition, it is possible to reduce the size and power consumption, and it is unlikely that a malfunction due to thermal runaway or the like will occur. Furthermore, there is no need to develop software that only requires hardware to implement the desired function. Therefore, there is no risk of malfunction due to software bugs, so that the reliability and safety are excellent.
  • this device inputs an analog signal and outputs an analog signal, it does not require AD conversion or DA conversion. Therefore, the function can be processed with a simpler configuration.
  • a predetermined function is implemented by using a threshold element circuit.
  • the threshold element circuit has functional completeness in arbitrary multi-valued logic. Therefore, an arbitrary multi-valued logic function can be implemented by combining the threshold value element circuits such that the output of the value element circuits is superimposed on the output of a desired function.
  • the output of this threshold element circuit is fragment linear (see Fig. 10 (b)) instead of fragment constant (see Fig. 10 (a)).
  • the threshold element circuit can be used as an analog threshold element, and its output can be called an analog threshold function.
  • this device uses a threshold element circuit with such output characteristics, it can implement not only digital functions but also analog functions. On the other hand, if an element circuit having fragment-constant output characteristics is used, only digital functions can be implemented.
  • a push-pull type sum amplifier is used. These are not limited to a push-pull type, and may be a differential type or any other amplifier.
  • Fig. 1 (b) the force of ten transistors is used. Naturally, this number also has various options. For example, if you determine the relationship with the amplification factor when using six transistors, Good.
  • an inversion type operational amplifier is used as a threshold element circuit.
  • a non-inversion type operational amplifier may be used as a threshold element circuit.
  • equation (3) becomes as follows.
  • threshold element circuit It is not essential to use an operational amplifier as the threshold element circuit.
  • Other circuits having output characteristics as shown in FIG. 2 (a) may be used as threshold element circuits.
  • the fuzzy control function and the trigonometric function have been described as examples, it is apparent from the above-described series of descriptions that the present invention can be applied to any other functions.
  • the function completeness of the threshold element circuit in the multi-valued logic a device corresponding to an arbitrary function can be obtained by appropriately combining the summing amplifiers. For example, if the output logic value is an arbitrary value in Table 7, one variable (here, X) is fixed, and as shown in Equation (26), the vertical column in Table 7 for each value of X As a function of y.
  • the number of input variables may be one or three or more.
  • the input logical value may be multiplied by a constant for convenience. (In the example of Table 5, it is doubled.)
  • the constant at this time is determined so that the maximum value and the minimum value of the output logical value fall within the range of the input logical value multiplied by the constant. Also, by multiplying the output logical value by a constant ( ⁇ 1), the maximum and minimum values of the output logical value multiplied by the constant may be within the range of the input logical value.
  • the number of logical values is 3 (three-valued logic) or seven (7-valued logic) has been described as an example, but it goes without saying that the number of logical values may be other values.
  • the elements of the LUT are expressed as “logical values” for convenience, however, it is noted that the input variables and the output variables are not limited to digital variables but may be analog variables. It is clear from the description.

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Abstract

Une fonction de flou est réalisée par l'intégration d'un convertisseur AN, d'un convertisseur NA et d'un logiciel de microprocesseur, nécessitant le développement à la fois d'un logiciel et de matériel. Etant donné que l'opération est exécutée par l'intermédiaire d'un logiciel, la vitesse de l'opération est limité. Une fonction de flou est assurée par un amplificateur possédant une valeur seuil. Les six transistors (M11-16) de gauche correspondent à un corps principal d'un amplificateur de sommation utilisé comme un inverseur et les dix transistors (M1-10) de droite correspondent au corps principal de l'amplificateur de sommation.
PCT/JP2004/009442 2003-07-02 2004-07-02 Dispositif a fonction WO2005004032A1 (fr)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05289883A (ja) * 1992-04-09 1993-11-05 Omron Corp ファジイ推論装置
JPH0696242A (ja) * 1992-09-10 1994-04-08 Rohm Co Ltd メンバーシップ関数発生回路
JPH06110696A (ja) * 1992-09-29 1994-04-22 Nippon Motorola Ltd ファジイ推論のグレード演算回路
JPH06195488A (ja) * 1992-12-22 1994-07-15 Mikuni Corp ファジィ推論のためのニューラルネットワーク
JPH07200708A (ja) * 1993-12-02 1995-08-04 Csem Centre Suisse Electron & De Microtech Sa Rech & Dev ファジイ論理制御装置
JPH08274197A (ja) * 1995-03-31 1996-10-18 Sunao Shibata 半導体演算回路
JPH08329171A (ja) * 1995-03-30 1996-12-13 Fujitsu Ltd 多値論理回路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05289883A (ja) * 1992-04-09 1993-11-05 Omron Corp ファジイ推論装置
JPH0696242A (ja) * 1992-09-10 1994-04-08 Rohm Co Ltd メンバーシップ関数発生回路
JPH06110696A (ja) * 1992-09-29 1994-04-22 Nippon Motorola Ltd ファジイ推論のグレード演算回路
JPH06195488A (ja) * 1992-12-22 1994-07-15 Mikuni Corp ファジィ推論のためのニューラルネットワーク
JPH07200708A (ja) * 1993-12-02 1995-08-04 Csem Centre Suisse Electron & De Microtech Sa Rech & Dev ファジイ論理制御装置
JPH08329171A (ja) * 1995-03-30 1996-12-13 Fujitsu Ltd 多値論理回路
JPH08274197A (ja) * 1995-03-31 1996-10-18 Sunao Shibata 半導体演算回路

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