WO2004109711A1

WO2004109711A1 - Semiconductor memory having booster circuit for redundant memory

Info

Publication number: WO2004109711A1
Application number: PCT/JP2003/007104
Authority: WO
Inventors: Shigekazu Yamada
Original assignee: Fujitsu Limited
Priority date: 2003-06-05
Filing date: 2003-06-05
Publication date: 2004-12-16
Also published as: JP4142685B2; JPWO2004109711A1

Abstract

A semiconductor memory wherein a read circuit for a redundant memory is small in size and wherein the redundant memory can be appropriately read for a determined address. A semiconductor memory, which has both ordinary cells and redundant cells, comprises a plurality of redundant memories for storing redundant information related to the redundant cells; a redundant memory selection circuit for selecting, in response to an address, a part of the plurality of redundant memories to enable a reading operation; a redundant information hold circuit for holding the redundant information read from the selected redundant memory; and first and second booster circuits for generating voltages for reading the redundant memories. The first and second booster circuits alternately repeat a boost operation and a reset operation in response to address changes. Even if those address changes successively occur in a short time period, one of the first and second booster circuits generates a reading voltage each time, whereby the redundant information can be appropriately read from the selected redundant memory when the address is eventually determined.

Description

TECHNICAL FIELD A semiconductor memory having a redundant memory booster circuit

The present invention relates to a semiconductor memory having a redundant memory for storing information about a redundant cell, and more particularly to a semiconductor memory having a booster circuit that generates a boosted voltage when an address is determined. Background art

A large-capacity semiconductor memory has a redundant cell array in addition to the normal cell array in order to improve the yield. If the normal cell array includes a defective bit, the normal cell array having the defective bit is replaced with the redundant cell array. Information on the replacement with the redundant cell (hereinafter, redundant information), for example, the address of the normal cell to be replaced is stored in the redundant memory. Then, the semiconductor memory reads the redundant information in the redundant memory in response to the address change at the time of the access request, and switches to the redundant cell side according to the address destination.

Non-volatile memory such as flash memory among semiconductor memories retains the storage state even when the power of the memory cell is turned off, so that the redundant memory is also composed of the same storage element as a normal cell. For example, when a normal cell is configured by a cell transistor having a floating gate or a trap gate, the redundant memory is also configured by the same cell transistor.

On the other hand, the power supply voltage of semiconductor memory tends to be lower due to the demand for lower power consumption. Accordingly, during a program operation, a power supply voltage is boosted to generate a program voltage (for example, Patent Document 1). For the same reason, when reading information from the redundant memory, it is necessary to apply a read voltage boosted to a power supply voltage or higher to the gate of the cell transistor. For this purpose, a booster circuit for supplying a read voltage to the redundant memory is provided.

The booster circuit for the redundant memory responds to the address 'transition' detection signal (ATD) generated by detecting that the end address has been switched. Then, the boost operation is performed only once, and the information in the redundant memory is read by the boost read voltage generated by the boost operation, and the switching to the redundant cell is controlled.

[Patent Document 1]

Japanese Patent Application Laid-Open No. Hei 6—2 2 3 5 8 8

As the capacity of the memory increases, the configuration of the redundant cells becomes more complicated, and the amount of redundant information stored in the redundant memory is increasing. Therefore, as in the conventional method, the booster circuit performs a boosting operation only once at the time of an address change to generate a read voltage, and reads the redundant information of the redundant memory based on the read voltage. There is a problem that the power consumption by the read operation increases with the increase of the capacity. Further, in order to read all data in the redundant memory with the boosted read voltage generated only once at the time of the address change and select redundant information corresponding to an access destination according to the determined address, all the redundant memories are used. It is necessary to provide a circuit that detects and holds the read data. Therefore, there is a problem that the circuit scale of the data detection circuit and the data holding circuit increases. Disclosure of the invention

Therefore, an object of the present invention is to provide a semiconductor memory capable of appropriately reading stored data of a part of redundant memories corresponding to an access destination.

In order to achieve the above object, according to one aspect of the present invention, in a semiconductor memory having a normal cell and a redundant cell, a plurality of redundant memories for storing redundant information related to the redundant cell; A redundant memory selection circuit that selects a part of the redundant memories according to an address among the redundant memories and performs a read operation; a redundant information holding circuit that holds redundant information read from the selected redundant memory; First and second booster circuits for generating a read voltage of the redundant memory, wherein the first and second booster circuits alternately perform a boost operation and a reset operation in response to an address change. And is repeated.

According to the above aspect of the invention, even if the address change occurs continuously in a short time, one of the first and second booster circuits generates the read voltage each time, so that the address is finally Appropriately read the redundant information of the selected redundant memory when confirmed Can be

To achieve the above object, according to a second aspect of the present invention, in a semiconductor memory having a normal cell and a redundant cell, a plurality of redundant memories storing redundant information on the redundant cell; A redundant memory selection circuit for selecting and performing a read operation by selecting a part of the redundant memories according to the determined address at the time when the address is determined, and reading from the selected redundant memory. A redundant information holding circuit for holding redundancy information, and a booster circuit for generating a read voltage of the redundant memory at a timing at which the address is determined after the change of the end address.

According to the aspect of the present invention, since the booster circuit generates the read voltage at the timing when the address force is determined, the redundant memory can be selected and read based on the determined address even if the address changes continuously occur. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is an overall configuration diagram of a semiconductor memory according to the present embodiment.

FIG. 2 is a diagram illustrating a redundant memory, a selection circuit, and a sense amplifier latch circuit according to the present embodiment.

FIG. 3 is a timing chart illustrating a problem of the booster circuit due to a change in address.

FIG. 4 is a diagram illustrating a specific example of the booster circuit according to the present embodiment.

FIG. 5 is a timing chart showing the operation of the booster circuit.

FIG. 6 is a diagram illustrating the configuration and operation of the first booster circuit.

FIG. 7 is a diagram showing a booster drive signal generation circuit and an operation timing chart. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the scope of protection of the present invention is not limited to the following embodiments, but extends to the inventions described in the claims and their equivalents. FIG. 1 is an overall configuration diagram of a semiconductor memory according to the present embodiment. This semiconductor memory is exemplified by a flash memory. The memory core has a normal cell array 10 and a redundant cell array 12. The normal cell array 10 has four sectors SEC0 to SEC4, and the redundant cell array 12 has one redundant sector RSEC. The sector having a defective bit in the normal cell array is configured to be replaced with a redundant sector. The address ADD supplied from the outside is input to the address buffer 18, and the input address is supplied to each decoder. The X address ADDx is supplied to the X decoder XDEC, the Y address ADDy and the sector address ADDs are supplied to the Y decoder YDEC, and the address ADDr required for selecting the redundant memory is supplied to the redundant decoder. Y gates 14 and 16 are provided on the normal cell array 10 side and the redundant cell array 12 side, respectively, and column selection is performed by selection signals from the corresponding decoders. The outputs of the Y gates 14 and 16 are detected by the read circuit 20 and output to the outside.

Redundant information such as a sector address to be replaced is stored in the redundant memory 22 and becomes readable by the boosted read voltage VRG generated by the booster circuit 36. The redundant memory is provided with a selection circuit 24 for selecting and driving the redundant memory selected by the redundant decoder 26 according to the determined redundant address ADDr. The data of the redundant memory selected by the selection circuit 24 is detected and latched by the sense amplifier / latch circuit 28. Therefore, only some of the redundant memories 22 are selected, read-driven, and the read data is held in the latch circuit 28. The replacement target sector address held in the latch circuit 28 and the sector address ADDs from the address buffer 18 are compared by the comparison circuit 30. When they match, the redundancy signal S30 outputs the Y signal of the normal cell array. The decoder YDEC is deactivated, and the Y decoder DECr in the redundant cell array is activated. As a result, the sector of the normal cell array is not selected, and the redundant sector of the redundant cell array is selected. When the comparison circuit 30 detects a mismatch, the normal cell array sector is selected.

The ATD generation circuit 32 detects the change of the external address ADD and generates an address change detection pulse ATD which becomes H level for a predetermined time. External address ADD changes If there is no address change for a predetermined time, it is considered that the address has been determined, and the equalize signal generation circuit 38 generates the equalize signal EQ in response to the L level of the address change detection pulse ATD. In response to the equalizing signal EQ, the operation of the memory core starts. Therefore, the equalize signal is supplied to each decoder. That is, the timing when the equalize signal EQ becomes H level is the address setting timing.

Also, in response to the short pulse detection pulse ATDx generated by the ATD generation circuit 32 in response to all address changes, the boost drive signal generation circuit 34 controls the boost operation and reset operation of the booster circuit 36 The first and second boost drive signals ATD1 and ATD2 are generated. The booster circuit 36 has first and second booster circuits that alternately perform a boosting operation and a reset operation in response to first and second boost drive signals ATD1 and ATD2, as described later.

FIG. 2 is a diagram illustrating a redundant memory, a selection circuit, and a sense amplifier latch circuit according to the present embodiment. The redundant memory 22-0 has a redundant memory transistor RM0 having a floating gate or a trap gate, and a read voltage VRG is applied to its control gate. On the drain side, an inverter 50 and a level shift circuit 51 for program operation are provided. When the selection signal S0 at the time of programming is at the H level, the program voltage VPRGM is applied to the drain of the redundant memory transistor RM0. Applied. Further, an erase voltage VER for an erase operation is applied to the source side, and the source voltage VER becomes ground level during a program operation and a read operation, and the source voltage VER is high during an erase operation. Controlled by level. Another redundant memory 22-1 has the same configuration as above.

When writing redundant information into the redundant memory 24, the program voltage VPRGM is applied to the gate of the redundant memory transistor by the selection signals S0 and S1, and electrons are injected into the floating gate or trap gate. This increases the threshold voltage of the redundant memory transistor.

The selection circuit 24 is composed of transistors 24-0 and 24-1, respectively, and each gate is supplied with the selection signals SEL0 and SEL1 from the redundant decoder 26 and is turned on. Is done. The sense amplifier's latch circuit 28 has a load transistor 40 common to the redundant memories.

In the read operation of the redundant memory, when the address is determined, the redundant decoder 26 supplies the selection signal SEL0.SEL1 in response to the equalize signal EQ, and turns on one of the transistors of the selection circuit 24. At this time, the boosted read voltage VKG is supplied to the gate of each redundant memory transistor. Therefore, a drain current is generated in accordance with the threshold state of the redundant memory transistors RM0 and RM1, and the voltage comparison circuit 41 compares the drain voltage with the reference voltage REF, and the detected redundant data is latched by the latch circuit 4 2 Latches.

Therefore, in the redundant memory transistors RM0 and RM1, a drain current is generated only in the transistor selected by the selection circuit 24 and read-out is performed, and no drain current is generated in all the redundant memory transistors. Power consumption has been reduced. In addition, since the selection circuit 24 performs the selection operation when the address is determined, the read voltage VRG supplied to the redundant memory needs to be set to a level that is surely boosted when the address is determined. .

FIG. 3 is a timing chart illustrating a problem of the booster circuit due to a change in address. As described with reference to FIG. 1, when the address changes, the ATD generation circuit 32 changes the address change detection signal ATD to the H level, and maintains the H level state until a predetermined time T 0 elapses after the address change. When the predetermined time TO elapses, the address is determined to be fixed, and the ATD generation circuit 32 sets the address change detection signal ATD to the L level. In response, the equalize signal EQ changes to the H level. A problem with this operation is that the end address changes again before the predetermined period TO has elapsed. In response to the change of the address again, the H level period of the address change detection signal ATD is extended, and the timing for determining the address is delayed. However, even if the booster circuit performs the boosting operation in response to the H level of the address change detection signal ATD, and the booster output BOOST and the read voltage VKG are boosted (Bl in the figure), the boosting state does not occur in a short time. Then, the boost operation needs to be performed again after the reset period RST. When the voltage is boosted again after this reset period RST (B 2 in the figure), the H level of the equalize signal EQ that controls the operation start of the memory core There are cases where the timing cannot be met.

The problem of such a booster circuit is that the booster circuit performs only one boosting operation.However, since the redundant memory is read each time the booster circuit is accessed, the booster circuit that generates the read voltage for that is as little as possible. A simple circuit configuration is preferable, and a circuit configuration that maintains the level of the read voltage boosted for a long time is not preferable from the viewpoint of power consumption.

FIG. 4 is a diagram illustrating a specific example of the booster circuit according to the present embodiment. The booster circuit 36 has a first booster circuit 60 and a second booster circuit 70. The first booster circuit 60 performs a boosting operation when the first booster drive signal ATD1 goes to H level, and performs a reset operation when it goes to L level. Similarly, the second booster circuit 70 performs a boosting operation when the second booster drive signal ATD2 goes to H level, and performs a reset operation when it goes to L level. Since the first and second booster drive signals ATD1 and ATD2 are generated alternately, the first and second booster circuits 60 and 70 alternately repeat the boosting operation and the reset operation.

The level shift circuits 61 and 71 set the control signals S61 and S71 to L level in response to the H level of the first and second booster drive signals ATD1 and ATD2, and the P-channel transistors 62, 63 and The first and second booster circuits 60 and 70 output the boosted signal BOOST1,2 as the read voltage VRG. In other words, the power supply level Vcc of the first and second booster drive signals ATD1,2 is level-shifted to the boost level.

The read voltage VEG generated by the booster circuit 36 is supplied to the plurality of redundant memories 22 and the redundant memory transistor RM0_RMn corresponding to the selection signal SELO—SELn generated by the redundant decoder 26 is supplied to the sense amplifier 28A. Connected and the data read operation is performed.

FIG. 5 is a timing chart showing the operation of the booster circuit. When an address change occurs at time tl, the ATD generation circuit 32 changes the address change detection signal ATD to H level. In response to this address change, a detection pulse ATDx is generated, and the first booster drive signal ATD1 becomes H level. In response, the first booster circuit 60 starts the boosting operation, the selection signal S61 goes to the L level, and the boosted The boost voltage BOOST1 is supplied to the redundant memory 22 as the read voltage VRG. Further, when an address change occurs again at time t2 within a predetermined time TO required for address determination from the first address change, the H level of the address change detection signal ATD is maintained, and the second level is responded to the detection pulse ATDx. The booster drive signal ATD2 becomes H level. In response, the second booster circuit 70 starts the boost operation, the select signal S71 goes to the L level, the boosted boost voltage BOOST2 is applied to the read voltage VRG, and the read voltage VRG becomes the boost level. To maintain. At this time, the first booster circuit 60 is reset, and prepares for the next boosting operation.

When a predetermined time TO elapses from the second address change, the address is determined, the address change detection signal ATD becomes L level, the equalize signal EQ becomes H level, the decoder determines the decode signal, and the memory core operates. Start. At this timing, the read voltage VKG is set to the boosted level, so that some of the redundant memory transistors selected from the plurality of redundant memories 22 by address determination perform a read operation, and the sense amplifier 28 A And is latched by the latch circuit 28B. Therefore, it is possible to perform the read operation only for the redundant memory necessary when the address is determined, and it is not necessary to provide the sense amplifier circuit and the latch circuit for all the redundant memories.

FIG. 6 is a diagram illustrating the configuration and operation of the first booster circuit. The configuration and operation of the second booster circuit are the same. The first booster circuit 60 receives a first booster drive signal ATD1 and generates control signals 1B and 2B, a control signal generation unit 60A, inverters 65 and 66, and an inverter 67. It has a P channel transistor 68 and a capacitor 69. As shown in the timing chart of FIG. 6 (B), in response to the H level of the first booster drive signal ATD1, the first control signal 1B goes to the L level, and the inverter 67 is turned on via the transistor 68. Raises the output BOOST1 to the power supply voltage Vcc. Immediately thereafter, the second control signal 2B becomes L level, and the electrode of the capacitor 69 is driven to the power supply voltage Vcc via the transistor 65 of the inverters 65 and 67. As a result, the output BOOST1 rises to the boosting level Vpp higher than the power supply voltage Vcc due to the force pulling operation of the capacitor 69. Then, in response to the L level of the first booster and drive signal ATD1, the first and second Control signals 1 B and 2 B go to H level, and the first booster circuit is reset. That is, in the reset operation, one electrode of the capacitor 69 is pulled down to the ground level via the transistor 66, while the output BOOST1, which is the opposite electrode of the capacitor, is maintained at the ground level by the inverter 67. Thus, this reset operation requires a predetermined time.

FIG. 7 is a diagram showing a booster drive signal generation circuit and an operation timing chart. As shown in FIG. 7A, the booster and drive signal generation circuit 34 generates the first and second booster drive signals ATD1 and ATD2 every time the address changes from the address change detection signal ATD and the detection pulse ATDx. Alternately set to H level. The booster drive signal generation circuit 34 is composed of a front stage circuit and a rear stage circuit. The front stage is configured by a latch circuit including a transfer gate 80, a P-channel transistor 82, and inverters 84 and 85. It is composed of a latch circuit composed of a transfer gate 81, a P-channel transistor 83, and inverters 87, 88, and the preceding and succeeding stages are connected via an inverter 86.

The operation will be described with reference to the timing chart of FIG. 7B. Before the time tl, the address change detection signal ATD is at the L level, and the nodes N82 and N83 are both at the H level. As a result, both drive signals ATD1 , ATD2 is at L level. When an address change occurs at time t1, the end address change detection signal ATD becomes H level, the transistors 82 and 83 become non-conductive, and the two transfer gates 80 and 81 cause The first and second stages generate drive signals ATD1 and ATD2 alternately. At the address change at time t1, the transfer gate 80 conducts for a short time, the node N82 becomes L level in response to the L level of the signal ATD1, and the latch circuits 84, 8 are closed when the transfer gate 80 is closed. 5 is inverted, and the first booster drive signal ATD1 becomes H level. At this time, the transfer gate 81 also conducts for a short time. The output of the inverter 86 is still at the H level, and the second booster drive signal ATD2 does not change. However, when the first booster drive signal ATD1 goes high, the output of the inverter 86 goes low.

Next, when the address changes at time t2, the transfer gate 81 conducts for a short time, inverting the latch circuits 87, 88, and the second booster drive signal ATD2 becomes high. Become a level. At the same time, the transfer gate 80 conducts, the node N82 goes high, and the first booster drive signal ATD1 goes low.

By repeating the above operation, each time the address change occurs, the first and second booster drive signals ATD1 and ATD2 alternately go to the H level. This operation continues while the address change detection signal ATD remains at the H level. That is, the first and second booster drive signals ATD1 and ATD2 are alternately generated until the address is determined, and the booster circuit 36 generates the boosted read voltage VRG without delaying the equalize signal EQ. . Therefore, even if the address changes continuously, a part of the redundant memory can perform the read operation at the timing when the address is finally determined.

In the above embodiment, the first and second booster circuits alternately perform the boosting operation and the reset operation. The present invention is not limited to this, and the booster circuit may have three or more booster circuits. In that case, each booster circuit starts the boosting operation in response to the address change, returns to the reset state after boosting for a certain period of time. However, the plurality of booster circuits start boosting operation sequentially in response to successive address changes. Then, after the first address change of the successive address changes, the plurality of booster circuits sequentially perform the boosting operation, and after the last address change, at the address determination timing, the boosted voltage from the booster circuit that last performed the boosting operation is used as the read voltage. Used. In this way, a boosted voltage can always be generated in response to an address change, and a boosted voltage is generated one after another in response to a subsequent address change. It is also possible to supply a boosted read voltage.

As described above, according to the present embodiment, it is possible to read out the redundant information by reading out a part of the memory of the redundant memory at the timing of determining the address, thereby achieving power saving and small circuit scale reduction. Can be planned. Industrial potential

As described above, according to the present invention, the readout circuit of the redundant memory can be reduced in size, and the semiconductor memory capable of appropriately reading the redundant memory for the determined address can be obtained. To provide

Claims

The scope of the claims

1. In a semiconductor memory having normal cells and redundant cells,

A plurality of redundant memories for storing redundant information on the redundant cells;

A redundant memory selection circuit that selects a part of the redundant memories according to an address among the plurality of redundant memories and performs a read operation;

A redundant information holding circuit for holding redundant information read from the selected redundant memory;

A first and a second booster circuit for generating a read voltage of the redundant memory,

A semiconductor memory, wherein the first and second booster circuits alternately repeat a boosting operation and a reset operation in response to a change in the address change.

2. In Claim 1,

In response to a first address change in response to successive address changes, the first or second booster circuit starts a boost operation, and in response to a last address change, the first or second booster circuit. Performing a boosting operation and thereafter stopping the boosting operation.

3. In Claim 2,

A semiconductor memory, wherein a memory operation start signal is generated at a timing of determining an address after the last address change.

4. In claim 1,

A memory operation start signal is generated at a fixed timing of the address after the last address change with respect to a continuous address change, and the redundant memory selection circuit performs a selection operation in response to the operation start signal. Semiconductor memory.

5. In Claim 1 A semiconductor memory, wherein one of a normal cell and a redundant cell is selected based on the read redundant information.

6. In Claim 1,

While the first booster circuit performs a boost operation, the second booster circuit performs a reset operation, and while the first booster circuit performs a reset operation, the second booster circuit performs a boost operation. A semiconductor memory.

7. In Claim 1,

In response to the first address change in response to successive address changes, an address change detection signal is generated, and while the address change detection signal is active, the first and second booster circuits are activated, Further, the first and second booster drive signals are generated alternately in response to the address change, and the first and second booster circuits are boosted in response to the first and second booster drive signals. A semiconductor memory characterized by performing operations.

8. In a semiconductor memory having normal cells and redundant cells,

A redundancy memory selection circuit for selecting and performing a read operation on a part of the plurality of redundant memories at a timing when the address is determined according to the determined address,

A booster circuit for generating a read voltage of the redundant memory at a timing when the address is determined after the address is changed.

9. In Claim 8,

A semiconductor memory, wherein the booster circuit has a plurality of booster circuits, and the plurality of booster circuits sequentially perform a boosting operation every time the address changes.