JP2001023384A - Semiconductor integrated circuit device, and supply method of verify-voltage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent delay of a time required for rewriting data and to prevent erroneous discrimination of the data by supplying optimum verify-voltage in accordance with the number of times of rewriting the data. SOLUTION: In the semiconductor integrated circuit device, at the time of rewriting operation of a flash memory, a rewriting number of times discrimination control circuit 15 reads out data of the number of times of rewriting for each sector from a rewriting number of times storing region 14, and outputs a verify-voltage control signal and a switching control signal in accordance with the above to a verify-voltage output circuit 17 and a switching circuit 18. The verify-voltage output circuit 17 selects verify-voltage being suitable for each sector out of verify-voltage V0-Vn generated by a verify-voltage generating circuit 16 and output it to the switching circuit 18. The switching circuit 18 switches an objective of output of the inputted verify-voltage based on a switching control signal, and output is so that the verify-voltage being optimum for each sector is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for improving the reliability of a nonvolatile memory, and more particularly to a technology effective when applied to prevention of delay in data rewriting speed and prevention of erroneous rewriting.

[0002]

2. Description of the Related Art According to studies made by the present inventor, a flash memory is an example of a semiconductor integrated circuit device capable of electrically writing and erasing data. In this flash memory, when writing and erasing data to and from a memory cell, a tunnel current flows through the entire channel portion of the memory cell to discharge and inject charges at a floating gate.

[0003] As an example describing this type of semiconductor integrated circuit device in detail, see, for example, June 1, 1995.
Published by Industrial Research Institute Co., Ltd., Masashi Oshima (ed.), "Electronic Materials" June Issue (Vol. 34, No. 6), and P32 to P37. This document describes the configuration of flash memory and the like. .

[0004]

However, the present inventor has found that there are the following problems in the data writing and erasing techniques in the semiconductor integrated circuit device as described above.

That is, in the above-described memory cell, when data writing and erasing are repeated, the threshold voltage of the transistor constituting the memory cell rises due to deterioration of the tunnel film and the like, so that data writing and erasing are delayed. There is a problem that it becomes.

Further, a delay in data writing and erasing causes a narrowing of a threshold region, which may cause erroneous data determination and impair the reliability of the semiconductor integrated circuit device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing a delay in the time required for a data rewrite operation and preventing erroneous data determination by supplying an optimum verify voltage in accordance with the number of data rewrites. An object of the present invention is to provide an integrated circuit device and a method of supplying a verify voltage.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit device of the present invention, a rewrite frequency storage area for storing the number of data rewrites (write / erase) for each bit unit composed of a certain number of bits, and a rewrite frequency storage area for storing the rewrite frequency storage area Read the number of times of data rewriting, and determine the number of times of data rewriting for each bit unit,
Based on the result, a verify voltage corresponding to each bit unit is calculated, a verify control unit that outputs a verify voltage control signal and a switching control signal, and a verify voltage generator that generates a plurality of verify voltages of different voltage levels Unit, a selection output unit that selects and outputs the verify voltage generated by the verify voltage generation unit based on the verify voltage control signal output from the determination control unit, and a switching control signal output from the determination control unit. And a voltage switching unit for switching a supply destination of the verify voltage selected by the selection output unit and outputting a verify voltage corresponding to each bit unit.

Further, in the semiconductor integrated circuit device according to the present invention, a bit unit of the number of rewrites of data stored in the rewrite number storage area is either a sector unit or a block unit.

Further, according to the semiconductor integrated circuit device of the present invention,
A current comparison bit region provided with a comparison memory cell in which data has been rewritten in advance at an arbitrary number of times, and a sector or a sector in which data is to be rewritten in each of the comparison memory cells and the memory cell array in the current comparison bit region. A comparison / determination control unit that compares a read current with an arbitrary memory cell selected for each block unit and outputs a verify voltage control signal and a switching control signal based on the comparison result; and a plurality of verify voltages of different voltage levels. A verify voltage generating unit that generates a verify voltage, a select output unit that selects and outputs a verify voltage generated by the verify voltage generating unit based on a verify voltage control signal output from the comparison / determination control unit, The verify output selected by the selection output unit based on the output switching control signal Switches the supply destination of Lee voltage, but with more composed verify voltage generation control means and voltage switching unit to output a verify voltage commensurate for each sector or block.

Further, according to the verify voltage supply method of the present invention, when data is rewritten, the verify voltage suitable for each sector or block is determined from the number of data rewrites for each sector or block in which data rewrite is performed. Based on the result of the determination, a verify voltage suitable for each sector or block unit is selected from a plurality of verify voltages of different voltage levels, and the supply destination of the selected verify voltage is switched. It is output for each sector or block.

Further, according to the verify voltage supply method of the present invention, when data is rewritten, a comparison memory cell in which data is rewritten in advance at an arbitrary number of times and a sector in the memory cell array in which data is rewritten. Alternatively, a read current with an arbitrary memory cell selected for each block unit is compared, a verify voltage suitable for each sector or block unit is determined, and verify voltages of a plurality of different voltage levels are determined based on the determination result. Then, a verify voltage suitable for each sector or block unit is selected, the supply destination of the selected verify voltage is switched, and output is performed for each sector or block unit.

As described above, the verify voltage is supplied at the optimum voltage level for each sector or block. Therefore, even if the threshold value of the memory cell is increased due to the increase in the number of data rewrites, the write and erase time can be reduced. Delay can be greatly reduced, and erroneous data determination can be prevented.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a flash memory according to Embodiment 1 of the present invention, and FIG.
FIG. 3 is a block diagram of a verify voltage generation control unit provided in the flash memory according to the embodiment of the present invention. FIG. 3 is an explanatory diagram of a flash memory cell array provided in the flash memory according to the embodiment of the present invention. FIG. 5 is a flowchart of a rewriting operation in the flash memory according to the first embodiment of the present invention. FIG.

In the first embodiment, a flash memory (semiconductor integrated circuit device) 1 includes, as shown in FIG.
A logic control 2 and an input / output control circuit 3 are provided. The logic control 2 temporarily stores a control signal input from a host such as a microcomputer to be connected, and controls operation logic.

The input / output control circuit 3 receives various signals such as commands, external addresses, and program data input / output from the host, and outputs commands, external addresses, and data to the respective commands based on control signals. It outputs to register 4, address register 5, and data register / sense amplifier 6.

A column address buffer 7 and a row address buffer 8 are connected to the address register 5. The column address buffer 7 and the row address buffer 8 temporarily store the address output from the address register 5.

A column address decoder 9 is connected to the column address buffer 7, and a row address decoder 10 is connected to the row address buffer 8. The column address decoder 9 performs decoding based on the column address output from the column address buffer 7, and the row address decoder 10 performs decoding based on the row address output from the row address buffer 8.

A control circuit 11 is connected to the logic control 2 and the command register 4, and the control circuit 11 controls the data register / sense amplifier 6.

The data register / sense amplifier 6 and the row address decoder 10 are connected to a flash memory cell array 12 capable of electrically erasing data and requiring no power supply for storing data. In the flash memory cell array 12, memory cells, which are the minimum units of storage, are regularly arranged in an array. In the memory cells provided in the flash memory cell array 12, for example, data writing and erasing are performed by flowing a tunnel current over the entire channel portion of the memory cell, and discharging and injecting charges in the floating gate.

A verify voltage generation control section (verify voltage generation control means) 13 is connected to the input / output control circuit 3. The verify voltage generation control unit 13 generates a verify voltage used for a verify operation, controls the voltage, and performs voltage control on the memory cell array 12.
To supply.

Next, the circuit configuration of the verify voltage generation controller 13 will be described.

As shown in FIG. 2, the verify voltage generation control section 13 includes a rewrite frequency storage area (rewrite frequency storage area) 14, a rewrite frequency determination control circuit (determination control section).
15, a verify voltage generating circuit (verify voltage generating unit) 16, a verify voltage output circuit (select output unit) 1
7 and a switching circuit (voltage switching unit) 18.

As shown in FIG. 3, the rewrite frequency storage area 14 is provided in a part of the data management area of the flash memory cell array 12, and stores the number of rewrites of data in each sector. The sector is a unit in which data is erased, read, and written, and is provided in the data area of the flash memory cell array 12.

The rewrite frequency determination control circuit 15 reads the number of rewrites of data in each sector stored in the rewrite frequency storage area 14, and outputs a verify voltage control signal based on the read rewrite frequency, to the verify voltage output circuit 17, And a switching circuit 18 for controlling the output of the verify voltage.

The verify voltage generation circuit 16 generates a plurality of verify voltages V0 to Vn. The verify voltage output circuit 17 selects and outputs the verify voltages V0 to Vn generated by the verify voltage generating circuit 16 based on the switching control signal of the rewrite number determination control circuit 15.

The verify voltage output circuit 17 includes, for example, transistors T1 to Tn. The transistors T1 to Tn are turned on / off by a verify voltage control signal input to the gates of the transistors T1 to Tn. Verify voltages V0 to Vn generated by verify voltage generating circuit 16 are selectively output.

The switching circuit 18 supplies the optimum verifying voltage to each sector by switching the connection destination of the verifying voltage to be supplied for each sector based on the switching control signal of the rewrite number determination control circuit 15. .

Next, the operation of the present embodiment will be described with reference to FIG.
3 and FIG. 4 and an explanatory diagram of the number of times of data rewriting and the threshold value in the memory cell of FIG.

First, when the rewriting operation of the flash memory 1 is performed, the rewriting number determination control circuit 15 in the verify voltage generation control unit 13 uses the rewriting number data of the sector stored in the rewriting number storage area 14 for each sector. Then, the data on the number of times of rewriting of the sector to be rewritten or erased is read out via the input / output control circuit 3 (step S101).

The rewrite frequency determination control circuit 15 reads the rewrite frequency data for each sector stored in the rewrite frequency storage area 14 and outputs a verify voltage control signal corresponding to the rewrite frequency data to the verify voltage output circuit 17. .

The verify voltage output circuit 17
Based on the input verify voltage control signal, a verify voltage corresponding to the rewrite frequency data for each sector is selected from the verify voltages V0 to Vn generated by the verify voltage generating circuit 16 and output to the switching circuit 18.

Here, the selected verify voltage is set, for example, such that the voltage level becomes higher every 10 ⁿ rewrites. Also, as shown in FIG. 5, the verify voltage and the number of rewrites are correlated by previously measuring the characteristic change between the number of data rewrites and the threshold in the memory cell, and the verify voltage is changed to the write state in the memory cell. Is set at a voltage level intermediate between the threshold value of the threshold voltage and the threshold value in the erased state.

The switching circuit 18 switches the supply destination of each input verify voltage based on the switching control signal of the number-of-times-of-rewriting determination control circuit 15, and outputs a verify voltage suitable for each sector. An optimum verify voltage is set for each time (step S102).

Thereafter, data write and erase operations are started (step S103), and verify operations such as erase verify and write verify are performed (step S104), and the write and erase operations in the flash memory 1 are completed (step S105). ). After the end of the write / erase operation, the number of rewrites of the corresponding sector stored in the storage area 14 is updated (step S1).
06).

Thus, in the present embodiment, even if the threshold value of the memory cell increases due to the increase in the number of times of rewriting of data, the verify voltage generation control unit 13
Since the optimum verify voltage is supplied for each sector, the delay of data rewriting time can be greatly reduced,
In addition, erroneous determination of data can be prevented.

(Embodiment 2) FIG. 6 is a block diagram of a verify voltage generation control unit provided in a flash memory according to Embodiment 2 of the present invention, and FIG. 7 is a flash memory according to Embodiment 2 of the present invention. And FIG. 8 is a flowchart of a rewriting operation in the flash memory according to the second embodiment of the present invention.

In the second embodiment, the flash memory 1 (FIG. 1) includes a logic control 2, an input / output control circuit 3, a command register 4, an address register 5, and a data register / similar to the first embodiment.
It comprises a sense amplifier 6, a column address buffer 7, a row address buffer 8, a column address decoder 9, a row address decoder 10, a control circuit 11, a flash memory cell array 12, and a verify voltage generation control section (verify voltage generation control means) 13a. ing.

The verify voltage generation controller 13a
As shown in FIG. 6, a verify voltage generating circuit 16, a verify voltage output circuit 17, and a switching circuit 18, which are the same as in the first embodiment,
And a current comparison / determination control circuit (comparison / determination control unit) 20.

The current comparison bit area 19 is an area provided with a current comparison memory cell to which data has been written or erased a predetermined number of times (for example, 10 ² to 10 ⁿ ) or to which a stress corresponding thereto has been applied. As shown in FIG. 7, the flash memory cell array 12 is provided in a part of the data management area.

The current comparison / judgment control circuit 20 compares the data read current of the current comparison memory cell in the rewrite frequency storage area 14 with the data read current of the normal memory cell, and performs verify voltage control based on the comparison result. A signal is output to the verify voltage output circuit 17 and the switching circuit 18 to control the output of the verify voltage.

Here, the normal memory cell is any one memory cell selected from each sector in the flash memory cell array 12 where writing and erasing are performed.

Next, the operation of the verify voltage generation control section 13a will be described with reference to the flowcharts of FIGS. 6, 7, and 8.

First, when the rewriting operation of the flash memory 1 is performed, the current comparison bit area 19 of the flash memory cell array 12 is stored in the flash memory 1.
First, a current comparison memory cell to which a predetermined number of times of data writing, erasing, or a stress equivalent thereto has been applied is prepared in advance (step S201).

The current comparison / judgment control circuit 20 determines the read current of the current comparison memory cell and the normal memory cell
The read current in the normal memory cell of the sector to be rewritten is compared with the read current (step S202), and the number of times of rewriting of each normal memory cell is determined from the current comparison memory cells having the same or similar current value (step S202). S203), the number of times of data rewriting in each sector is determined.

Then, the current comparison / judgment control circuit 20 outputs a verify voltage control signal to the verify voltage output circuit 17. The verify voltage output circuit 17 outputs a verify voltage generating circuit 16 based on a verify voltage control signal.
Selects and outputs a verify voltage corresponding to the number of times of rewriting in each sector from the verify voltages V0 to Vn generated by.

The current comparison / judgment control circuit 20 also outputs a switching control signal to the switching circuit 18. The switching circuit 18 switches and outputs the verify voltage selected by the verify voltage output circuit 17 based on the input switching control signal so that a verify voltage corresponding to each sector is supplied to each sector. Thus, the optimum verify voltage is set for each sector (step S204).

Also in this case, the verify voltage is set to be at a voltage level intermediate between the threshold value of the write state in the memory cell and the threshold value of the erase state in the memory cell.

Thereafter, data write and erase operations are started (step S205), and verify operations such as erase verify and verify read are performed (step S206).
The erasing operation ends (step S207).

Thus, also in the second embodiment,
The number of rewrites in the flash memory 1 increases,
Even if the threshold value of the memory cell becomes high, the verify voltage generation control section 13a supplies the optimum verify voltage for each sector, so that the delay of the rewriting and erasing time can be greatly reduced, and the erroneous data judgment is performed. And the like can be prevented, so that the reliability of the flash memory 1 can be improved.

Also, since the number of memory cells for current comparison can be reduced, the current comparison bit region 19 can be reduced, and the layout area of the semiconductor chip can be reduced. Further, since the optimum verify voltage is set by current comparison, the verify voltage can be supplied in a shorter time.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first and second embodiments, the supply of the verify voltage is performed in units of sectors. However, the verify voltage is set and supplied in units of one block (for example, 8 sectors = 1 block). You may.

[0057]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the verify voltage generation control means sets and supplies the verify voltage to the optimum voltage level for each sector or block in accordance with the number of data rewrites, so that the data is rewritten. Time delay can be significantly reduced, and erroneous data determination can be prevented.

(2) In the present invention, the verify voltage is supplied at the optimum voltage level for each sector or block unit, so that the number of times of data rewriting can be greatly improved.

(3) Further, in the present invention, the reliability of the semiconductor integrated circuit device can be improved by the above (1) and (2).

[Brief description of the drawings]

FIG. 1 is a block diagram of a flash memory according to an embodiment of the present invention.

FIG. 2 is a block diagram of a verify voltage generation control unit provided in the flash memory according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of a flash memory cell array provided in the flash memory according to the embodiment of the present invention.

FIG. 4 is a flowchart of a rewriting operation in the flash memory according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of the number of times of data rewriting and a threshold in a memory cell.

FIG. 6 is a block diagram of a verify voltage generation control unit provided in a flash memory according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a flash memory cell array provided in a flash memory according to a second embodiment of the present invention.

FIG. 8 is a flowchart of a rewriting operation in the flash memory according to the second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Flash memory (semiconductor integrated circuit device) 2 Logic control 3 I / O control circuit 4 Command register 5 Address register 6 Data register / sense amplifier 7 Column address buffer 8 Row address buffer 9 Column address decoder 10 Row address decoder 11 Control circuit 12 Flash Memory cell array 13 Verify voltage generation control section (verify voltage generation control means) 13a Verify voltage generation control section (verify voltage generation control means) 14 Rewrite count storage area (rewrite count storage area) 15 Rewrite count determination control circuit (determination control section) 16 Verify voltage generation circuit (verify voltage generation unit) 17 Verify voltage output circuit (selection output unit) 18 Switching circuit (voltage switching unit) 19 Current comparison bit area 20 current comparison judgment control circuit (comparison determination control unit) V0～Vn verify voltage

Claims (5)

[Claims] 1. A rewrite frequency storage area for storing a data rewrite frequency for each bit unit composed of a certain number of bits, and a data rewrite frequency stored in the rewrite frequency storage area are read, and each bit unit is read. A judgment control unit for judging the number of data rewrites for each bit, calculating a verify voltage corresponding to each bit unit based on the result, and outputting a verify voltage control signal and a switching control signal; A verify voltage generator that generates a verify voltage of a level, a selection output unit that selects and outputs a verify voltage generated by the verify voltage generator based on a verify voltage control signal output from the determination controller; Based on the switching control signal output from the determination control unit, A semiconductor integrated circuit device comprising a verify voltage generation control means comprising a voltage switching unit for switching a supply destination of the verify voltage selected by the selection output unit and outputting a verify voltage corresponding to each bit unit. . 2. The semiconductor integrated circuit device according to claim 1, wherein a bit unit of the number of rewrites of data stored in the rewrite number storage area is one of a sector unit and a block unit. Semiconductor integrated circuit device. 3. A current comparison bit area provided with a comparison memory cell in which data has been rewritten in advance at an arbitrary number of times, each comparison memory cell in the current comparison bit area, and a data A comparison determination control unit that compares a read current with an arbitrary memory cell selected for each sector or block to be rewritten, and outputs a verify voltage control signal and a switching control signal based on the comparison result; A verify voltage generator for generating verify voltages of different voltage levels; and a selection output for selecting and outputting a verify voltage generated by the verify voltage generator based on a verify voltage control signal output from the comparison / determination controller. And a switching control signal output from the comparison / determination control unit. And a voltage switching unit for switching a supply destination of the verify voltage selected by the selection output unit and outputting a verify voltage corresponding to each sector or block unit. Semiconductor integrated circuit device. 4. When data is rewritten, a verify voltage appropriate for each sector or block is determined from the number of data rewrites for each sector or block in which data rewrite is performed, and based on the determination result. Selecting a verify voltage suitable for each sector or block unit from a plurality of verify voltage levels, switching the supply destination of the selected verify voltage, and outputting for each sector or block unit. Characteristic supply method of verify voltage. 5. A memory cell for comparison in which data is rewritten in advance at an arbitrary number of times when data is rewritten, and an arbitrary memory selected for each sector or block in the memory cell array in which data is to be rewritten. The read current with the cell is compared, and a verify voltage suitable for each sector or block unit is determined. Based on the determination result, verify voltages of a plurality of different voltage levels are determined for each sector or block unit. A verify voltage supply method, comprising selecting an appropriate verify voltage, switching the supply destination of the selected verify voltage, and outputting the selected verify voltage for each sector or block unit.