JP2001148192A - Semiconductor memory and word line drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such problems that hitherto, when a selection word line is continued, that is, as capability cannot help being decided supposing a case in which a load is maximum, a boosting circuit is operated exceeding actual word line current consumption and a current is consumed excessively, and also it is hard to apply the device to a memory LSI operated at high speed. SOLUTION: Word line transition is detected by an address latch 11, an EX-OR circuit 12, and an OR circuit 13 instead of boosting circuit voltage, and an output counter value of a counter 14 is varied. A boosting circuit 15 has such capability that the circuit receives the counter output value of the counter 14 and varies current capability supplied to a word driver 17, corresponding to the counter output value. As optimum current capability just enough is set to the boosting circuit 15 according to the magnitude of the load, power consumption can be suppressed. Also, the device is easily applied to the memory LSI which operates at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a word line driving method, and more particularly to a large-scale semiconductor integrated circuit.
The present invention relates to an (LSI) semiconductor memory device and a word line driving method.

[0002]

2. Description of the Related Art Conventionally, not only semiconductor memory devices (so-called memory LSIs) formed into LSIs but also LSIs are strongly required to have both low power supply voltage, low power consumption and high-speed operation. In general, lowering the power supply voltage causes a decrease in the operation speed. In particular, in the case of a memory LSI, a decrease in the voltage amplitude of the word driver significantly reduces the operation speed.

[0003] It is for the following reason. Since the memory cell transistor constituting the memory is the smallest in the chip, the threshold value Vt is higher than the other transistors. That is, the threshold value Vt is increased by the narrow channel effect or the substrate effect, or by the influence of the close proximity of the high concentration channel stopper. Further, the small size is liable to be affected by manufacturing variations such as dimensions, and the variation of the threshold value Vt is also increased. The word driver is required to have a voltage higher than the maximum threshold Vt. In other words, the voltage amplitude of the word driver greatly affects the operation speed, and a decrease in the voltage amplitude of the word driver significantly lowers the operation speed.

In order to solve this problem, a method has been proposed in which a high-level output voltage of a word driver is boosted from a power supply voltage to a high voltage by using a booster circuit. This method can maintain the potential of the selected word line high even if the power supply voltage is low, and is an effective method for speeding up. Two types of currents flow through this booster circuit.
One is a minute, almost constant reverse bias leak current flowing through the pn junction of the load. The second is a large transient current that flows when the memory is selected and the word driver operates. The former is a small and almost constant value of D
This is not a problem because it is a C current, but the latter has a large current value and a fluctuating AC current, and therefore must be sufficiently considered when designing a booster circuit.

The AC current depends on how much the selected word line transition occurs within a certain time. For example, 100
The AC current consumption greatly differs depending on whether the change accompanied by the selected word line transition is 50 or 100 times among the address changes. However, since the manner in which the address changes cannot be predicted, it is necessary to set the supply capacity of the booster circuit so as to exceed the maximum load, assuming the case where the load is selected in which different word lines are continuously selected. Absent.

If the current capability is insufficient and the high level output voltage of the word driver decreases, the potential of the selected word line decreases. In this case, not only the reading speed is reduced but also there is a possibility that an erroneous reading may occur. As described above, the load circuit always consumes a large current irrespective of the size of the load, which greatly hinders reduction in power consumption.

In order to solve this problem, a semiconductor memory device that monitors the level of the boosted voltage and varies the current output capability of the booster has been proposed (RCFosse).
t al., "Application of a High-Voltage Pumped Supply
for Low-Power DRAM "1992Symposium on VLSI Circui
ts Digest of Technical Papers, pp. 106-107).

FIG. 4 is a circuit diagram showing an example of the conventional semiconductor memory device. As shown in FIG. 1, the conventional semiconductor memory device includes a level monitor 1, a ring oscillator 2, and a booster 3. VDD is a power supply voltage, and VPP is a boosted power supply voltage. In this conventional device, VPP applied to a word line (not shown) of a dynamic random access memory (DRAM) is monitored by a level monitor 1, and when the voltage drops, a ring oscillator 2
Operate and the booster 3 boosts VPP.

Next, the operation of the conventional device will be described in detail. The enable signal is a signal that determines the operation / non-operation of the illustrated circuit. When the enable signal changes from a low level to a high level, the node a goes high and the gate voltage of the transistor QM becomes VPP. The transistor QM is a monitoring transistor having the same shape and dimensions as the memory cell and having a threshold value Vt.

When power supply voltage VPP is sufficiently high, VPP>
If (VDD + Vt), the transistor QM to which VDD is applied to the source conducts and the transistor Q1,
A current mirror circuit is formed by Q2. The current driving capability of the transistor Q2 is sufficiently larger than that of the transistors Q0 and Q0 ', and the VP voltage until the current starts flowing through the transistor Q2 due to the high level voltage of the node a.
If the P detection circuit is fast enough, the voltage at the node b at the drain of the transistor Q0 is maintained at a substantially high level. Therefore, the output voltage OSCEN of the inverter INV is kept at a low level, and the ring oscillator 2 is not started.

However, when the power supply voltage VPP is VPP <(V
DD + Vt), the electric charge at the node b is discharged through the transistors Q0 and Q0 'and the inverter IN
The V output voltage OSCEN becomes high level, and the ring oscillator 2 starts oscillating. When the ring oscillator 2 oscillates, the output signal OS of the ring oscillator 2
The following operation is performed when C alternates between a low level and a high level alternately.

First, the output signal OS of the ring oscillator 2
During the period in which C is at a low level, the nodes c, d, and e in the boosting unit 3 have been at a low level, so that the transistors Q3 and Q4 are on, and the node f at the drains of Q3 and Q4 , G are Q3 and Q4, respectively.
Were the source potentials VDD and VPP. However, since the signal OSC is at a low level, the nodes c, d, and e are both at a high level, the potential of the node f is 0 V, and the potential of the node g is (VDD-Vt5) (where Vt5 is the node g. (The threshold value of the transistor Q5 which is the drain)

At this time, since Q4 is off, when the node f discharges from VDD to 0V, the voltage fluctuates, so that the node g also fluctuates to a low level. (VDD-Vt
5) is held.

Next, the output signal O of the ring oscillator 2
During a period in which SC is at a high level, nodes c, d, and e are all at a low level, and node f is charged to VDD again. The node f is connected to the node g via the capacitor Cp.
(Common connection point of both drains of Q4 and Q5). At this time, since the transistor Q4 is on and the transistor Q5 is off, a charge corresponding to the change of the node f to the voltage VDD is supplied to VPP, and the potential of VPP rises. As described above, when the VPP decreases, the ring oscillator 2 starts oscillating, and the output signal OSC of the ring oscillator 2 alternately repeats the low level and the high level, so that the potential of the VPP is kept constant in the booster 3. Work is performed.

[0015]

However, FIG.
In the conventional semiconductor memory device shown in (1), since the operation is performed after the output voltage VPP of the boosting unit 3 is lowered, the semiconductor memory device is a high-speed operation LSI which requires a capability to react in a short time and increase the boosted voltage VPP. Is very difficult to apply.

The present invention has been made in view of the above points,
An object of the present invention is to provide a semiconductor memory device and a word line driving method which can be easily applied to a high-speed operation LSI by detecting a word line transition and controlling a booster circuit to suppress a voltage drop in advance.

[0017]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a step of applying a boosted voltage from a booster circuit to a selected one of word lines connected to a memory cell. In a semiconductor memory device supplied via a driver, a word line transition detection circuit for detecting a change in a selected word line, a counter for changing or maintaining an output count value in response to an output detection signal of the word line transition detection circuit , A booster circuit that receives the output count value and varies the current capability to be supplied to the word driver. In the present invention, instead of the booster circuit voltage,
By detecting a word line transition, it is possible to set an optimal current capacity in the booster circuit without excess or deficiency according to the size of the load.

Further, according to the present invention, when the selected word line transition continues, the output count value gradually changes in the first direction toward the first value in synchronization with the clock signal. Is continued, the output count value gradually changes toward the second value in the second direction opposite to the first direction in synchronization with the clock signal, and the booster circuit counts the count value. Changes in the first direction, the supply current capability increases in accordance with the count value, and the count value changes to the second value.
, The supply current capability is reduced in accordance with the count value.

According to another aspect of the present invention, there is provided a semiconductor device for supplying a boosted voltage from a booster circuit to a selected one of word lines connected to a memory cell via a word driver. In a word line driving method for a storage device, a change in a selected word line is detected, and an output count value of a counter is changed or maintained in accordance with a result of the detection, and supplied from a booster circuit to a word driver in accordance with the output count value. The current capability to be increased at least when the selected word line transition continues.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device according to the present invention. In the figure, an X-decode address signal A0 among the address input signals of the memory is latched by an address latch 11 synchronized with a clock signal CLK to be a signal A0L, and then a two-input exclusive-OR circuit (EX-OR) It is supplied to one input terminal of the circuit 12 and is directly supplied to the other input terminal of the EX-OR circuit 12.

Although not shown in FIG. 1 for convenience of illustration, each of the other X decode address signals A1 to An is also latched by a corresponding address latch similarly to the X decode address signal A0, and has a two-input EX-address. The signal is supplied to the OR circuit and directly to the two-input EX-OR circuit. The output signals of all (n + 1) address latches including the address latch 11 for latching the X decode address signals A0 to An are also supplied to the X decoder 16.

The address signals extracted from all (n + 1) EX-OR circuits including the EX-OR circuit 12 are O
The signal is commonly input to the counter 14 through the R circuit 13.
The counter 14 is a synchronous counter that counts in synchronization with a clock signal CLK, and outputs 0 immediately after reset. If the output signal of the OR circuit 13 is at a high level, the counter 14 performs a count-up operation in synchronization with the clock signal CLK until a constant value p, and after the output value becomes p, When the output signal is at a high level, the output value p is maintained.

On the other hand, if the output signal of the OR circuit 13 is at a low level, the counter 14 performs a countdown operation in synchronization with the clock signal CLK, and after the output value becomes 0, the output signal of the OR circuit 13 becomes When the level is low, the output value 0 is maintained.

The booster circuit 15 is a booster circuit with a variable supply current capability, and supplies the boosted power supply voltage to the word driver 17 via the power supply line 18. That is, the potential when the word line 19 connected to the memory cell (not shown) is selected becomes the potential supplied from the booster circuit 15 to the word driver 17. The booster circuit 15 has a function of receiving a counter output value of the counter 14 and varying a current capability to be supplied to the word driver 17 according to the counter output value.

FIG. 2 is a circuit diagram of an embodiment of the booster circuit 15. As shown in the figure, the booster circuit 15 includes two diode-connected N-channel MOS field-effect transistors M1 and M2 connected in series, and a connection point (node N) between the transistors M1 and M2 has a capacitor. One end of the CP is connected. This capacitor C
P is the pump-up capacity. Also, the transistor M
Each threshold of 1 and M2 is Vt, respectively.

The other end of the capacitor CP is connected to an output terminal of the frequency division ratio variable circuit 21. Dividing ratio variable circuit 21
Divides the input clock signal CLK to produce a capacitor CP
, And the frequency division ratio is determined by the counter 14 shown in FIG.
Is varied in accordance with the output count value. Here, for example, when the counter value is the maximum value p, the frequency division ratio is the minimum, the output signal frequency of the frequency division ratio variable circuit 21 is the highest, and when the minimum count value is 0, the frequency division ratio is the maximum, The output signal frequency of the frequency division ratio variable circuit 21 becomes the lowest. The power supply voltage VDD input to the transistor M1 is boosted from the transistor M2 and output to the VPP terminal. Here, for the sake of simplicity, the voltage limiter circuit for preventing excessive boosting is omitted. Note that the clock signal CLK is
This is a square wave in which a low level (GND) and a high level (VDD) are alternately repeated.

Next, the operation of this embodiment shown in FIGS. 1 and 2 will be described with reference to the timing chart of FIG. One of the X decoder address signals, for example, X
Consider a case where only the decoder address signal A0 changes. One cycle Φ0 of the clock signal CLK shown in FIG.
Then, the X-decoder address signal A0 changes from the low level (0) to the high level (1), and changes from the high level to the low level in the next cycle Φ1, so that the selected word line becomes as shown in FIG. And changes from W <0> to W <1>. At this time, the EX-OR circuit 1 to which the address signal A0 and the signal A0L obtained by latching by the address latch 11 are input.
The output signal of No. 2 is a pulse.

This output signal passes through the OR circuit 13 and
Is input to the counter 14 as a pulse waveform shown in FIG. 7, and the count value is counted up from 0 to 1 in synchronization with the clock during the high level period. Here, the address signal A0 has been described. However, when at least one of the X decode address signals changes, the pulse signal becomes OR.
It is taken out of the circuit 13 and inputted to the counter 14.
That is, when the selected word line changes, the counter 1
The output of 4 is counted up as shown in FIG.

The booster circuit 15 receives the output counter value of the counter 14 and increases the current capacity to be supplied to the word driver 17 by one step. Here, the operation of the booster circuit 15 shown in FIG. 2 will be described. When the frequency-divided clock signal output from the frequency-division-ratio variable circuit 21 is at a low level (GND), current flows from VDD to the node N through the transistor M1. Flows, and the potential of the node N becomes (VDD−V
t). Subsequently, when the frequency-divided clock signal goes high (VDD), coupling occurs at both ends of the capacitor CP (the potential difference between both ends is (VDD−Vt)).
), The potential of the node N is higher than VDD, so that the current does not flow to the VDD terminal due to the operation of the transistor M1, but flows in the direction of the VPP terminal, and the VPP terminal has a maximum of 2 (V
DD-Vt).

By continuing to supply the clock signal in this way, the above state is repeated, and the VPP terminal
(VDD-Vt) is maintained at the boosted potential. Further, the repetition of the above state changes according to the count value.

When the selected word line changes, the consumed AC current also increases. However, if the supply current capability is set to increase without excess or deficiency, the booster circuit 15 consumes excessive current. Without doing so, the high level of the word driver 17, that is, the selected word line potential is maintained at a constant value.

Further, as shown in FIG. 3, the clock changes from Φ1 to Φ2 and the word line transition continues,
Even if the AC current consumption further increases, the supply current capability of the booster circuit 15 increases as shown in FIG. 3 as the output counter value of the counter 14 increases, so that the optimum current consumption and the selected word line potential are reduced. Will be kept.

On the other hand, in three successive clock cycles of Φ3, Φ4, and Φ5 shown in FIG.
0 is maintained at a high level, and the same word line selection is continued. In this case, the AC current consumption of the word driver 17 is reduced. In this case, the output counter value of the counter 14 is counted down from 2 → 1 → 0 as shown in FIG.
The current supply capacity is reduced, and the booster circuit 15 operates so as not to consume excessive current.

As described above, when the transition of the selected word line is continuous, the counter 14 performs the count-up operation, but it is physically impossible to increase the count output value infinitely and to increase the power supply capability. Impossible. Therefore, the configuration is such that when the count-up is performed at a certain value or more, the count output value is kept at a constant value thereafter. In FIG. 3, when Φ2 → Φ3 is in that state, if the count value becomes 2 or more, that is, if the selected word line change occurs three or more times continuously, the count output value of the counter 14 remains at 2.

In this case, even if the change of the selected word line is repeated three or more times, the setting of changing the dimension of the booster circuit 15 may be set so that the word line AC current consumption can be sufficiently supplied. Specifically, for example, the capacitor C shown in FIG.
It is conceivable that a plurality of Ps are prepared, and a P having a small capacity is usually used, and a P having a large capacity is used when the load increases.

In the above-described embodiment, the same applies to the case where the selected word line transition does not occur, that is, the case where the same word line is continuously selected. For example, when the counter output value becomes 0, it is maintained at 0 thereafter, and the state where the current consumption of the booster circuit 15 is the lowest is continued.

As described above, in this embodiment, the transition of the word line is detected, and the output counter value of the counter 14 that operates so as to change or maintain the output value in accordance with the magnitude of the load is supplied to the booster circuit 15. Since the current capacity to be supplied and supplied to the word driver 17 is set to an optimum current capacity without excess or deficiency, unnecessary power consumption can be suppressed and the boosted voltage can be kept constant. In addition, since the word line transition is detected instead of the booster circuit voltage and the booster circuit 15 is controlled to suppress the voltage drop in advance, it is not necessary to react in a short time.

The booster circuit 15 in which the current capacity to be supplied changes according to the output value of the counter has several realizing methods other than the configuration shown in FIG. For example, a configuration is conceivable in which the dimensions of a transistor, a resistor, and the like that constitute the booster circuit 15 are made variable according to the output count value of the counter 14. Both are easy to realize.

The present invention is not limited to the above embodiment. For example, the transistors M1 and M2 shown in FIG. 2 are diode-connected in order to function as diodes, but are functionally equivalent. Therefore, it is possible to use not only a diode but also a transistor having a gate to which a clock signal is input and a structure equivalent to the case of using a diode, which includes all diode elements. Further, it is needless to say that the transistors M1 and M2 may be field effect transistors other than MOS transistors or bipolar transistors.

[0040]

As described above, according to the present invention,
Instead of the booster circuit voltage, the word line transition is detected, and the optimum current capacity without excess or deficiency is set in the booster circuit in accordance with the size of the load. Since the capacity must be determined assuming the case of the maximum load, the phenomenon that the booster circuit operates exceeding the actual word line current consumption and consumes excessive current can be prevented. Can be kept constant.

Further, according to the present invention, the voltage drop is suppressed in advance by detecting the word line transition and controlling the booster circuit. It is easy to apply to a memory LSI that performs low voltage, low power consumption and high speed operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of one embodiment of a booster circuit in FIG. 1;

FIG. 3 is a timing chart for explaining the operation of FIG. 1;

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Address latch 12 Exclusive OR circuit (EX-OR circuit) 13 OR circuit 14 Counter 15 Booster circuit 16 X decoder 17 Word driver 19 Word line 21 Dividing ratio variable circuit M1, M2 N channel MOS field effect transistor CP capacitor (Pump-up capacity)

Claims (6)

[Claims] 1. A semiconductor memory device that supplies a boosted voltage from a booster circuit to a selected word line among word lines connected to a memory cell via a word driver, and detects a change in the selected word line. A word line transition detection circuit, a counter for changing or maintaining an output count value in response to an output detection signal of the word line transition detection circuit, and varying a current capability of receiving the output count value and supplying the word driver. A semiconductor memory device having a booster circuit. 2. The method according to claim 1, wherein the word line transition detection circuit includes a plurality of X lines.
A plurality of address latches for separately latching each of the decoder address signals in synchronization with a clock signal; a plurality of logic circuits for detecting a change in an output signal of the address latch and a corresponding X decoder address signal; 2. The semiconductor memory device according to claim 1, comprising a single OR circuit that performs an OR operation on an output signal of the logic circuit. 3. When the selected word line transition continues, the counter gradually changes the output count value in the first direction toward the first value in synchronization with the clock signal, and Are continuously generated, the output count value gradually changes toward a second value in a second direction opposite to the first direction in synchronization with the clock signal, and the booster circuit outputs the count value. When the current value changes in the first direction, the supply current capability increases in accordance with the count value, and when the count value changes in the second direction, the supply current capability decreases in accordance with the count value. 2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device has a configuration. 4. The booster circuit outputs a first diode element having one end connected to a power supply voltage, and a power supply voltage boosted by receiving the power supply voltage from the first diode element. A second diode element connected in series to the first diode element, a capacitor having one end connected to a connection point between the first and second diode elements, and an output count value of the counter connected to the other end of the capacitor. 2. The semiconductor memory device according to claim 1, further comprising supply means for supplying a clock signal having a frequency that changes according to the time. 5. The semiconductor memory device according to claim 4, wherein a dimension of said capacitor is changed according to an output count value of said counter instead of said capacitor. 6. A word line driving method for a semiconductor memory device, which supplies a boosted voltage from a booster circuit to a selected word line among word lines connected to a memory cell via a word driver. Line change is detected, the output count value of the counter is changed or maintained in accordance with the detection result, and the current capability to be supplied from the booster circuit to the word driver in accordance with the output count value is at least selected word line transition. A word line driving method characterized in that the word line is varied so as to rise when continues.